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Sun, 16 Feb 2025 22:34:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IHZ7gToBq7D4VtpV2EASi1+JDe5Y5Jkt/4aGWzWeA8pKMBeCH8FZhkAAVk6ksqeb0q+oCvNuA== X-Received: by 2002:a05:6a21:2d87:b0:1ee:43c3:9bfa with SMTP id adf61e73a8af0-1ee8cc16ab5mr16622835637.35.1739774067507; Sun, 16 Feb 2025 22:34:27 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73263b79287sm3771800b3a.29.2025.02.16.22.34.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Feb 2025 22:34:27 -0800 (PST) From: Krishna Chaitanya Chundru Date: Mon, 17 Feb 2025 12:04:09 +0530 Subject: [PATCH 2/8] PCI/bwctrl: Add support to scale bandwidth before & after link re-training Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250217-mhi_bw_up-v1-2-9bad1e42bdb1@oss.qualcomm.com> References: <20250217-mhi_bw_up-v1-0-9bad1e42bdb1@oss.qualcomm.com> In-Reply-To: <20250217-mhi_bw_up-v1-0-9bad1e42bdb1@oss.qualcomm.com> To: Bjorn Helgaas , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Johannes Berg , Jeff Johnson Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev, linux-wireless@vger.kernel.org, ath11k@lists.infradead.org, quic_jjohnson@quicinc.com, quic_pyarlaga@quicinc.com, quic_vbadigan@quicinc.com, quic_vpernami@quicinc.com, quic_mrana@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739774050; l=3068; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=UOzsnW0yk1kCZhcOHUKzAXiM1zBrG/5KAYYsM43pKTM=; b=xi2H5j+IGrnLH2KW01vOyRK0v1mmhX6st6biV7Tank1/vHMoUUt8rpVtOT60WK8uXuBhj8yK3 8x2ATQZIgedBNLlXYuqyCQVT/znFmyy+9q/E+GmWNi3TPK/ehbPnrMA X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: 1KCUPjTHsdQCs3qH8KvYeb-20M1yBJ7b X-Proofpoint-ORIG-GUID: 1KCUPjTHsdQCs3qH8KvYeb-20M1yBJ7b X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-17_03,2025-02-13_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 malwarescore=0 phishscore=0 spamscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502170056 If the driver wants to move to higher data rate/speed than the current data rate then the controller driver may need to change certain votes so that link may come up at requested data rate/speed like QCOM PCIe controllers need to change their RPMh (Resource Power Manager-hardened) state. Once link retraining is done controller drivers needs to adjust their votes based on the final data rate. Some controllers also may need to update their bandwidth voting like ICC bw votings etc. So, add pre_scale_bus_bw() & post_scale_bus_bw() op to call before & after the link re-train. In case of PCIe switch, if there is a request to change target speed for a downstream port then no need to call these function ops as these are outside the scope of the controller drivers. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/pcie/bwctrl.c | 15 +++++++++++++++ include/linux/pci.h | 2 ++ 2 files changed, 17 insertions(+) diff --git a/drivers/pci/pcie/bwctrl.c b/drivers/pci/pcie/bwctrl.c index 0a5e7efbce2c..e3faa4d1f935 100644 --- a/drivers/pci/pcie/bwctrl.c +++ b/drivers/pci/pcie/bwctrl.c @@ -161,6 +161,8 @@ static int pcie_bwctrl_change_speed(struct pci_dev *por= t, u16 target_speed, bool int pcie_set_target_speed(struct pci_dev *port, enum pci_bus_speed speed_r= eq, bool use_lt) { + struct pci_host_bridge *host =3D pci_find_host_bridge(port->bus); + bool is_root =3D pci_is_root_bus(port->bus); struct pci_bus *bus =3D port->subordinate; u16 target_speed; int ret; @@ -173,6 +175,16 @@ int pcie_set_target_speed(struct pci_dev *port, enum p= ci_bus_speed speed_req, =20 target_speed =3D pcie_bwctrl_select_speed(port, speed_req); =20 + /* + * The controller driver may need to be scaled for targeted speed + * otherwise link might not come up at requested speed. + */ + if (is_root && host->ops->pre_scale_bus_bw) { + ret =3D host->ops->pre_scale_bus_bw(host->bus, target_speed); + if (ret) + return ret; + } + scoped_guard(rwsem_read, &pcie_bwctrl_setspeed_rwsem) { struct pcie_bwctrl_data *data =3D port->link_bwctrl; =20 @@ -197,6 +209,9 @@ int pcie_set_target_speed(struct pci_dev *port, enum pc= i_bus_speed speed_req, !list_empty(&bus->devices)) ret =3D -EAGAIN; =20 + if (is_root && host->ops->post_scale_bus_bw) + host->ops->post_scale_bus_bw(host->bus, pci_bus_speed2lnkctl2(bus->cur_b= us_speed)); + return ret; } =20 diff --git a/include/linux/pci.h b/include/linux/pci.h index 47b31ad724fa..58f1de626c37 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -804,6 +804,8 @@ struct pci_ops { void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int whe= re); int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size,= u32 *val); int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size= , u32 val); + int (*pre_scale_bus_bw)(struct pci_bus *bus, int target_speed); + void (*post_scale_bus_bw)(struct pci_bus *bus, int current_speed); }; =20 /* --=20 2.34.1