From nobody Fri Dec 19 12:19:25 2025 Received: from sendmail.purelymail.com (sendmail.purelymail.com [34.202.193.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC90922DFBF for ; Mon, 17 Feb 2025 19:06:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=34.202.193.197 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739819200; cv=none; b=WmveaceCiOTiJnrBzr02QcPqMd+6n89NjMyfNT2UbnNHryxw1HMfF/pSQbg0+/4HUI/VRybchWMkJDQi2OYQ6fjucEzmOk2vKVbh4HmbfqX7y4RQybHwm/lL5VIX4oi19/fulPgxyzUqsZF7EpMezMhRYS99WFr+mzaNrZXuRvU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739819200; c=relaxed/simple; bh=ExVaCUBzcNC+wkHRkApsOynmUd07dvbz0C9qAwKk5Qg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=S9lXVilQlUMQ6Vj9/UYlZhiVQ+5cnH+iierjqPZoLaQ6FnfAyWU5I+yx9dZV+72/BnUDVqYYbR0dE8tIK9nbdZLDx+fRtiOm/Ool5NNONZavKYNpz/F3k4iNWhyrWZLMVjbxmf9kTFnizRJ3TRgToB7I3lSZ7I3z5UJRp+CHzIY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org; spf=pass smtp.mailfrom=mentallysanemainliners.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b=gEabBLK4; arc=none smtp.client-ip=34.202.193.197 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mentallysanemainliners.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=purelymail.com header.i=@purelymail.com header.b="gEabBLK4" Authentication-Results: purelymail.com; auth=pass DKIM-Signature: a=rsa-sha256; b=gEabBLK4/OW9lEl+1Pr1HTKx6Hj3IzZhsCCbDu3V6Y6hfw9uvxvbexfvobOgE8xgDizX9/PfVRefb5BN5HCS7P5u9eHT/zFz3JMpCVm1MLOg1xjWqvFROWo4wjM7fXeFJd+9VW39qF6DCqeovJrcA4FHdXqYvG8hIbcvy3oPnZR4K3LmXA75xw4o4V6ts5aGp/FjhiHCLQQF5vmmrZjc78Zzy6JT+hC9tU+bu8LJY2y7Zww5uvVJHY0UnnyWBCNTGo/G4aLWRDMSFbCLMfXs78evUtYpzREZo8Um0Z+htB8xxix4CFqMQS54pCHFa2z2a4cQLbksX+STb8V3d+hM+w==; s=purelymail3; d=purelymail.com; v=1; bh=ExVaCUBzcNC+wkHRkApsOynmUd07dvbz0C9qAwKk5Qg=; h=Feedback-ID:Received:From:Date:Subject:To; Feedback-ID: 68247:10037:null:purelymail X-Pm-Original-To: linux-kernel@vger.kernel.org Received: by smtp.purelymail.com (Purelymail SMTP) with ESMTPSA id -1350358103; (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 17 Feb 2025 19:05:53 +0000 (UTC) From: Igor Belwon Date: Mon, 17 Feb 2025 20:05:19 +0100 Subject: [PATCH 1/2] dt-bindings: watchdog: samsung-wdt: Add exynos990-wdt compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250217-exynos990-wdt-v1-1-9b49df5256b0@mentallysanemainliners.org> References: <20250217-exynos990-wdt-v1-0-9b49df5256b0@mentallysanemainliners.org> In-Reply-To: <20250217-exynos990-wdt-v1-0-9b49df5256b0@mentallysanemainliners.org> To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Krzysztof Kozlowski , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Igor Belwon X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739819149; l=2481; i=igor.belwon@mentallysanemainliners.org; s=20241206; h=from:subject:message-id; bh=ExVaCUBzcNC+wkHRkApsOynmUd07dvbz0C9qAwKk5Qg=; b=mRkJpujMaWtYA215YBhSum3Q3+AFasnoTKmdWZixH/WWoYNb5mwvZeJo5hqxbqv0/xSMMiEtf M+WhVBsl/ZqDEKKLNTpStdiPv6c9fwSWBzXeGvHQ1sQaSV2zg9nPTvY X-Developer-Key: i=igor.belwon@mentallysanemainliners.org; a=ed25519; pk=qKAuSTWKTaGQM0vwBxV0p6hPKMN4vh0CwZ+bozrG5lY= Add a dt-binding compatible for the Exynos990 Watchdog timer. This watchdog is compatible with the GS101/Exynos850 design, as such it requires the cluster-index and syscon-phandle properties to be present. Signed-off-by: Igor Belwon --- Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/= Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml index d175ae9683366d33b1f9d9d820501d1e7c5964bd..e36f87830ea8a185a1543e62fde= ebd97fb9a8abb 100644 --- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml @@ -25,6 +25,7 @@ properties: - samsung,exynos5420-wdt # for Exynos5420 - samsung,exynos7-wdt # for Exynos7 - samsung,exynos850-wdt # for Exynos850 + - samsung,exynos990-wdt # for Exynos990 - samsung,exynosautov9-wdt # for Exynosautov9 - samsung,exynosautov920-wdt # for Exynosautov920 - items: @@ -49,14 +50,14 @@ properties: samsung,cluster-index: $ref: /schemas/types.yaml#/definitions/uint32 description: - Index of CPU cluster on which watchdog is running (in case of Exynos= 850 - or Google gs101). + Index of CPU cluster on which watchdog is running (in case of Exynos= 850, + Exynos990 or Google gs101). =20 samsung,syscon-phandle: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to the PMU system controller node (in case of Exynos5250, - Exynos5420, Exynos7, Exynos850 and gs101). + Exynos5420, Exynos7, Exynos850, Exynos990 and gs101). =20 required: - compatible @@ -77,6 +78,7 @@ allOf: - samsung,exynos5420-wdt - samsung,exynos7-wdt - samsung,exynos850-wdt + - samsung,exynos990-wdt - samsung,exynosautov9-wdt - samsung,exynosautov920-wdt then: @@ -89,6 +91,7 @@ allOf: enum: - google,gs101-wdt - samsung,exynos850-wdt + - samsung,exynos990-wdt - samsung,exynosautov9-wdt - samsung,exynosautov920-wdt then: --=20 2.47.2 From nobody Fri Dec 19 12:19:25 2025 Received: from sendmail.purelymail.com (sendmail.purelymail.com [34.202.193.197]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18551188587 for ; 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(version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384); Mon, 17 Feb 2025 19:05:55 +0000 (UTC) From: Igor Belwon Date: Mon, 17 Feb 2025 20:05:20 +0100 Subject: [PATCH 2/2] watchdog: s3c2410_wdt: Add exynos990-wdt compatible data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250217-exynos990-wdt-v1-2-9b49df5256b0@mentallysanemainliners.org> References: <20250217-exynos990-wdt-v1-0-9b49df5256b0@mentallysanemainliners.org> In-Reply-To: <20250217-exynos990-wdt-v1-0-9b49df5256b0@mentallysanemainliners.org> To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Krzysztof Kozlowski , linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, Igor Belwon X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1739819149; l=3489; i=igor.belwon@mentallysanemainliners.org; s=20241206; h=from:subject:message-id; bh=ooAfCtIBB4Gn/GKkD7UJYql1T65TueuYbZ/OTNt6n3I=; b=52j0yL0JmFDhHfLO0JNk1R4BLqQFJ1/n/TFVE18WHMD956oD9C47L+KT7I/Ut+ber7hp79cAP 3N50GSYq4boCc9Ac1YhpDcQUnoNRBqqcpV8rOHzyNclwKk1p1AZUywg X-Developer-Key: i=igor.belwon@mentallysanemainliners.org; a=ed25519; pk=qKAuSTWKTaGQM0vwBxV0p6hPKMN4vh0CwZ+bozrG5lY= The Exynos990 has two watchdog clusters - cl0 and cl2. Add new driver data for these two clusters, making it possible to use the watchdog timer on this SoC. Signed-off-by: Igor Belwon --- drivers/watchdog/s3c2410_wdt.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c index 30450e99e5e9d40b5596e2f87cc47c80ccbd2ddd..8f406e08d848646348dafabced5= bc0f2bbcf49df 100644 --- a/drivers/watchdog/s3c2410_wdt.c +++ b/drivers/watchdog/s3c2410_wdt.c @@ -80,6 +80,10 @@ #define GS_CLUSTER2_NONCPU_INT_EN 0x1644 #define GS_RST_STAT_REG_OFFSET 0x3B44 =20 +#define EXYNOS990_CLUSTER2_NONCPU_OUT 0x1620 +#define EXYNOS990_CLUSTER2_NONCPU_INT_EN 0x1644 +#define EXYNOS990_CLUSTER2_WDTRESET_BIT 23 + /** * DOC: Quirk flags for different Samsung watchdog IP-cores * @@ -257,6 +261,32 @@ static const struct s3c2410_wdt_variant drv_data_exyno= s850_cl1 =3D { QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN, }; =20 +static const struct s3c2410_wdt_variant drv_data_exynos990_cl0 =3D { + .mask_reset_reg =3D GS_CLUSTER0_NONCPU_INT_EN, + .mask_bit =3D 2, + .mask_reset_inv =3D true, + .rst_stat_reg =3D EXYNOS5_RST_STAT_REG_OFFSET, + .rst_stat_bit =3D EXYNOS850_CLUSTER0_WDTRESET_BIT, + .cnt_en_reg =3D EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT, + .cnt_en_bit =3D 7, + .quirks =3D QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | + QUIRK_HAS_DBGACK_BIT, +}; + +static const struct s3c2410_wdt_variant drv_data_exynos990_cl2 =3D { + .mask_reset_reg =3D EXYNOS990_CLUSTER2_NONCPU_INT_EN, + .mask_bit =3D 2, + .mask_reset_inv =3D true, + .rst_stat_reg =3D EXYNOS5_RST_STAT_REG_OFFSET, + .rst_stat_bit =3D EXYNOS990_CLUSTER2_WDTRESET_BIT, + .cnt_en_reg =3D EXYNOS990_CLUSTER2_NONCPU_OUT, + .cnt_en_bit =3D 7, + .quirks =3D QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET | + QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN | + QUIRK_HAS_DBGACK_BIT, +}; + static const struct s3c2410_wdt_variant drv_data_exynosautov9_cl0 =3D { .mask_reset_reg =3D EXYNOS850_CLUSTER0_NONCPU_INT_EN, .mask_bit =3D 2, @@ -348,6 +378,8 @@ static const struct of_device_id s3c2410_wdt_match[] = =3D { .data =3D &drv_data_exynos7 }, { .compatible =3D "samsung,exynos850-wdt", .data =3D &drv_data_exynos850_cl0 }, + { .compatible =3D "samsung,exynos990-wdt", + .data =3D &drv_data_exynos990_cl0 }, { .compatible =3D "samsung,exynosautov9-wdt", .data =3D &drv_data_exynosautov9_cl0 }, { .compatible =3D "samsung,exynosautov920-wdt", @@ -676,7 +708,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, = struct s3c2410_wdt *wdt) if (variant =3D=3D &drv_data_exynos850_cl0 || variant =3D=3D &drv_data_exynosautov9_cl0 || variant =3D=3D &drv_data_gs101_cl0 || - variant =3D=3D &drv_data_exynosautov920_cl0) { + variant =3D=3D &drv_data_exynosautov920_cl0 || + variant =3D=3D &drv_data_exynos990_cl0) { u32 index; int err; =20 @@ -698,6 +731,10 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev,= struct s3c2410_wdt *wdt) else if (variant =3D=3D &drv_data_exynosautov920_cl0) variant =3D &drv_data_exynosautov920_cl1; break; + case 2: + if (variant =3D=3D &drv_data_exynos990_cl0) + variant =3D &drv_data_exynos990_cl2; + break; default: return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index); } --=20 2.47.2