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charset="utf-8" Some controllers and endpoints provide provision to program the entry delays of L0s & L1 which will allow the link to enter L0s & L1 more aggressively to save power. These values needs to be programmed before link training. Signed-off-by: Krishna Chaitanya Chundru --- dtschema/schemas/pci/pci-bus-common.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pc= i/pci-bus-common.yaml index 94b648f..a9309af 100644 --- a/dtschema/schemas/pci/pci-bus-common.yaml +++ b/dtschema/schemas/pci/pci-bus-common.yaml @@ -150,6 +150,12 @@ properties: description: Disables ASPM L0s capability type: boolean =20 + aspm-l0s-entry-delay-ns: + description: ASPM L0s entry delay + + aspm-l1-entry-delay-ns: + description: ASPM L1 entry delay + vpcie12v-supply: description: 12v regulator phandle for the slot =20 --=20 2.34.1 From nobody Fri Dec 19 15:20:43 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2FB0C2BB13 for ; Sun, 16 Feb 2025 01:45:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Per PCIe r6.0, sec 4.2.5.1, during Link training, a PCIe component captures the N_FTS value it receives. Per 4.2.5.6, when transitioning the Link from L0s to L0, it must transmit N_FTS Fast Training Sequences to enable the receiver to obtain bit and Symbol lock. Components may have device-specific ways to configure N_FTS values to advertise during Link training. Define an n_fts array with an entry for each supported data rate. Signed-off-by: Krishna Chaitanya Chundru --- dtschema/schemas/pci/pci-bus-common.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/dtschema/schemas/pci/pci-bus-common.yaml b/dtschema/schemas/pc= i/pci-bus-common.yaml index a9309af..ca97a00 100644 --- a/dtschema/schemas/pci/pci-bus-common.yaml +++ b/dtschema/schemas/pci/pci-bus-common.yaml @@ -128,6 +128,16 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [ 1, 2, 4, 8, 16, 32 ] =20 + n-fts: + description: + The number of Fast Training Sequences (N_FTS) required by the + Receiver (this component) when transitioning the Link from L0s + to L0; advertised during initial Link training. Each entry in + the array specifies a PCIe data rate + $ref: /schemas/types.yaml#/definitions/uint8-array + minItems: 1 + maxItems: 5 + reset-gpios: description: GPIO controlled connection to PERST# signal maxItems: 1 --=20 2.34.1