From nobody Fri Dec 19 15:17:03 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0494B1FDA7C; Sat, 15 Feb 2025 23:55:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739663711; cv=pass; b=inwe33TQzGBfecSZtZHuo25xPyImmNR63cGebQgWyxI9MScj5kRuNRq2S1ldOhDP4vehv5F0r7U3soQEfgY+Yb4GgPQSx5sL1yY1qzPPsLJQdXd3QSFwJF/WzyFGxAjcM3Yoy+kOMzOI3zMPYtYh9GSNLlqOysRpKzk+CjHncwA= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739663711; c=relaxed/simple; bh=yZI9YkppnA4Jrt7zIZ8DGmdRDeuDKuobF+K2ibWtqEc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KKfx/iPDfxJ+iD6z6VQalwhwz/dW8GAqByZoRws5VYBZjDULqB+O4UXDfpVbtOqb9f7uwZcps/AwfQdsT5gKxU2EgBYrpEt1TnY5fkgJvF6Mwi7ceZeOXA2vQU6b15bepJljGyTyeuOJCrVEPZvSCepZgUR4uYZisct6x0gP2zE= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=dmitry.osipenko@collabora.com header.b=cq7SsNZh; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=dmitry.osipenko@collabora.com header.b="cq7SsNZh" ARC-Seal: i=1; a=rsa-sha256; t=1739663686; cv=none; d=zohomail.com; s=zohoarc; b=Xzszj1H9esnDOxaT7RtmpY0fJVWJpM5duJudkMNLr/EM/Gvcr7/ap1lVv1FaKPkyZorODjnLtgSKBS9kiKCU20DOobjw+fWwEOuGIOmfWy1GYFz8rPJ9hnxBGeQRk1iFPLTIFkK/6d5XsoAXZb0Zfr3HjMPaw9VBIoQzamK+2Fs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1739663686; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=Rg2lRKuMuur32yytc+cosmJNyARibhGFTS7jn14DKBw=; b=nmiwRwC7ZD1Cce/YzEICyeDQsKgaLEvDElqUe5K8D7ItqvlxNc6r94VnMFOhtK5MCx5fGYfOO+FJjwKjbzEhYh+e16t699jYb3Z6ER+myIek2drT/gLhLClhDYkABnhbNTeCgzuyt+OzfmOMQFCm169fe6UUy33MEf5w2la9F7g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=dmitry.osipenko@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1739663686; s=zohomail; d=collabora.com; i=dmitry.osipenko@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=Rg2lRKuMuur32yytc+cosmJNyARibhGFTS7jn14DKBw=; b=cq7SsNZhdvFjqITiwXM1Cdr4UQXV6/7+PB+Fp1MYCrtgzXMd9SWQf/5Za4l2E/Dw aXZMn5wlRkB4emkpx13kWzoKs3izrL5j6J9KJm+5X0VHFwYuVkSaHScl/tno3/7hzBr ciQxiJt5MyjKWkgu9OWRWm1anOv279+Vfm66Lmto= Received: by mx.zohomail.com with SMTPS id 1739663684002695.9780529795356; Sat, 15 Feb 2025 15:54:44 -0800 (PST) From: Dmitry Osipenko To: Heiko Stuebner , Marc Zyngier Cc: Rob Herring , Krzysztof Kozlowski , Thomas Gleixner , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Kever Yang , XiaoDong Huang , Peter Geis , Robin Murphy , kernel@collabora.com Subject: [PATCH v1 1/4] irqchip/gic-v3: Add Rockchip 3568002 erratum workaround Date: Sun, 16 Feb 2025 02:54:28 +0300 Message-ID: <20250215235431.143138-2-dmitry.osipenko@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250215235431.143138-1-dmitry.osipenko@collabora.com> References: <20250215235431.143138-1-dmitry.osipenko@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" Rockchip RK3566/RK3568 GIC600 integration has DDR addressing limited to first 4GB of DRAM. Rockchip assigned Erratum ID #3568002 for this issue. Add driver quirk for this Rockchip GIC Erratum. Note, that the 0x0201743b ID is not Rockchip 356x specific and thus there is an extra of_machine_is_compatible() check. Rockchip 3588 uses same ID and it is not affected by this errata. Signed-off-by: Dmitry Osipenko Acked-by: Marc Zyngier --- Documentation/arch/arm64/silicon-errata.rst | 2 ++ arch/arm64/Kconfig | 9 ++++++++ drivers/irqchip/irq-gic-v3-its.c | 23 ++++++++++++++++++++- 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/ar= ch/arm64/silicon-errata.rst index f074f6219f5c..f968c13b46a7 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -284,6 +284,8 @@ stable kernels. +----------------+-----------------+-----------------+--------------------= ---------+ | Rockchip | RK3588 | #3588001 | ROCKCHIP_ERRATUM_35= 88001 | +----------------+-----------------+-----------------+--------------------= ---------+ +| Rockchip | RK3568 | #3568002 | ROCKCHIP_ERRATUM_35= 68002 | ++----------------+-----------------+-----------------+--------------------= ---------+ +----------------+-----------------+-----------------+--------------------= ---------+ | Fujitsu | A64FX | E#010001 | FUJITSU_ERRATUM_010= 001 | +----------------+-----------------+-----------------+--------------------= ---------+ diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index c997b27b7da1..0428ad8f324d 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -1302,6 +1302,15 @@ config NVIDIA_CARMEL_CNP_ERRATUM =20 If unsure, say Y. =20 +config ROCKCHIP_ERRATUM_3568002 + bool "Rockchip 3568002: can not support DDR addresses higher than 4G" + default y + help + The Rockchip RK3566 and RK3568 GIC600 SoC integrations have DDR + addressing limited to first 4GB. + + If unsure, say Y. + config ROCKCHIP_ERRATUM_3588001 bool "Rockchip 3588001: GIC600 can not support shareability attributes" default y diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-= its.c index 8c3ec5734f1e..f30ed281882f 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -205,13 +205,15 @@ static DEFINE_IDA(its_vpeid_ida); #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) #define gic_data_rdist_vlpi_base() (gic_data_rdist_rd_base() + SZ_128K) =20 +static gfp_t gfp_flags_quirk; + static struct page *its_alloc_pages_node(int node, gfp_t gfp, unsigned int order) { struct page *page; int ret =3D 0; =20 - page =3D alloc_pages_node(node, gfp, order); + page =3D alloc_pages_node(node, gfp | gfp_flags_quirk, order); =20 if (!page) return NULL; @@ -4887,6 +4889,17 @@ static bool __maybe_unused its_enable_quirk_hip09_16= 2100801(void *data) return true; } =20 +static bool __maybe_unused its_enable_rk3568002(void *data) +{ + if (!of_machine_is_compatible("rockchip,rk3566") && + !of_machine_is_compatible("rockchip,rk3568")) + return false; + + gfp_flags_quirk |=3D GFP_DMA32; + + return true; +} + static const struct gic_quirk its_quirks[] =3D { #ifdef CONFIG_CAVIUM_ERRATUM_22375 { @@ -4954,6 +4967,14 @@ static const struct gic_quirk its_quirks[] =3D { .property =3D "dma-noncoherent", .init =3D its_set_non_coherent, }, +#ifdef CONFIG_ROCKCHIP_ERRATUM_3568002 + { + .desc =3D "ITS: Rockchip erratum RK3568002", + .iidr =3D 0x0201743b, + .mask =3D 0xffffffff, + .init =3D its_enable_rk3568002, + }, +#endif { } }; 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charset="utf-8" Rockchip 3566/8 SoCs are affected by the GIC integration issue where GIC reports that it supports programmable shareability in a feature register, while in fact it doesn't support this feature. Rockchip assigned Errata ID #3568001 for the issue. Add dma-noncoherent GIC property, denoting that a SW quirk is required for the GIC. Signed-off-by: Dmitry Osipenko --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index de5e6c0c3d24..28be38b7182e 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -284,6 +284,7 @@ gic: interrupt-controller@fd400000 { mbi-alias =3D <0x0 0xfd410000>; mbi-ranges =3D <296 24>; msi-controller; + dma-noncoherent; }; =20 usb_host0_ehci: usb@fd800000 { --=20 2.48.1 From nobody Fri Dec 19 15:17:03 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18A2D1FE444; Sat, 15 Feb 2025 23:55:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=pass smtp.client-ip=136.143.188.112 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739663716; cv=pass; b=LxZxJkrhN393AgLI1GPgqZWjRCfkjGTal2RQostl0+4NT8PvGTBvOHL01B9EL/I644pQvKh0e8QvgOg/w75i+QIgHN6UyiaLw9N2qgxl54f0CrJXlKxUEwMPEd41Yajp4rmvg3cxPpv6XuHnTO+1UpdhTXJzdp9Q3Eti+ETlTuw= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739663716; c=relaxed/simple; bh=XdBLsGtN/7xOlNbFtrN52dU7LE5bMVG+nKHZ4Fs5sTM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=K0tOIN7yPDa8Rcl9Qw/KbM0SO+yUYXPiZM+TLYJj0HRvlpFxwulZ3JkUgxum7JpZ3z/k2STkxfS7ylmfJnezfgnvrmt92GLc3R+KTlLJ0ERQO+x6xzGd+BaOXUk/tqc1ZvX+TU+aIbiJ9OnGJkvMBZhAenuu7wUL1C4iQ9JJcCk= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (1024-bit key) header.d=collabora.com header.i=dmitry.osipenko@collabora.com header.b=GYo6xfTY; arc=pass smtp.client-ip=136.143.188.112 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=collabora.com header.i=dmitry.osipenko@collabora.com header.b="GYo6xfTY" ARC-Seal: i=1; a=rsa-sha256; t=1739663692; cv=none; d=zohomail.com; s=zohoarc; b=HhXDMQpra6W+3UXNuLbuAQzVukz2AnpaULYHdn7SHlffKEvcXDIlmpOnwK7l38SkXTvGF33igzqOpfPMHcVRGCwpWyD9c696ldWAskNmUBS8oyIbZia94MMyLQ7SKG//8Hiu7Q0HQXPG/F9g/jCCw0IyYZTNrUsB6yucdUVcxZI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1739663692; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:Subject:To:To:Message-Id:Reply-To; bh=bk824fFEtJ4JFX/2FTI1e4/t7fqz6XFoNQNdiEacVVk=; b=JL3BWw6LOrN84w5R7wVuSNoF8Cl+DMYFv7Bnzrkzu4Nr5PIksC/iUgKEgBorCH1E6BlDrKU9sQ6TCtXiZ4dgURqngLwe07R+o1O0G8+vmkjXNZl9Juy32BLtEOtqKdZmHz6zBId73qOyI9GRA5M8dB6Lwgd7PP69V7TCxkh+tTw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=collabora.com; spf=pass smtp.mailfrom=dmitry.osipenko@collabora.com; dmarc=pass header.from= DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; t=1739663692; s=zohomail; d=collabora.com; i=dmitry.osipenko@collabora.com; h=From:From:To:To:Cc:Cc:Subject:Subject:Date:Date:Message-ID:In-Reply-To:References:MIME-Version:Content-Transfer-Encoding:Message-Id:Reply-To; bh=bk824fFEtJ4JFX/2FTI1e4/t7fqz6XFoNQNdiEacVVk=; b=GYo6xfTYrndfSuf258+c3emT8CQjDptqxGrCFuLS4dqC474pjK3whe0zTeaGrTxv 3usimKIFYP4BtsPuSSel8iUvjr4L3iC0rXUJu/UexPGUKLomfHN4yPTwvN/+73IeuE3 qmVzp1bLYqmMxprIy2oeYMNpzKaFo9W5hd5DTxTE= Received: by mx.zohomail.com with SMTPS id 1739663691563809.1510485476141; Sat, 15 Feb 2025 15:54:51 -0800 (PST) From: Dmitry Osipenko To: Heiko Stuebner , Marc Zyngier Cc: Rob Herring , Krzysztof Kozlowski , Thomas Gleixner , devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Kever Yang , XiaoDong Huang , Peter Geis , Robin Murphy , kernel@collabora.com Subject: [PATCH v1 3/4] arm64: dts: rockchip: rk356x: Add MSI controller node Date: Sun, 16 Feb 2025 02:54:30 +0300 Message-ID: <20250215235431.143138-4-dmitry.osipenko@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250215235431.143138-1-dmitry.osipenko@collabora.com> References: <20250215235431.143138-1-dmitry.osipenko@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ZohoMailClient: External Content-Type: text/plain; charset="utf-8" Rockchip 356x SoC's GIC has two hardware integration issues that affect MSI functionality of the GIC. Previously, both these GIC limitations were worked around by using MBI for MSI instead of ITS because kernel GIC driver didn't have necessary quirks. The first limitation is about RK356x GIC not supporting programmable shareability. Rockchip assigned Errata ID #3568001 for this issue. Second limitation is about GIC AXI master interface addressing only first 4GB of DRAM. Rockchip assigned Errata ID #3568002 for this issue. Now that kernel supports quirks for both of the erratums, add MSI controller node to RK356x device-tree. Signed-off-by: Dmitry Osipenko --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index 28be38b7182e..423185686600 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -284,7 +284,18 @@ gic: interrupt-controller@fd400000 { mbi-alias =3D <0x0 0xfd410000>; mbi-ranges =3D <296 24>; msi-controller; + ranges; + #address-cells =3D <2>; + #size-cells =3D <2>; dma-noncoherent; + + its: msi-controller@fd440000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0xfd440000 0 0x20000>; + dma-noncoherent; + msi-controller; + #msi-cells =3D <1>; + }; }; =20 usb_host0_ehci: usb@fd800000 { --=20 2.48.1 From nobody Fri Dec 19 15:17:03 2025 Received: from sender4-pp-f112.zoho.com (sender4-pp-f112.zoho.com [136.143.188.112]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 81F281FE461; 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charset="utf-8" Rockchip 356x device-tree now supports GIC ITS. Move PCIe controller's MSI to use ITS instead of MBI. This removes extra CPU overhead of handling PCIe MBIs by letting GIC's ITS to serve the PCIe MSIs. Signed-off-by: Dmitry Osipenko --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boo= t/dts/rockchip/rk356x-base.dtsi index 423185686600..4f11141ea146 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -969,7 +969,7 @@ pcie2x1: pcie@fe260000 { num-ib-windows =3D <6>; num-ob-windows =3D <2>; max-link-speed =3D <2>; - msi-map =3D <0x0 &gic 0x0 0x1000>; + msi-map =3D <0x0 &its 0x0 0x1000>; num-lanes =3D <1>; phys =3D <&combphy2 PHY_TYPE_PCIE>; phy-names =3D "pcie-phy"; --=20 2.48.1