From nobody Fri Dec 19 18:31:33 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E97891A239E; Sat, 15 Feb 2025 00:55:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739580958; cv=none; b=Ca47MViWaO+2zDJK+Ht2sQflUuOq9xNSJo0OI+5TRH+AQQvrVBCm4KDGuWSe0j59prHPjMY86KxjBiPsSJ5x6wf2BNlDjPHJkkot9DNIz9xBoFf1nq27LmeIJg7FLz2JQ6ub5Umd2qRJMvMPeZO+1CaKKs5ZeTtcYcSe2SdkS2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739580958; c=relaxed/simple; bh=g4ZiNjBB56+mnqDk9Mu4uIOUw/V5PSViIE9EHg+P5Ss=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UMHnGt79B7Vm7Iy/g5qeavf9d8/iBeVJsjlNJdIFtGdPuHPaX3c1+idux6OgZomw2y5STBT+uBoA3XrD9Qu7rszm4yHU0QdksDFcd5I5nHZLuphtgaNaX3M26vA8tMlgEZEMj2o9WvSwdMBcoMSL/ObFObKTQX7p+VBXO9GN6Ok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=pjmbm3Wg; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="pjmbm3Wg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739580955; bh=g4ZiNjBB56+mnqDk9Mu4uIOUw/V5PSViIE9EHg+P5Ss=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pjmbm3Wg1oS7pYIFqz84AP0iP/Y3H9SiuKck4O7M+cykW0FWNskBKIlbXeSKER3MP cLDu5/Ujwfub5TR9NVnxISKz3jzh7/GbLmCQCEqycPR9r3QIqM2WDDg9Xk1GhCNJxa VRRWQi8cPmMMjz7fIMtEUc6a5gmKQ7R+XEbKYd4a9v7HVZafF00FwMcL0r2iLLxojg lf1RCv+55HHXjOCQfX48N8H4jYqccOV1xJFDv851ZalDN20ueVfQPG1QHZdDnwP0Gv EvvL64pqURZVMLbfcnK9nCpIPciz0gCHtu0qVI4pV8lBuAaMdy5so2lObCo13JG05c xDq86Gt4yNfJg== Received: from localhost (144.232.221.87.dynamic.jazztel.es [87.221.232.144]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id C4D1D17E0E95; Sat, 15 Feb 2025 01:55:54 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 15 Feb 2025 02:55:37 +0200 Subject: [PATCH 1/4] drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250215-vop2-hdmi1-disp-modes-v1-1-81962a7151d6@collabora.com> References: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> In-Reply-To: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 The RK3588 specific implementation is currently quite limited in terms of handling the full range of display modes supported by the connected screens, e.g. 2560x1440@75Hz, 2048x1152@60Hz, 1024x768@60Hz are just a few of them. Additionally, it doesn't cope well with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of HDMI1 PHY PLL as a more accurate DCLK source to handle all display modes up to 4K@60Hz. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 26 ++++++++++++++++++++++++= +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index afc946ead87091373605e59dbca281a9e91bea57..f1700b2fabf0b0d000cf3c9cf5f= 06ca791b87499 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -216,6 +216,7 @@ struct vop2 { struct clk *aclk; struct clk *pclk; struct clk *pll_hdmiphy0; + struct clk *pll_hdmiphy1; =20 /* optional internal rgb encoder */ struct rockchip_rgb *rgb; @@ -2270,11 +2271,14 @@ static void vop2_crtc_atomic_enable(struct drm_crtc= *crtc, * Switch to HDMI PHY PLL as DCLK source for display modes up * to 4K@60Hz, if available, otherwise keep using the system CRU. */ - if (vop2->pll_hdmiphy0 && clock <=3D VOP2_MAX_DCLK_RATE) { + if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <=3D VOP2_MAX_DCL= K_RATE) { drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); =20 if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI0) { + if (!vop2->pll_hdmiphy0) + break; + if (!vp->dclk_src) vp->dclk_src =3D clk_get_parent(vp->dclk); =20 @@ -2284,6 +2288,20 @@ static void vop2_crtc_atomic_enable(struct drm_crtc = *crtc, "Could not switch to HDMI0 PHY PLL: %d\n", ret); break; } + + if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI1) { + if (!vop2->pll_hdmiphy1) + break; + + if (!vp->dclk_src) + vp->dclk_src =3D clk_get_parent(vp->dclk); + + ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); + if (ret < 0) + drm_warn(vop2->drm, + "Could not switch to HDMI1 PHY PLL: %d\n", ret); + break; + } } } =20 @@ -3733,6 +3751,12 @@ static int vop2_bind(struct device *dev, struct devi= ce *master, void *data) return PTR_ERR(vop2->pll_hdmiphy0); } =20 + vop2->pll_hdmiphy1 =3D devm_clk_get_optional(vop2->dev, "pll_hdmiphy1"); + if (IS_ERR(vop2->pll_hdmiphy1)) { + drm_err(vop2->drm, "failed to get pll_hdmiphy1\n"); + return PTR_ERR(vop2->pll_hdmiphy1); + } + vop2->irq =3D platform_get_irq(pdev, 0); if (vop2->irq < 0) { drm_err(vop2->drm, "cannot find irq for vop2\n"); --=20 2.48.1