From nobody Fri Dec 19 16:54:26 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E97891A239E; Sat, 15 Feb 2025 00:55:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739580958; cv=none; b=Ca47MViWaO+2zDJK+Ht2sQflUuOq9xNSJo0OI+5TRH+AQQvrVBCm4KDGuWSe0j59prHPjMY86KxjBiPsSJ5x6wf2BNlDjPHJkkot9DNIz9xBoFf1nq27LmeIJg7FLz2JQ6ub5Umd2qRJMvMPeZO+1CaKKs5ZeTtcYcSe2SdkS2E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739580958; c=relaxed/simple; bh=g4ZiNjBB56+mnqDk9Mu4uIOUw/V5PSViIE9EHg+P5Ss=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=UMHnGt79B7Vm7Iy/g5qeavf9d8/iBeVJsjlNJdIFtGdPuHPaX3c1+idux6OgZomw2y5STBT+uBoA3XrD9Qu7rszm4yHU0QdksDFcd5I5nHZLuphtgaNaX3M26vA8tMlgEZEMj2o9WvSwdMBcoMSL/ObFObKTQX7p+VBXO9GN6Ok= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=pjmbm3Wg; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="pjmbm3Wg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739580955; bh=g4ZiNjBB56+mnqDk9Mu4uIOUw/V5PSViIE9EHg+P5Ss=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pjmbm3Wg1oS7pYIFqz84AP0iP/Y3H9SiuKck4O7M+cykW0FWNskBKIlbXeSKER3MP cLDu5/Ujwfub5TR9NVnxISKz3jzh7/GbLmCQCEqycPR9r3QIqM2WDDg9Xk1GhCNJxa VRRWQi8cPmMMjz7fIMtEUc6a5gmKQ7R+XEbKYd4a9v7HVZafF00FwMcL0r2iLLxojg lf1RCv+55HHXjOCQfX48N8H4jYqccOV1xJFDv851ZalDN20ueVfQPG1QHZdDnwP0Gv EvvL64pqURZVMLbfcnK9nCpIPciz0gCHtu0qVI4pV8lBuAaMdy5so2lObCo13JG05c xDq86Gt4yNfJg== Received: from localhost (144.232.221.87.dynamic.jazztel.es [87.221.232.144]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id C4D1D17E0E95; Sat, 15 Feb 2025 01:55:54 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 15 Feb 2025 02:55:37 +0200 Subject: [PATCH 1/4] drm/rockchip: vop2: Improve display modes handling on RK3588 HDMI1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250215-vop2-hdmi1-disp-modes-v1-1-81962a7151d6@collabora.com> References: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> In-Reply-To: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 The RK3588 specific implementation is currently quite limited in terms of handling the full range of display modes supported by the connected screens, e.g. 2560x1440@75Hz, 2048x1152@60Hz, 1024x768@60Hz are just a few of them. Additionally, it doesn't cope well with non-integer refresh rates like 59.94, 29.97, 23.98, etc. Make use of HDMI1 PHY PLL as a more accurate DCLK source to handle all display modes up to 4K@60Hz. Signed-off-by: Cristian Ciocaltea --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 26 ++++++++++++++++++++++++= +- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index afc946ead87091373605e59dbca281a9e91bea57..f1700b2fabf0b0d000cf3c9cf5f= 06ca791b87499 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -216,6 +216,7 @@ struct vop2 { struct clk *aclk; struct clk *pclk; struct clk *pll_hdmiphy0; + struct clk *pll_hdmiphy1; =20 /* optional internal rgb encoder */ struct rockchip_rgb *rgb; @@ -2270,11 +2271,14 @@ static void vop2_crtc_atomic_enable(struct drm_crtc= *crtc, * Switch to HDMI PHY PLL as DCLK source for display modes up * to 4K@60Hz, if available, otherwise keep using the system CRU. */ - if (vop2->pll_hdmiphy0 && clock <=3D VOP2_MAX_DCLK_RATE) { + if ((vop2->pll_hdmiphy0 || vop2->pll_hdmiphy1) && clock <=3D VOP2_MAX_DCL= K_RATE) { drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { struct rockchip_encoder *rkencoder =3D to_rockchip_encoder(encoder); =20 if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI0) { + if (!vop2->pll_hdmiphy0) + break; + if (!vp->dclk_src) vp->dclk_src =3D clk_get_parent(vp->dclk); =20 @@ -2284,6 +2288,20 @@ static void vop2_crtc_atomic_enable(struct drm_crtc = *crtc, "Could not switch to HDMI0 PHY PLL: %d\n", ret); break; } + + if (rkencoder->crtc_endpoint_id =3D=3D ROCKCHIP_VOP2_EP_HDMI1) { + if (!vop2->pll_hdmiphy1) + break; + + if (!vp->dclk_src) + vp->dclk_src =3D clk_get_parent(vp->dclk); + + ret =3D clk_set_parent(vp->dclk, vop2->pll_hdmiphy1); + if (ret < 0) + drm_warn(vop2->drm, + "Could not switch to HDMI1 PHY PLL: %d\n", ret); + break; + } } } =20 @@ -3733,6 +3751,12 @@ static int vop2_bind(struct device *dev, struct devi= ce *master, void *data) return PTR_ERR(vop2->pll_hdmiphy0); } =20 + vop2->pll_hdmiphy1 =3D devm_clk_get_optional(vop2->dev, "pll_hdmiphy1"); + if (IS_ERR(vop2->pll_hdmiphy1)) { + drm_err(vop2->drm, "failed to get pll_hdmiphy1\n"); + return PTR_ERR(vop2->pll_hdmiphy1); + } + vop2->irq =3D platform_get_irq(pdev, 0); if (vop2->irq < 0) { drm_err(vop2->drm, "cannot find irq for vop2\n"); --=20 2.48.1 From nobody Fri Dec 19 16:54:26 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 428911A23AA; Sat, 15 Feb 2025 00:55:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739580960; cv=none; b=ABspxXIhfu6ICxo+q5QcUNvXy1Yb/9oN6jc4zRfupuZ3sJpqrXIOdn3DPzY5kKy41JCy9spHz/PqFSuRJlJnny5gzok4MeJzEtq9GaQpyFuAGAt6Q4UiXzcv8qjGfFZQ/LEODHEP+IIhCUYSgZEKNSNA8jUCgZz64M7nIotB6CM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739580960; c=relaxed/simple; bh=MLcedUWBkgkxVWzbTDCOp0QOw7S68POvgln+Xwcmv1I=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=CyiiByU5b/74wpH3cDZMalB5K9Ba3mYZn94FVJbunqP2lTHMNQ539YhXX1Ezi0zcRNErQTYegArV4vYVscRI2JuNOGIIbbQ3G2I1fQkgMDXQT0vvlbi9NOd3/XH4EPFqYly3DE3D1XrLQcXpbiXhgyi/Y0YlW6PEyTgmnC9iXT4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=DXg2dQg3; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="DXg2dQg3" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739580956; bh=MLcedUWBkgkxVWzbTDCOp0QOw7S68POvgln+Xwcmv1I=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=DXg2dQg3MG/904U+ETV8QkQ6q5k5cPYok47HVEkyQkeKso7F7pLb3cCAQ2klpxkG/ daW5nCLdXVmjqD1om9qxWTPcwhzJsRjHvHeruTji6ExRJcjlmUTfnKjjz8/4RrdjG4 7l3qXsctRvkD/hNMihjXYCE7pu6LeNXuSoHJPSHNl8iT/5zeVz+N2qNGVDgmioRhMC Qo5XpGoQKsjPGRhPbDNCcndIn8V1c97bgc8nTfcQM331pg+DxZ0VqboiiKcF31Kf+/ vUmRzlbNzcxfmacJ8LENhyOM+ynNHrxmAS6iBfbp8AomyYo0o6dKgozVbM0HZptpHN MMzty5Y97z8Iw== Received: from localhost (144.232.221.87.dynamic.jazztel.es [87.221.232.144]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 2D35017E0FBA; Sat, 15 Feb 2025 01:55:56 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 15 Feb 2025 02:55:38 +0200 Subject: [PATCH 2/4] arm64: dts: rockchip: Enable HDMI1 PHY clk provider on RK3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250215-vop2-hdmi1-disp-modes-v1-2-81962a7151d6@collabora.com> References: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> In-Reply-To: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 Since commit c4b09c562086 ("phy: phy-rockchip-samsung-hdptx: Add clock provider support"), the HDMI PHY PLL can be used as an alternative and more accurate pixel clock source for VOP2 to improve display modes handling on RK3588 SoC. Add the missing #clock-cells property to allow using the clock provider functionality of HDMI1 PHY. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-extra.dtsi index 9bc5287bb6469138c2d9e2fcfec7984c830c2ce5..97e55990e0524ed447d182cef41= 6190822bf67be 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -479,6 +479,7 @@ hdptxphy1: phy@fed70000 { reg =3D <0x0 0xfed70000 0x0 0x2000>; clocks =3D <&cru CLK_USB2PHY_HDPTXRXPHY_REF>, <&cru PCLK_HDPTX1>; clock-names =3D "ref", "apb"; + #clock-cells =3D <0>; #phy-cells =3D <0>; resets =3D <&cru SRST_HDPTX1>, <&cru SRST_P_HDPTX1>, <&cru SRST_HDPTX1_INIT>, <&cru SRST_HDPTX1_CMN>, --=20 2.48.1 From nobody Fri Dec 19 16:54:26 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0CD3C1A304A; Sat, 15 Feb 2025 00:55:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739580961; cv=none; b=Rzkrv4an0YY5z+FonZ615PvimLZUFmhk6oGGDvUJW/nInQ6MbDQQevpOl+xtg6RkOfDtvUpzcYdauvv9KdUUr56yfH+4Syt5Q1vqjARxYb4Q1k60WGNgO8wbTHolv5S/jUjhphHmq7nCTxqv52dntQp4y9kf9or9jKrQp/qkU38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739580961; c=relaxed/simple; bh=SE9Nutny/gzjaQ3Hy7tTClTNDcn3VFJaaCAjW0BhTsc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=NBchboEuM+I52Ub9BbcvxB/K0NxW+XXAZv1VlVL1/GrK6BXXGBBJk4NQGRt92LV+XsJqBVARHj5xbXPSRI/sSf+olaDcvb4k1t++7U6BXfO8slOiuEIcCrkDYE/fB2g5nqLX3uf+DGr6FV++ecVoVAfT0sPNGQAZLIPeRNlV7gE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=S2aF9Ehy; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="S2aF9Ehy" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739580958; bh=SE9Nutny/gzjaQ3Hy7tTClTNDcn3VFJaaCAjW0BhTsc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=S2aF9EhypxIuz+HM/aOb9onCVBBNSj0b4uWLsV0wcZrlDSNMrdTzKJKp6ILTxA1Nv xFb6UzPOJ3HbsU1cWYhoIJpPZ/2k7wI/25AQxMfbuY2+xgbPFjys7BOTM9UVOXXzbX eM2hE67AfxrcBJOw3uBdA5v9SQ+iEBagBPfNIo+YP9cjzsUG+mzd+Hk95ZCIAj02pT TS+xJD9suo7v+Wp4D4nlxLL8htQwPAMkmBillK834miktsl6zlcnfQ+yJLetV9py1W lNgPXLp3PVAJHjmfLXnNIMLBafwLPF1EBvyVnttdEBctCkA6jBegqABXdwYyXBqsH+ HAngOoIpYCRbg== Received: from localhost (144.232.221.87.dynamic.jazztel.es [87.221.232.144]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id A628B17E0FC1; Sat, 15 Feb 2025 01:55:57 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 15 Feb 2025 02:55:39 +0200 Subject: [PATCH 3/4] arm64: dts: rockchip: Add HDMI1 PHY PLL clock source to VOP2 on RK3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250215-vop2-hdmi1-disp-modes-v1-3-81962a7151d6@collabora.com> References: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> In-Reply-To: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 VOP2 on RK3588 is able to use the HDMI PHY PLL as an alternative and more accurate pixel clock source to improve handling of display modes up to 4K@60Hz on video ports 0, 1 and 2. The HDMI1 PHY PLL clock source cannot be added directly to vop node in rk3588-base.dtsi, along with the HDMI0 related one, because HDMI1 is an optional feature and its PHY node belongs to a separate (extra) DT file. Therefore, add the HDMI1 PHY PLL clock source to VOP2 by overwriting its clocks & clock-names properties in the extra DT file. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-extra.dtsi index 97e55990e0524ed447d182cef416190822bf67be..1df8845bdc264b07601add3747b= 273f92091e7fa 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi @@ -542,3 +542,24 @@ pcie30phy: phy@fee80000 { status =3D "disabled"; }; }; + +&vop { + clocks =3D <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>, + <&hdptxphy0>, + <&hdptxphy1>; + clock-names =3D "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop", + "pll_hdmiphy0", + "pll_hdmiphy1"; +}; --=20 2.48.1 From nobody Fri Dec 19 16:54:26 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 427DE1FDA65; Sat, 15 Feb 2025 00:56:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739580966; cv=none; b=sl8JD3DoSfMUadqWMxztN1cH9sy0jUdOhbRidmGLmFireR5ET2KlBVS+pCw3UwlADEqzOyuuwtUWcslmvuzEPxATwTBjaFsITf2ZMI8DhRiPoq2Hgf7B7nrLZMUujYguzNOuwLjpQ0/L2neWSWtMQP1XS3civAkj4d/8o+zn9Mo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739580966; c=relaxed/simple; bh=SamXBzmLvsEp0Jz0d1kldxkjLOu7b/3p5uRtusyt+UA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=FtbFLjQT6Hy+F6s72C88B+5QAUKGL5Dros6M9+aw2SksS2J7Z3cCNZByP0uDRHjhmZejq9Xe2PD4OnMkfyZ0ORXrZJStkd3PY9wwEjaotE87XnrDuHHbFmWTTTyQLKubLNzbJuwXwE0ImJt0LsIK7qcSFK6LubH70ENo4CjosRk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=YHX+RxPr; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="YHX+RxPr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739580959; bh=SamXBzmLvsEp0Jz0d1kldxkjLOu7b/3p5uRtusyt+UA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YHX+RxPrOuFbD+K59CXEFQAKW0HgHAw+8zomFsb8XCMPAUAIK9LnBBkYXUAGtoZot Yr2h1HVHvWsManylI0wE8R54lIaqsvDqPHcw2vs5q2C6BjA9mcWMZDMEI7WfPSwrVW DMCHpLcI+jjq/fMurpyrvcxTsp4n55fXyCVl6MyrGYPweNpty1qeQjUbQEKlNGKfcr Y+tcnqZb2JHSTgh1M21nkOsTONZ6mpTln9Y42PVtMw/n/tA4FZaf7RcQExzH+9ILnT 3ZxLNvamZHzLkAetsNE+EJAwVrql4HGXdF7lf0OzPagELxU4A4tkAuIX3V4CmPnWx7 wox9izcsH8Ifw== Received: from localhost (144.232.221.87.dynamic.jazztel.es [87.221.232.144]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 3229D17E1553; Sat, 15 Feb 2025 01:55:59 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 15 Feb 2025 02:55:40 +0200 Subject: [PATCH 4/4] arm64: dts: rockchip: Enable HDMI1 on rk3588-evb1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250215-vop2-hdmi1-disp-modes-v1-4-81962a7151d6@collabora.com> References: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> In-Reply-To: <20250215-vop2-hdmi1-disp-modes-v1-0-81962a7151d6@collabora.com> To: Sandy Huang , =?utf-8?q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: kernel@collabora.com, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-Mailer: b4 0.14.2 Add the necessary DT changes to enable the second HDMI output port on Rockchip RK3588 EVB1. While at it, switch the position of &vop_mmu and @vop to maintain the alphabetical order. Signed-off-by: Cristian Ciocaltea --- arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 42 ++++++++++++++++++++= ++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts b/arch/arm64/= boot/dts/rockchip/rk3588-evb1-v10.dts index 3fd0665cde2ca15cd309919ff751b00e0f53a400..27a7895595ee9fa2f5d5f3096cb= e334c1d3792cf 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts @@ -132,6 +132,17 @@ hdmi0_con_in: endpoint { }; }; =20 + hdmi1-con { + compatible =3D "hdmi-connector"; + type =3D "a"; + + port { + hdmi1_con_in: endpoint { + remote-endpoint =3D <&hdmi1_out_con>; + }; + }; + }; + pcie20_avdd0v85: regulator-pcie20-avdd0v85 { compatible =3D "regulator-fixed"; regulator-name =3D "pcie20_avdd0v85"; @@ -364,10 +375,30 @@ hdmi0_out_con: endpoint { }; }; =20 +&hdmi1 { + status =3D "okay"; +}; + +&hdmi1_in { + hdmi1_in_vp1: endpoint { + remote-endpoint =3D <&vp1_out_hdmi1>; + }; +}; + +&hdmi1_out { + hdmi1_out_con: endpoint { + remote-endpoint =3D <&hdmi1_con_in>; + }; +}; + &hdptxphy0 { status =3D "okay"; }; =20 +&hdptxphy1 { + status =3D "okay"; +}; + &i2c2 { status =3D "okay"; =20 @@ -1371,11 +1402,11 @@ &usb_host1_xhci { status =3D "okay"; }; =20 -&vop_mmu { +&vop { status =3D "okay"; }; =20 -&vop { +&vop_mmu { status =3D "okay"; }; =20 @@ -1385,3 +1416,10 @@ vp0_out_hdmi0: endpoint@ROCKCHIP_VOP2_EP_HDMI0 { remote-endpoint =3D <&hdmi0_in_vp0>; }; }; + +&vp1 { + vp1_out_hdmi1: endpoint@ROCKCHIP_VOP2_EP_HDMI1 { + reg =3D ; + remote-endpoint =3D <&hdmi1_in_vp1>; + }; +}; --=20 2.48.1