From nobody Thu Mar 13 20:51:52 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF30F25A65B for ; Fri, 14 Feb 2025 09:27:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=170.10.133.124 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739525225; cv=none; b=LsW4WrKjSrjD8F7KJDhZRySzx+m+auav5N3VZijfeAMQlzbxicfMpq4TafpZ90+Y7Ij5tUBb6IfbH3q4ebULJejaoeLfGjBUFuScPrKDLRLT2pM/fC+uO53k3Z04Gc05xmXvz6acMACAiAN+6S9cq+tt6wODELo2tj49pMVtsTA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739525225; c=relaxed/simple; bh=uTgUtNO8406O5vWKaN5vokRgtyiqaXrMetNPncVI2JE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r2/L6qEysD1jmoDUu+DidjKE2MY2/LShbj4tjtxjHM8NBtpdu29H3QM8UG+XwpbvkyP+AC9tAbhlVzu0JgzJ4bj6nQnkuLPctWAMm2mstGqBET/eCghMXJHJ+OzomNotsh+MKUtFyoOipdV6VotTF9ZHHOwJOpj+uapFF7XQQEA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com; spf=pass smtp.mailfrom=redhat.com; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b=GK6BEqm5; arc=none smtp.client-ip=170.10.133.124 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=redhat.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=redhat.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=redhat.com header.i=@redhat.com header.b="GK6BEqm5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1739525222; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=8gnYcHx8du+Hw1GvMIJpqwsVQPG+9zeooKptV8KqTFM=; b=GK6BEqm5GtzxqxJ07NtZpRyByPBaVte35jt76UbAjKJlkMlm4afJDAgzTFqn+Rb9IVyZ9l Z2CLwkhTwIoO9ykDXz1pn29CJ3UjNxEOlKXYVxxu+3Ttv4zUQTwEqnEZ6358FJnP4UA/Nj k0b5190A3jVmrhN3ULEKakiCgTdS+S8= Received: from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3, cipher=TLS_AES_256_GCM_SHA384) id us-mta-578-nM1hhWhROmW1GiMymFciwA-1; Fri, 14 Feb 2025 04:26:56 -0500 X-MC-Unique: nM1hhWhROmW1GiMymFciwA-1 X-Mimecast-MFC-AGG-ID: nM1hhWhROmW1GiMymFciwA_1739525215 Received: from mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.111]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS id 1CF011800373; Fri, 14 Feb 2025 09:26:55 +0000 (UTC) Received: from hydra.redhat.com (unknown [10.45.225.79]) by mx-prod-int-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP id 9D362180035E; Fri, 14 Feb 2025 09:26:51 +0000 (UTC) From: Jocelyn Falempe To: Jani Nikula , Rodrigo Vivi , Joonas Lahtinen , Tvrtko Ursulin , David Airlie , Simona Vetter , intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org Cc: Jocelyn Falempe Subject: [PATCH v5 8/8] drm/i915/display: Add drm_panic support for 4-tiling with DPT Date: Fri, 14 Feb 2025 10:21:43 +0100 Message-ID: <20250214092608.2555218-9-jfalempe@redhat.com> In-Reply-To: <20250214092608.2555218-1-jfalempe@redhat.com> References: <20250214092608.2555218-1-jfalempe@redhat.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Scanned-By: MIMEDefang 3.4.1 on 10.30.177.111 Content-Type: text/plain; charset="utf-8" On Alder Lake and later, it's not possible to disable tiling when DPT is enabled. So this commit implements 4-Tiling support, to still be able to draw the panic screen. Signed-off-by: Jocelyn Falempe --- .../gpu/drm/i915/display/intel_atomic_plane.c | 22 ++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gp= u/drm/i915/display/intel_atomic_plane.c index 4cb12fdc21fe4..2a319cd319566 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c +++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c @@ -1241,6 +1241,25 @@ static void intel_ytile_set_pixel(struct drm_scanout= _buffer *sb, unsigned int x, iosys_map_wr(&sb->map[0], offset, u32, color); } =20 +static void intel_4tile_set_pixel(struct drm_scanout_buffer *sb, unsigned = int x, unsigned int y, + u32 color) +{ + u32 offset; + unsigned int swizzle; + unsigned int width_in_blocks =3D DIV_ROUND_UP(sb->width, 32); + + /* Block offset */ + offset =3D ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * Y= TILE_SIZE; + + x =3D x % YTILE_WIDTH; + y =3D y % YTILE_HEIGHT; + + /* bit order inside a block is y4 y3 x4 y2 x3 x2 y1 y0 x1 x0 */ + swizzle =3D (x & 3) | ((y & 3) << 2) | ((x & 0xc) << 2) | (y & 4) << 4 | = ((x & 0x10) << 3) | ((y & 0x18) << 5); + offset +=3D swizzle * 4; + iosys_map_wr(&sb->map[0], offset, u32, color); +} + static void intel_panic_flush(struct drm_plane *plane) { struct intel_plane_state *plane_state =3D to_intel_plane_state(plane->sta= te); @@ -1275,7 +1294,6 @@ static void (*intel_get_tiling_func(u64 fb_modifier))= (struct drm_scanout_buffer case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS: case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS: return intel_ytile_set_pixel; - case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_4_TILED: case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS: case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS: @@ -1285,6 +1303,8 @@ static void (*intel_get_tiling_func(u64 fb_modifier))= (struct drm_scanout_buffer case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS: case I915_FORMAT_MOD_4_TILED_BMG_CCS: case I915_FORMAT_MOD_4_TILED_LNL_CCS: + return intel_4tile_set_pixel; + case I915_FORMAT_MOD_X_TILED: case I915_FORMAT_MOD_Yf_TILED: case I915_FORMAT_MOD_Yf_TILED_CCS: default: --=20 2.47.1