From nobody Thu Mar 13 00:18:38 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 01382211497; Fri, 14 Feb 2025 09:08:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739524108; cv=none; b=F2VHHbl2LbmK+WBO50RUPFJ3HaybQEbezX2urySJmHoeZr4PypPnzd8rELRCtQ0ouGxFGjLK6PdXbc5Bi3vUuDdzZ77lIUCb9Cwi/fDy5y4vWFo+yWkDwqc8hpNRJUNvk1Rx/6jQx54yCcAGUI9T5TZc7Yz36oKFOMgFVghSdik= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739524108; c=relaxed/simple; bh=9GAN2wqhXEOHdcyK7lREPKym8KwXksIObQM5sWX+jrY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=n+sKa1BiJzxGKp2I765e1/4h77Ij6MVylf5DelAZe0TJZV8iNiPGD5Gk9l/dEfZz8z2qD2x75Nu7MOSom6v8kGgX4Nb6tNC1SLsIHPoOIDhDa7nUzCkol0YqNRp3jlW9qctZ4EIJeRWxxsskfWIgfiWHSsaYUJu9z6BZU+Mh/hQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=cHWt3UJ5; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="cHWt3UJ5" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739524106; x=1771060106; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9GAN2wqhXEOHdcyK7lREPKym8KwXksIObQM5sWX+jrY=; b=cHWt3UJ5QkWnxkyLrkTMVxNbrbSRh5+H9H430tppMDf6mA3zQfIBfnFB PFv1ISKxBGICZjaQoKAFAoKPIYfeESOlOlogvBUfEVDPvy4gOKtWvURui od3QtgWz3CPzRmJrtCsF/MYDCOhxCAFHPHLiS239p/zNGZyxvru+4wsH2 mg9QyFeNZS1/6nQrfQUZ6syaW6GPEA8VKCS18ykMbovNmkOi4cO33yv/z pfkF4p0RP5Rr2TF5ONhpWW+d7GQny4l4R3rPrQNSmOr/6jp/d546gRJUp isk/o7lUisZ//cJ+S/d61S8smlOy6dO7gbo/kP4OERYXb2wOJPCTMeo8u g==; X-CSE-ConnectionGUID: DUNERLhDREGSlQ2D0uOy0w== X-CSE-MsgGUID: welsIwUDSiKWwoJoQq9M7A== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="51694755" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="51694755" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 01:08:24 -0800 X-CSE-ConnectionGUID: SgEbyHy1RjaiHx/TbP09EA== X-CSE-MsgGUID: 7H56IjySQpqx84tJFUhDRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="114303047" Received: from inlubt0246.iind.intel.com ([10.191.24.87]) by orviesa008.jf.intel.com with ESMTP; 14 Feb 2025 01:08:01 -0800 From: subramanian.mohan@intel.com To: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, giometti@enneenne.com, tglx@linutronix.de, corbet@lwn.net Cc: eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, thejesh.reddy.t.r@intel.com, david.zage@intel.com, srinivasan.chinnadurai@intel.com, subramanian.mohan@intel.com Subject: [PATCH v14 1/4] drivers pps/generators: replace copy of pps-gen info struct with const pointer Date: Fri, 14 Feb 2025 14:37:52 +0530 Message-Id: <20250214090755.37450-2-subramanian.mohan@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20250214090755.37450-1-subramanian.mohan@intel.com> References: <20250214090755.37450-1-subramanian.mohan@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Subramanian Mohan Some PPS generator drivers may need to retrieve a pointer to their internal data while executing the PPS generator enable() method. During the driver registration the pps_gen_device pointer is returned from the framework, and for that reason, there is difficulty in getting generator driver data back in the enable function. We won't be able to use container_of macro as it results in static assert, and we might end up in using static pointer. To solve the issue and to get back the generator driver data back, we should not copy the struct pps_gen_source_info within the struct pps_gen_device during the registration stage, but simply save the pointer of the driver one. In this manner, driver may get a pointer to their internal data as shown below: struct pps_gen_foo_data_s { ... struct pps_gen_source_info gen_info; struct pps_gen_device *pps_gen; ... }; static int __init pps_gen_foo_init(void) { struct pps_gen_foo_data_s *foo; ... foo->pps_gen =3D pps_gen_register_source(&foo->gen_info); ... } Then, in the enable() method, we can retrieve the pointer to the main struct by using the code below: static int pps_gen_foo_enable(struct pps_gen_device *pps_gen, bool enable) { struct pps_gen_foo_data_s *foo =3D container_of(pps_gen->info, struct pps_gen_foo_data_s, gen_info); ... } Signed-off-by: Rodolfo Giometti Tested-by: Subramanian Mohan Suggested-by: Andy Shevchenko Signed-off-by: Subramanian Mohan Reviewed-by: Andy Shevchenko --- Documentation/driver-api/pps.rst | 3 +-- drivers/pps/generators/pps_gen-dummy.c | 2 +- drivers/pps/generators/pps_gen.c | 14 +++++++------- drivers/pps/generators/sysfs.c | 6 +++--- include/linux/pps_gen_kernel.h | 4 ++-- 5 files changed, 14 insertions(+), 15 deletions(-) diff --git a/Documentation/driver-api/pps.rst b/Documentation/driver-api/pp= s.rst index 71ad04c82d6c..04f1b88778fc 100644 --- a/Documentation/driver-api/pps.rst +++ b/Documentation/driver-api/pps.rst @@ -206,8 +206,7 @@ To do so the class pps-gen has been added. PPS generato= rs can be registered in the kernel by defining a struct pps_gen_source_info as follows:: =20 - static struct pps_gen_source_info pps_gen_dummy_info =3D { - .name =3D "dummy", + static const struct pps_gen_source_info pps_gen_dummy_info =3D { .use_system_clock =3D true, .get_time =3D pps_gen_dummy_get_time, .enable =3D pps_gen_dummy_enable, diff --git a/drivers/pps/generators/pps_gen-dummy.c b/drivers/pps/generator= s/pps_gen-dummy.c index b284c200cbe5..55de4aecf35e 100644 --- a/drivers/pps/generators/pps_gen-dummy.c +++ b/drivers/pps/generators/pps_gen-dummy.c @@ -61,7 +61,7 @@ static int pps_gen_dummy_enable(struct pps_gen_device *pp= s_gen, bool enable) * The PPS info struct */ =20 -static struct pps_gen_source_info pps_gen_dummy_info =3D { +static const struct pps_gen_source_info pps_gen_dummy_info =3D { .use_system_clock =3D true, .get_time =3D pps_gen_dummy_get_time, .enable =3D pps_gen_dummy_enable, diff --git a/drivers/pps/generators/pps_gen.c b/drivers/pps/generators/pps_= gen.c index ca592f1736f4..5b8bb454913c 100644 --- a/drivers/pps/generators/pps_gen.c +++ b/drivers/pps/generators/pps_gen.c @@ -66,7 +66,7 @@ static long pps_gen_cdev_ioctl(struct file *file, if (ret) return -EFAULT; =20 - ret =3D pps_gen->info.enable(pps_gen, status); + ret =3D pps_gen->info->enable(pps_gen, status); if (ret) return ret; pps_gen->enabled =3D status; @@ -76,7 +76,7 @@ static long pps_gen_cdev_ioctl(struct file *file, case PPS_GEN_USESYSTEMCLOCK: dev_dbg(pps_gen->dev, "PPS_GEN_USESYSTEMCLOCK\n"); =20 - ret =3D put_user(pps_gen->info.use_system_clock, uiuarg); + ret =3D put_user(pps_gen->info->use_system_clock, uiuarg); if (ret) return -EFAULT; =20 @@ -175,7 +175,7 @@ static int pps_gen_register_cdev(struct pps_gen_device = *pps_gen) devt =3D MKDEV(MAJOR(pps_gen_devt), pps_gen->id); =20 cdev_init(&pps_gen->cdev, &pps_gen_cdev_fops); - pps_gen->cdev.owner =3D pps_gen->info.owner; + pps_gen->cdev.owner =3D pps_gen->info->owner; =20 err =3D cdev_add(&pps_gen->cdev, devt, 1); if (err) { @@ -183,8 +183,8 @@ static int pps_gen_register_cdev(struct pps_gen_device = *pps_gen) MAJOR(pps_gen_devt), pps_gen->id); goto free_ida; } - pps_gen->dev =3D device_create(pps_gen_class, pps_gen->info.parent, devt, - pps_gen, "pps-gen%d", pps_gen->id); + pps_gen->dev =3D device_create(pps_gen_class, pps_gen->info->parent, devt, + pps_gen, "pps-gen%d", pps_gen->id); if (IS_ERR(pps_gen->dev)) { err =3D PTR_ERR(pps_gen->dev); goto del_cdev; @@ -225,7 +225,7 @@ static void pps_gen_unregister_cdev(struct pps_gen_devi= ce *pps_gen) * Return: the PPS generator device in case of success, and ERR_PTR(errno) * otherwise. */ -struct pps_gen_device *pps_gen_register_source(struct pps_gen_source_info = *info) +struct pps_gen_device *pps_gen_register_source(const struct pps_gen_source= _info *info) { struct pps_gen_device *pps_gen; int err; @@ -235,7 +235,7 @@ struct pps_gen_device *pps_gen_register_source(struct p= ps_gen_source_info *info) err =3D -ENOMEM; goto pps_gen_register_source_exit; } - pps_gen->info =3D *info; + pps_gen->info =3D info; pps_gen->enabled =3D false; =20 init_waitqueue_head(&pps_gen->queue); diff --git a/drivers/pps/generators/sysfs.c b/drivers/pps/generators/sysfs.c index faf8b1c6d202..6d6bc0006fea 100644 --- a/drivers/pps/generators/sysfs.c +++ b/drivers/pps/generators/sysfs.c @@ -19,7 +19,7 @@ static ssize_t system_show(struct device *dev, struct dev= ice_attribute *attr, { struct pps_gen_device *pps_gen =3D dev_get_drvdata(dev); =20 - return sysfs_emit(buf, "%d\n", pps_gen->info.use_system_clock); + return sysfs_emit(buf, "%d\n", pps_gen->info->use_system_clock); } static DEVICE_ATTR_RO(system); =20 @@ -30,7 +30,7 @@ static ssize_t time_show(struct device *dev, struct devic= e_attribute *attr, struct timespec64 time; int ret; =20 - ret =3D pps_gen->info.get_time(pps_gen, &time); + ret =3D pps_gen->info->get_time(pps_gen, &time); if (ret) return ret; =20 @@ -49,7 +49,7 @@ static ssize_t enable_store(struct device *dev, struct de= vice_attribute *attr, if (ret) return ret; =20 - ret =3D pps_gen->info.enable(pps_gen, status); + ret =3D pps_gen->info->enable(pps_gen, status); if (ret) return ret; pps_gen->enabled =3D status; diff --git a/include/linux/pps_gen_kernel.h b/include/linux/pps_gen_kernel.h index 022ea0ac4440..6214c8aa2e02 100644 --- a/include/linux/pps_gen_kernel.h +++ b/include/linux/pps_gen_kernel.h @@ -43,7 +43,7 @@ struct pps_gen_source_info { =20 /* The main struct */ struct pps_gen_device { - struct pps_gen_source_info info; /* PSS generator info */ + const struct pps_gen_source_info *info; /* PSS generator info */ bool enabled; /* PSS generator status */ =20 unsigned int event; @@ -70,7 +70,7 @@ extern const struct attribute_group *pps_gen_groups[]; */ =20 extern struct pps_gen_device *pps_gen_register_source( - struct pps_gen_source_info *info); + const struct pps_gen_source_info *info); extern void pps_gen_unregister_source(struct pps_gen_device *pps_gen); extern void pps_gen_event(struct pps_gen_device *pps_gen, unsigned int event, void *data); --=20 2.35.3 From nobody Thu Mar 13 00:18:38 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D82F22D78E; Fri, 14 Feb 2025 09:08:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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14 Feb 2025 01:08:26 -0800 X-CSE-ConnectionGUID: Ny9G3qn8S1+NLeR5RgWO9A== X-CSE-MsgGUID: C9S4XPjeT1uoXuQ0vEhriw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="114303098" Received: from inlubt0246.iind.intel.com ([10.191.24.87]) by orviesa008.jf.intel.com with ESMTP; 14 Feb 2025 01:08:09 -0800 From: subramanian.mohan@intel.com To: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, giometti@enneenne.com, tglx@linutronix.de, corbet@lwn.net Cc: eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, thejesh.reddy.t.r@intel.com, david.zage@intel.com, srinivasan.chinnadurai@intel.com, subramanian.mohan@intel.com Subject: [PATCH v14 2/4] pps: generators: Add PPS Generator TIO Driver Date: Fri, 14 Feb 2025 14:37:53 +0530 Message-Id: <20250214090755.37450-3-subramanian.mohan@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20250214090755.37450-1-subramanian.mohan@intel.com> References: <20250214090755.37450-1-subramanian.mohan@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Subramanian Mohan The Intel Timed IO PPS generator driver outputs a PPS signal using dedicated hardware that is more accurate than software actuated PPS. The Timed IO hardware generates output events using the ART timer. The ART timer period varies based on platform type, but is less than 100 nanoseconds for all current platforms. Timed IO output accuracy is within 1 ART period. PPS output is enabled by writing '1' the 'enable' sysfs attribute. The driver uses hrtimers to schedule a wake-up 10 ms before each event (edge) target time. At wakeup, the driver converts the target time in terms of CLOCK_REALTIME to ART trigger time and writes this to the Timed IO hardware. The Timed IO hardware generates an event precisely at the requested system time without software involvement. Co-developed-by: Christopher Hall Signed-off-by: Christopher Hall Co-developed-by: Pandith N Signed-off-by: Pandith N Co-developed-by: Thejesh Reddy T R Signed-off-by: Thejesh Reddy T R Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Eddie Dong Reviewed-by: Andy Shevchenko Acked-by: Rodolfo Giometti Signed-off-by: Subramanian Mohan --- drivers/pps/generators/Kconfig | 16 ++ drivers/pps/generators/Makefile | 1 + drivers/pps/generators/pps_gen_tio.c | 272 +++++++++++++++++++++++++++ 3 files changed, 289 insertions(+) create mode 100644 drivers/pps/generators/pps_gen_tio.c diff --git a/drivers/pps/generators/Kconfig b/drivers/pps/generators/Kconfig index cd94bf3bfaf2..b3f340ed3163 100644 --- a/drivers/pps/generators/Kconfig +++ b/drivers/pps/generators/Kconfig @@ -31,4 +31,20 @@ config PPS_GENERATOR_PARPORT utilizes STROBE pin of a parallel port to send PPS signals. It uses parport abstraction layer and hrtimers to precisely control the signal. =20 +config PPS_GENERATOR_TIO + tristate "TIO PPS signal generator" + depends on X86 && CPU_SUP_INTEL + help + If you say yes here you get support for a PPS TIO signal generator + which generates a pulse at a prescribed time based on the system clock. + It uses time translation and hrtimers to precisely generate a pulse. + This hardware is present on 2019 and newer Intel CPUs. However, this + driver is not useful without adding highly specialized hardware outside + the Linux system to observe these pulses. + + To compile this driver as a module, choose M here: the module + will be called pps_gen_tio. + + If unsure, say N. + endif # PPS_GENERATOR diff --git a/drivers/pps/generators/Makefile b/drivers/pps/generators/Makef= ile index dc1aa5a4688b..e109920e8a2d 100644 --- a/drivers/pps/generators/Makefile +++ b/drivers/pps/generators/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_PPS_GENERATOR) :=3D pps_gen_core.o =20 obj-$(CONFIG_PPS_GENERATOR_DUMMY) +=3D pps_gen-dummy.o obj-$(CONFIG_PPS_GENERATOR_PARPORT) +=3D pps_gen_parport.o +obj-$(CONFIG_PPS_GENERATOR_TIO) +=3D pps_gen_tio.o =20 ccflags-$(CONFIG_PPS_DEBUG) :=3D -DDEBUG diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/= pps_gen_tio.c new file mode 100644 index 000000000000..6c46b46c66cd --- /dev/null +++ b/drivers/pps/generators/pps_gen_tio.c @@ -0,0 +1,272 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PPS signal Generator Driver + * + * Copyright (C) 2024 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define TIOCTL 0x00 +#define TIOCOMPV 0x10 +#define TIOEC 0x30 + +/* Control Register */ +#define TIOCTL_EN BIT(0) +#define TIOCTL_DIR BIT(1) +#define TIOCTL_EP GENMASK(3, 2) +#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) +#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) +#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) + +/* Safety time to set hrtimer early */ +#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) + +#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) +#define ART_HW_DELAY_CYCLES 2 + +struct pps_tio { + struct pps_gen_source_info gen_info; + struct pps_gen_device *pps_gen; + struct hrtimer timer; + void __iomem *base; + u32 prev_count; + spinlock_t lock; + struct device *dev; +}; + +static inline u32 pps_tio_read(u32 offset, struct pps_tio *tio) +{ + return readl(tio->base + offset); +} + +static inline void pps_ctl_write(u32 value, struct pps_tio *tio) +{ + writel(value, tio->base + TIOCTL); +} + +/* + * For COMPV register, It's safer to write + * higher 32-bit followed by lower 32-bit + */ +static inline void pps_compv_write(u64 value, struct pps_tio *tio) +{ + hi_lo_writeq(value, tio->base + TIOCOMPV); +} + +static inline ktime_t first_event(struct pps_tio *tio) +{ + return ktime_set(ktime_get_real_seconds() + 1, MAGIC_CONST); +} + +static u32 pps_tio_disable(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl =3D pps_tio_read(TIOCTL, tio); + pps_compv_write(0, tio); + + ctrl &=3D ~TIOCTL_EN; + pps_ctl_write(ctrl, tio); + tio->pps_gen->enabled =3D false; + tio->prev_count =3D 0; + return ctrl; +} + +static void pps_tio_enable(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl =3D pps_tio_read(TIOCTL, tio); + ctrl |=3D TIOCTL_EN; + pps_ctl_write(ctrl, tio); + tio->pps_gen->enabled =3D true; +} + +static void pps_tio_direction_output(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl =3D pps_tio_disable(tio); + + /* + * We enable the device, be sure that the + * 'compare' value is invalid + */ + pps_compv_write(0, tio); + + ctrl &=3D ~(TIOCTL_DIR | TIOCTL_EP); + ctrl |=3D TIOCTL_EP_TOGGLE_EDGE; + pps_ctl_write(ctrl, tio); + pps_tio_enable(tio); +} + +static bool pps_generate_next_pulse(ktime_t expires, struct pps_tio *tio) +{ + u64 art; + + if (!ktime_real_to_base_clock(expires, CSID_X86_ART, &art)) { + pps_tio_disable(tio); + return false; + } + + pps_compv_write(art - ART_HW_DELAY_CYCLES, tio); + return true; +} + +static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) +{ + ktime_t expires, now; + u32 event_count; + struct pps_tio *tio =3D container_of(timer, struct pps_tio, timer); + + guard(spinlock)(&tio->lock); + + /* + * Check if any event is missed. + * If an event is missed, TIO will be disabled. + */ + event_count =3D pps_tio_read(TIOEC, tio); + if (tio->prev_count && tio->prev_count =3D=3D event_count) + goto err; + tio->prev_count =3D event_count; + + expires =3D hrtimer_get_expires(timer); + + now =3D ktime_get_real(); + if (now - expires >=3D SAFE_TIME_NS) + goto err; + + tio->pps_gen->enabled =3D pps_generate_next_pulse(expires + SAFE_TIME_NS,= tio); + if (!tio->pps_gen->enabled) + return HRTIMER_NORESTART; + + hrtimer_forward(timer, now, NSEC_PER_SEC / 2); + return HRTIMER_RESTART; + +err: + dev_err(tio->dev, "Event missed, Disabling Timed I/O"); + pps_tio_disable(tio); + pps_gen_event(tio->pps_gen, PPS_GEN_EVENT_MISSEDPULSE, NULL); + return HRTIMER_NORESTART; +} + +static int pps_tio_gen_enable(struct pps_gen_device *pps_gen, bool enable) +{ + struct pps_tio *tio =3D container_of(pps_gen->info, struct pps_tio, gen_i= nfo); + + if (!timekeeping_clocksource_has_base(CSID_X86_ART)) { + dev_err_once(tio->dev, "PPS cannot be used as clock is not related to AR= T"); + return -ENODEV; + } + + guard(spinlock_irqsave)(&tio->lock); + if (enable && !pps_gen->enabled) { + pps_tio_direction_output(tio); + hrtimer_start(&tio->timer, first_event(tio), HRTIMER_MODE_ABS); + } else if (!enable && pps_gen->enabled) { + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + } + + return 0; +} + +static int pps_tio_get_time(struct pps_gen_device *pps_gen, + struct timespec64 *time) +{ + struct system_time_snapshot snap; + + ktime_get_snapshot(&snap); + *time =3D ktime_to_timespec64(snap.real); + + return 0; +} + +static int pps_gen_tio_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct pps_tio *tio; + + if (!(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ) && + cpu_feature_enabled(X86_FEATURE_ART))) { + dev_warn(dev, "TSC/ART is not enabled"); + return -ENODEV; + } + + tio =3D devm_kzalloc(dev, sizeof(*tio), GFP_KERNEL); + if (!tio) + return -ENOMEM; + + tio->gen_info.use_system_clock =3D true; + tio->gen_info.enable =3D pps_tio_gen_enable; + tio->gen_info.get_time =3D pps_tio_get_time; + tio->gen_info.owner =3D THIS_MODULE; + + tio->pps_gen =3D pps_gen_register_source(&tio->gen_info); + if (IS_ERR(tio->pps_gen)) + return PTR_ERR(tio->pps_gen); + + tio->dev =3D dev; + tio->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tio->base)) + return PTR_ERR(tio->base); + + pps_tio_disable(tio); + hrtimer_init(&tio->timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); + tio->timer.function =3D hrtimer_callback; + spin_lock_init(&tio->lock); + platform_set_drvdata(pdev, &tio); + + return 0; +} + +static void pps_gen_tio_remove(struct platform_device *pdev) +{ + struct pps_tio *tio =3D platform_get_drvdata(pdev); + + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + pps_gen_unregister_source(tio->pps_gen); +} + +static const struct acpi_device_id intel_pmc_tio_acpi_match[] =3D { + { "INTC1021" }, + { "INTC1022" }, + { "INTC1023" }, + { "INTC1024" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); + +static struct platform_driver pps_gen_tio_driver =3D { + .probe =3D pps_gen_tio_probe, + .remove =3D pps_gen_tio_remove, + .driver =3D { + .name =3D "intel-pps-gen-tio", + .acpi_match_table =3D intel_pmc_tio_acpi_match, + }, +}; +module_platform_driver(pps_gen_tio_driver); + +MODULE_AUTHOR("Christopher Hall "); +MODULE_AUTHOR("Lakshmi Sowjanya D "); +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Thejesh Reddy T R "); +MODULE_AUTHOR("Subramanian Mohan "); +MODULE_DESCRIPTION("Intel PMC Time-Aware IO Generator Driver"); +MODULE_LICENSE("GPL"); --=20 2.35.3 From nobody Thu Mar 13 00:18:38 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 920A222333E; Fri, 14 Feb 2025 09:08:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739524118; cv=none; b=eqFqf3iO4LhgFEP+/e5usv+Eme0m6BxtulGT76KGr/264c5r/rTrFPFV4EpXCbpq9PlRTENXPook5jcgACqVHGoz9ZBQqYdzb5hPXpJDXCKuuq/yO083YF3dzKSasnMYQwjat9Lpo/iOBOVr9XhfefpQqVfVG1seUV/kgN8LDmk= ARC-Message-Signature: i=1; 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charset="utf-8" From: Subramanian Mohan Add Intel Timed I/O PPS usage instructions. Co-developed-by: Pandith N Signed-off-by: Pandith N Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Andy Shevchenko Acked-by: Rodolfo Giometti Signed-off-by: Subramanian Mohan --- Documentation/driver-api/pps.rst | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/driver-api/pps.rst b/Documentation/driver-api/pp= s.rst index 04f1b88778fc..598729f9cd27 100644 --- a/Documentation/driver-api/pps.rst +++ b/Documentation/driver-api/pps.rst @@ -285,3 +285,27 @@ delay between assert and clear edge as small as possib= le to reduce system latencies. But if it is too small slave won't be able to capture clear edge transition. The default of 30us should be good enough in most situations. The delay can be selected using 'delay' pps_gen_parport module parameter. + + +Intel Timed I/O PPS signal generator +------------------------------------ + +Intel Timed I/O is a high precision device, present on 2019 and newer Intel +CPUs, that can generate PPS signals. + +Timed I/O and system time are both driven by same hardware clock. The sign= al +is generated with a precision of ~20 nanoseconds. The generated PPS signal +is used to synchronize an external device with system clock. For example, +it can be used to share your clock with a device that receives PPS signal, +generated by Timed I/O device. There are dedicated Timed I/O pins to deliv= er +the PPS signal to an external device. + +Usage of Intel Timed I/O as PPS generator: + +Start generating PPS signal:: + + $echo 1 > /sys/class/pps-gen/pps-genx/enable + +Stop generating PPS signal:: + + $echo 0 > /sys/class/pps-gen/pps-genx/enable --=20 2.35.3 From nobody Thu Mar 13 00:18:38 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AB78C22D78E; Fri, 14 Feb 2025 09:08:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.10 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739524120; cv=none; b=GnGYDrd1f73raz/Qdcg91SgoXnrkBUE4gTBgEBBlF0qvF8ZEcMYzUPk5ZGtXCoyOpfNfcTg5NCvGe0jQBPObPGJYd5G4le5JLzFNJ+0BRTIzIRuY9TnNlznRIehnmviHlhJE9CAlrlG6CJpT6TH+LF/6f+BfvAsPvdO5usV1Zyg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739524120; c=relaxed/simple; bh=BUMwJBFmmCgIajK9QzBHIVRRQQs+ucHortjyYy4kOlA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=CYZcCjSBOpTH+Tlfws089Aj064ss1OaTgy2RqrkOC1N/UayGTujVLWoLqLgS4lj4gMfs7zPbEv1txlQMoMjebiuj7SUn799olTmvxL01Bo9Y1gqjMhVb+vKoIMkGDD7vV2qEZNqeIialyEA8bjzWyMkBEpYZFJh/LZGEzIGXbUg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=lW5Sqw8u; arc=none smtp.client-ip=192.198.163.10 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="lW5Sqw8u" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1739524118; x=1771060118; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BUMwJBFmmCgIajK9QzBHIVRRQQs+ucHortjyYy4kOlA=; b=lW5Sqw8u3VYG3ORmeDG7C/rInQ3sFMmhMj2CkmtMesEwjnjIKKNjWxEv r0jOKUwihzreKPIBU7obTHvwPxONni2GISh0oV/iTCNk+nFXGOaKYA0na 5zvUyOOF35osxUCytmSSov9BSoPP38Hb6+1d4UhuMf/EXk2fvkmUvFhrH BH/addoc/zanekB1a57rS10bo7im53siD3jMBEij0iJSJ2LsNG845syul VMDwn29W3w9/3GHvqgOBnnjVnzAQA5RP0NeonIWUZakAU5OyLhNL4v/tb 5DOhoxL5opBOO/Z6rZmiodWWXoMOpkH3n1d4TO22NayqnK86C6u7JycM7 Q==; X-CSE-ConnectionGUID: YZnCUAjESD+tX50x9hC0nA== X-CSE-MsgGUID: LftW7VUFSXWRWhluL5dCrA== X-IronPort-AV: E=McAfee;i="6700,10204,11314"; a="51694826" X-IronPort-AV: E=Sophos;i="6.12,310,1728975600"; d="scan'208";a="51694826" Received: from orviesa008.jf.intel.com ([10.64.159.148]) by fmvoesa104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Feb 2025 01:08:37 -0800 X-CSE-ConnectionGUID: xEU9KErcT6WzBy7ZE4IcHA== X-CSE-MsgGUID: DBiIPmSkQxajPbyzEHgpIA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="114303155" Received: from inlubt0246.iind.intel.com ([10.191.24.87]) by orviesa008.jf.intel.com with ESMTP; 14 Feb 2025 01:08:19 -0800 From: subramanian.mohan@intel.com To: linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, gregkh@linuxfoundation.org, andriy.shevchenko@linux.intel.com, giometti@enneenne.com, tglx@linutronix.de, corbet@lwn.net Cc: eddie.dong@intel.com, christopher.s.hall@intel.com, pandith.n@intel.com, thejesh.reddy.t.r@intel.com, david.zage@intel.com, srinivasan.chinnadurai@intel.com, subramanian.mohan@intel.com Subject: [PATCH v14 4/4] ABI: pps: Add ABI documentation for Intel TIO Date: Fri, 14 Feb 2025 14:37:55 +0530 Message-Id: <20250214090755.37450-5-subramanian.mohan@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20250214090755.37450-1-subramanian.mohan@intel.com> References: <20250214090755.37450-1-subramanian.mohan@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Subramanian Mohan Document sysfs interface for Intel Timed I/O PPS driver. Signed-off-by: Lakshmi Sowjanya D Signed-off-by: Subramanian Mohan --- Documentation/ABI/testing/sysfs-pps-gen-tio | 6 ++++++ MAINTAINERS | 1 + 2 files changed, 7 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-pps-gen-tio diff --git a/Documentation/ABI/testing/sysfs-pps-gen-tio b/Documentation/AB= I/testing/sysfs-pps-gen-tio new file mode 100644 index 000000000000..3c34ff17a335 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-pps-gen-tio @@ -0,0 +1,6 @@ +What: /sys/class/pps-gen/pps-genx/enable +Date: April 2025 +KernelVersion: 6.15 +Contact: Subramanian Mohan +Description: + Enable or disable PPS TIO generator output. diff --git a/MAINTAINERS b/MAINTAINERS index 25c86f47353d..d4280facbe51 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -18916,6 +18916,7 @@ S: Maintained W: http://wiki.enneenne.com/index.php/LinuxPPS_support F: Documentation/ABI/testing/sysfs-pps F: Documentation/ABI/testing/sysfs-pps-gen +F: Documentation/ABI/testing/sysfs-pps-gen-tio F: Documentation/devicetree/bindings/pps/pps-gpio.yaml F: Documentation/driver-api/pps.rst F: drivers/pps/ --=20 2.35.3