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Fri, 14 Feb 2025 07:09:06 -0800 (PST) From: Krzysztof Kozlowski Date: Fri, 14 Feb 2025 16:08:42 +0100 Subject: [PATCH v3 2/4] drm/msm/dsi/phy: Protect PHY_CMN_CLK_CFG1 against clock driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250214-drm-msm-phy-pll-cfg-reg-v3-2-0943b850722c@linaro.org> References: <20250214-drm-msm-phy-pll-cfg-reg-v3-0-0943b850722c@linaro.org> In-Reply-To: <20250214-drm-msm-phy-pll-cfg-reg-v3-0-0943b850722c@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jonathan Marek Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Clark , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5326; i=krzysztof.kozlowski@linaro.org; h=from:subject:message-id; bh=6d31yt4/0eptwO5sGCeUjo/cybg3SpE5A04xzTo+AZY=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBnr1yL+xzURKrXVULWEQh05QUgv0y4Y0lrn+IEx 5chLHR69UCJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCZ69ciwAKCRDBN2bmhouD 1yuLD/4p8DmI9eKNYanA+xTsZEo0UJl6ywYkRn28tea7zP+jjDPOfWaCoA4yBHsfrJj6IVmGqD9 EL6XgU+E0Y1vGWDewD6C3tRqSR+OX7htPd78K4u86nS+SeHOh1Vnzq1hU5/YpkxHyD5hittrKkH IrvRoTEIXGRv+df0CsYI9yXbGZ0UJFVwkF469XFNUmSisj4CcyLuewVCKvTndYkgD+R5sm9Ws62 bxE+Gh9+4nmgTH+zZpO8yJJuPXGuBQ9LifTyJasA//js7UL3qMtGx585J2sa5hetIZpvGoRc2pl e9FLSYyNnLBubP47XBP//4RyI9oHvpkoCRh7PmKsKSO35wN9gGIo5I+g/R9F4PKlReFtSUxgiO6 G3eKRW+zrD4pk5fTHpZuk+lj4rJrDGLmxKc7k3SdK+bAIrlV3fvjUV0+rnCiU8LTJ52NJRDwZ0U ypfIbunx/dMQhINA1W2i8waz8DeDjDaxFk0fbuqFtoRPo07miWO3bT/Xon6adIr0rcYUN7WUf00 Fon88BPiqm4kY+TS6lGIARveHNB/q+pX0orF5U8HR6zleIEPW+QkxlVvCRjV/1c3X5FHtboIAtB vDtE5Jnf4ONc8lzr3ceRIaDFiTmj6AvWYBUjj+Qx0xA77NsRKmMEMt0Fb7aqJmANKDvN32cDNmY WH8CL8Shbhe7VnQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B PHY_CMN_CLK_CFG1 register is updated by the PHY driver and by a mux clock from Common Clock Framework: devm_clk_hw_register_mux_parent_hws(). There could be a path leading to concurrent and conflicting updates between PHY driver and clock framework, e.g. changing the mux and enabling PLL clocks. Add dedicated spinlock to be sure all PHY_CMN_CLK_CFG1 updates are synchronized. While shuffling the code, define and use PHY_CMN_CLK_CFG1 bitfields to make the code more readable and obvious. Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL") Signed-off-by: Krzysztof Kozlowski Reviewed-by: Abhinav Kumar Reviewed-by: Dmitry Baryshkov --- Changes in v3: 1. Define bitfields (move here parts from patch #4) Changes in v2: 1. Store BIT(4) and BIT(5) in local var in dsi_pll_enable_global_clk() --- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 35 ++++++++++++++----= ---- .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 5 +++- 2 files changed, 26 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index 25ca649de717eaeec603c520bbaa603ece244d3c..388017db45d802c4ef1299296f9= 32c4182512aae 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -83,6 +83,9 @@ struct dsi_pll_7nm { /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG0 register */ spinlock_t postdiv_lock; =20 + /* protects REG_DSI_7nm_PHY_CMN_CLK_CFG1 register */ + spinlock_t pclk_mux_lock; + struct pll_7nm_cached_state cached_state; =20 struct dsi_pll_7nm *slave; @@ -381,22 +384,32 @@ static void dsi_pll_cmn_clk_cfg0_write(struct dsi_pll= _7nm *pll, u32 val) spin_unlock_irqrestore(&pll->postdiv_lock, flags); } =20 -static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) +static void dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm *pll, u32 mask, + u32 val) { + unsigned long flags; u32 data; =20 + spin_lock_irqsave(&pll->pclk_mux_lock, flags); data =3D readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - writel(data & ~BIT(5), pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + data &=3D ~mask; + data |=3D val & mask; + + writel(data, pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + spin_unlock_irqrestore(&pll->pclk_mux_lock, flags); +} + +static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll) +{ + dsi_pll_cmn_clk_cfg1_update(pll, DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN, 0); } =20 static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll) { - u32 data; + u32 cfg_1 =3D DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN | DSI_7nm_PHY_CMN_CLK_CFG1_= CLK_EN_SEL; =20 writel(0x04, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3); - - data =3D readl(pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - writel(data | BIT(5) | BIT(4), pll->phy->base + REG_DSI_7nm_PHY_CMN_CLK_C= FG1); + dsi_pll_cmn_clk_cfg1_update(pll, cfg_1, cfg_1); } =20 static void dsi_pll_phy_dig_reset(struct dsi_pll_7nm *pll) @@ -574,7 +587,6 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy= *phy) { struct dsi_pll_7nm *pll_7nm =3D to_pll_7nm(phy->vco_hw); struct pll_7nm_cached_state *cached =3D &pll_7nm->cached_state; - void __iomem *phy_base =3D pll_7nm->phy->base; u32 val; int ret; =20 @@ -586,11 +598,7 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_ph= y *phy) dsi_pll_cmn_clk_cfg0_write(pll_7nm, DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0(cached->bit_clk_div) | DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4(cached->pix_clk_div)); - - val =3D readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); - val &=3D ~0x3; - val |=3D cached->pll_mux; - writel(val, phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1); + dsi_pll_cmn_clk_cfg1_update(pll_7nm, 0x3, cached->pll_mux); =20 ret =3D dsi_pll_7nm_vco_set_rate(phy->vco_hw, pll_7nm->vco_current_rate, @@ -743,7 +751,7 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm= , struct clk_hw **provide pll_by_2_bit, }), 2, 0, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1, - 0, 1, 0, NULL); + 0, 1, 0, &pll_7nm->pclk_mux_lock); if (IS_ERR(hw)) { ret =3D PTR_ERR(hw); goto fail; @@ -788,6 +796,7 @@ static int dsi_pll_7nm_init(struct msm_dsi_phy *phy) pll_7nm_list[phy->id] =3D pll_7nm; =20 spin_lock_init(&pll_7nm->postdiv_lock); + spin_lock_init(&pll_7nm->pclk_mux_lock); =20 pll_7nm->phy =3D phy; =20 diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/driver= s/gpu/drm/msm/registers/display/dsi_phy_7nm.xml index e0bf6e016b4ce5b35f73fce7b8e371456b88e3ac..cfaf78c028b1325682889a5c2d8= fffd0268122cf 100644 --- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml +++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml @@ -13,7 +13,10 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/fre= edreno/ rules-fd.xsd"> - + + + + --=20 2.43.0