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Thu, 13 Feb 2025 14:03:50 -0800 (PST) From: Samuel Holland To: Arnaldo Carvalho de Melo , Ian Rogers , Palmer Dabbelt , linux-perf-users@vger.kernel.org, linux-riscv@lists.infradead.org Cc: Mark Rutland , Adrian Hunter , Alexander Shishkin , linux-kernel@vger.kernel.org, Jiri Olsa , Peter Zijlstra , Ingo Molnar , Namhyung Kim , Arnaldo Carvalho de Melo , Eric Lin , Samuel Holland Subject: [RESEND PATCH 5/7] perf vendor events riscv: Add SiFive Bullet version 0x0d events Date: Wed, 12 Feb 2025 17:21:38 -0800 Message-ID: <20250213220341.3215660-6-samuel.holland@sifive.com> X-Mailer: git-send-email 2.47.0 In-Reply-To: <20250213220341.3215660-1-samuel.holland@sifive.com> References: <20250213220341.3215660-1-samuel.holland@sifive.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Eric Lin SiFive Bullet microarchitecture cores with mimpid values starting with 0x0d or greater add new PMU events to count TLB miss stall cycles. All other PMU events are unchanged from earlier Bullet cores. Signed-off-by: Eric Lin Signed-off-by: Samuel Holland --- tools/perf/pmu-events/arch/riscv/mapfile.csv | 1 + .../cycle-and-instruction-count.json | 1 + .../arch/riscv/sifive/bullet-0d/firmware.json | 1 + .../riscv/sifive/bullet-0d/instruction.json | 1 + .../arch/riscv/sifive/bullet-0d/memory.json | 1 + .../riscv/sifive/bullet-0d/microarch.json | 72 +++++++++++++++++++ .../riscv/sifive/bullet-0d/watchpoint.json | 1 + 7 files changed, 78 insertions(+) create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle= -and-instruction-count.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmw= are.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instr= uction.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memor= y.json create mode 100644 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/micro= arch.json create mode 120000 tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watch= point.json diff --git a/tools/perf/pmu-events/arch/riscv/mapfile.csv b/tools/perf/pmu-= events/arch/riscv/mapfile.csv index 8706d289215e..9e9bd7ac0ebe 100644 --- a/tools/perf/pmu-events/arch/riscv/mapfile.csv +++ b/tools/perf/pmu-events/arch/riscv/mapfile.csv @@ -16,6 +16,7 @@ #MVENDORID-MARCHID-MIMPID,Version,Filename,EventType 0x489-0x8000000000000007-0x[[:xdigit:]]+,v1,sifive/bullet,core 0x489-0x8000000000000[1-9a-e]07-0x[78ac][[:xdigit:]]+,v1,sifive/bullet-07,= core +0x489-0x8000000000000[1-9a-e]07-0xd[[:xdigit:]]+,v1,sifive/bullet-0d,core 0x5b7-0x0-0x0,v1,thead/c900-legacy,core 0x67e-0x80000000db0000[89]0-0x[[:xdigit:]]+,v1,starfive/dubhe-80,core 0x31e-0x8000000000008a45-0x[[:xdigit:]]+,v1,andes/ax45,core diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-in= struction-count.json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cy= cle-and-instruction-count.json new file mode 120000 index 000000000000..ccd29278f61b --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/cycle-and-instructi= on-count.json @@ -0,0 +1 @@ +../bullet-07/cycle-and-instruction-count.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.jso= n b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json new file mode 120000 index 000000000000..34e5c2870eee --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/firmware.json @@ -0,0 +1 @@ +../bullet/firmware.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.= json b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json new file mode 120000 index 000000000000..62eacc2d7497 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/instruction.json @@ -0,0 +1 @@ +../bullet/instruction.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json = b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json new file mode 120000 index 000000000000..df50fc47a5fe --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/memory.json @@ -0,0 +1 @@ +../bullet/memory.json \ No newline at end of file diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.js= on b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json new file mode 100644 index 000000000000..6573b24788eb --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/microarch.json @@ -0,0 +1,72 @@ +[ + { + "EventName": "ADDRESSGEN_INTERLOCK", + "EventCode": "0x101", + "BriefDescription": "Counts cycles with an address-generation interloc= k" + }, + { + "EventName": "LONGLATENCY_INTERLOCK", + "EventCode": "0x201", + "BriefDescription": "Counts cycles with a long-latency interlock" + }, + { + "EventName": "CSR_INTERLOCK", + "EventCode": "0x401", + "BriefDescription": "Counts cycles with a CSR interlock" + }, + { + "EventName": "ICACHE_BLOCKED", + "EventCode": "0x801", + "BriefDescription": "Counts cycles in which the instruction cache was = not able to provide an instruction" + }, + { + "EventName": "DCACHE_BLOCKED", + "EventCode": "0x1001", + "BriefDescription": "Counts cycles in which the data cache blocked an = instruction" + }, + { + "EventName": "BRANCH_DIRECTION_MISPREDICTION", + "EventCode": "0x2001", + "BriefDescription": "Counts mispredictions of conditional branch direc= tion (taken/not taken)" + }, + { + "EventName": "BRANCH_TARGET_MISPREDICTION", + "EventCode": "0x4001", + "BriefDescription": "Counts mispredictions of the target PC of control= -flow instructions" + }, + { + "EventName": "PIPELINE_FLUSH", + "EventCode": "0x8001", + "BriefDescription": "Counts flushes of the core pipeline. Common cause= s include fence.i and CSR accesses" + }, + { + "EventName": "REPLAY", + "EventCode": "0x10001", + "BriefDescription": "Counts instruction replays" + }, + { + "EventName": "INTEGER_MUL_DIV_INTERLOCK", + "EventCode": "0x20001", + "BriefDescription": "Counts cycles with a multiply or divide interlock" + }, + { + "EventName": "FP_INTERLOCK", + "EventCode": "0x40001", + "BriefDescription": "Counts cycles with a floating-point interlock" + }, + { + "EventName": "TRACE_STALL", + "EventCode": "0x80001", + "BriefDescription": "Counts cycles in which the core pipeline is stall= ed due to backpressure from the Trace Encoder" + }, + { + "EventName": "ITLB_MISS_STALL", + "EventCode": "0x100001", + "BriefDescription": "Counts cycles in which the core pipeline is stall= ed due to ITLB Miss" + }, + { + "EventName": "DTLB_MISS_STALL", + "EventCode": "0x200001", + "BriefDescription": "Counts cycles in which the core pipeline is stall= ed due to DTLB Miss" + } +] diff --git a/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.j= son b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json new file mode 120000 index 000000000000..e88b98bfc5c8 --- /dev/null +++ b/tools/perf/pmu-events/arch/riscv/sifive/bullet-0d/watchpoint.json @@ -0,0 +1 @@ +../bullet-07/watchpoint.json \ No newline at end of file --=20 2.47.0