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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aba533998e2sm181360466b.134.2025.02.13.10.46.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 10:46:26 -0800 (PST) From: Alexander Sverdlin To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-rtc@vger.kernel.org Cc: Jingbao Qiu , Inochi Amaoto , alexandre.belloni@bootlin.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, unicorn_wang@outlook.com, inochiama@outlook.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, dlan@gentoo.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Alexander Sverdlin Subject: [PATCH v10 1/2] dt-bindings: rtc: sophgo: add RTC support for Sophgo CV1800 series SoC Date: Thu, 13 Feb 2025 19:46:14 +0100 Message-ID: <20250213184622.2099324-2-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250213184622.2099324-1-alexander.sverdlin@gmail.com> References: <20250213184622.2099324-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jingbao Qiu Add RTC devicetree binding for Sophgo CV1800 SoC. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Jingbao Qiu Signed-off-by: Alexander Sverdlin --- .../bindings/rtc/sophgo,cv1800-rtc.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc= .yaml diff --git a/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml b= /Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml new file mode 100644 index 000000000000..b36b51a69166 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/sophgo,cv1800-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Real Time Clock of the Sophgo CV1800 SoC + +description: + Real Time Clock (RTC) is an independently powered module + within the chip, which includes a 32KHz oscillator and a + Power On Reset/POR submodule. It can be used for time display + and timed alarm generation. In addition, the hardware state + machine provides triggering and timing control for chip + power on, off, and reset. + +maintainers: + - Jingbao Qiu + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + const: sophgo,cv1800-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + + rtc@5025000 { + compatible =3D "sophgo,cv1800-rtc"; + reg =3D <0x5025000 0x2000>; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&osc>; + }; --=20 2.48.1 From nobody Thu Dec 18 20:17:28 2025 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FE2D24A048; Thu, 13 Feb 2025 18:46:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739472391; cv=none; b=qEbdox3hKTUK4EeXhNDWf8cEZKOwz1lJcQbxCMx+98gnqf0q3FouRlEOq3SCuUUlBALe+LyiSRebuv9vTMI+wgbJpmoEM/A6RmNNuDQcxKJOk16GpLFqqPBNDm2apJ46+b80hB8NSHI4K1d53l7UUt0myOcDmCIzjwNZKo7iRiY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739472391; c=relaxed/simple; bh=zixQ5GhQTzBFHCTrvdtATSSH17XYTJ67wS2V/FdC7hc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DXulh6iXaOBrLRbC6RGcvsFJ8mUKFxA3GYvyYUPVJauM0AUf0UCHaS7ilnXGmwRbv84nNclKsHjSYUScuZGGvsLKCDM5z0rJETXWpRcmGfUuv+cBWsxPBjuw1ALk3H3okB/Rpw8Ntdoft7SxqBU5bpueemH5r84VEtPQOdtxCFk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=nAPmn8F5; arc=none smtp.client-ip=209.85.218.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="nAPmn8F5" Received: by mail-ej1-f42.google.com with SMTP id a640c23a62f3a-aaec61d0f65so290055566b.1; Thu, 13 Feb 2025 10:46:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1739472387; x=1740077187; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HaEihAiyP6MocC5Oa52F4VzuNeOxClEAtoQkxcRqaYg=; b=nAPmn8F5FJI6V+sEFCq/vfyEIAaj39m2iDSiHP8nFwG9arElScXkuK2c9DPKe0ITxp gULwJph89d7F40xZ2Qq3e+D1ex2KmotOFr3WArn51kJFpVivisrQmjewtIblFIlVCIiJ RPgau0BU7kXvoUTOmT0imQNUYwR/PTKaccFp3JuJW1NefM4tdj40JrxhxOmGQEGxtpSx bfZHeHpRCKnS6+LBFHVnLp/k6jKSFgo2Xba1HRuYUWasiI3tgSwkO7Mc49vOE0bvqG5e 9RPYDqvQ4dKLIBulY5kal3trmMQ2nXBOsjlVLf97AzfGg+XOET7jX3BmlGUHPtA9nZb/ LoZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739472387; x=1740077187; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HaEihAiyP6MocC5Oa52F4VzuNeOxClEAtoQkxcRqaYg=; b=Dkb39iXX9RksMapJH2NUrEDRBO7iIUbZzxuM3xjI5xMYpfl2USQvndBIJsogMQk/W1 pshT7YdbZWzSXtNVSZXXu39+WNSA75KfuxrR5+n37Hem0T8U58vd4Ood0P1YOzsdKjk/ AVnMkvk0RMhs/irUL+ElyCey4DWsvDIZEZlMd5cN3ixsADZIfiOBnoUCO4cvRSteMoOO 9jdNpo8/sy6pXd1e3ZOJblUaSG0mx1j0/oOXDkeuGjH4bBs/CJtfvgMZNdFQ4R5B1c1J iSCQDgMtp7E/OGn5ZZxhLnBivRUPurT+x0PhJDN1DCywcwtCGukeXCjH5S0Mf3zheT2x mThw== X-Forwarded-Encrypted: i=1; AJvYcCUGHXxu5xAg8OzlCJkbf5UfM4sQbDD1DAQbXhMQ9qy5+0mUQO5EePHNxyZSOgXjYTSkWaGUrhSp8BRK@vger.kernel.org, AJvYcCUjeFh3KsfCMROy8g8FZh6Cvbfte0ys/ND5wF+koLPIATQ+7/6e2Y5hw1OSYoNnSyK2HDvTe4BUKgEo2pRw@vger.kernel.org, AJvYcCUufiGXF6kbHMRtTAvVbjdAptYAx4QkcPqcw3U+69Ns/sM+Jg/gcx4FYDt3pSjQAIxmwzVhcai8D91k@vger.kernel.org X-Gm-Message-State: AOJu0YzAT50xVQSOe5E6asiqiSdjB29VJBpavAZ+wjtIGEph7fyS/RaE OI5sKckFhOMi9oTT2ZTHx79P6uHotcGbMTvp3vWTDRO0opzs42uR X-Gm-Gg: ASbGncu+PhOhFcOCsVo5kXRSIWy0/th/4U5wKBJOTGPmDYa0lKPZ4PJkjD8P0B6V/MB ODaLbjE0hkZEXpE6htW+P1hGOh7e9RYR+u44QGl0rehxJ3mu0ko6goY8dVJICmRfmrMcSFhLfCM P/mCFbX2RMmeYgEdDsNezyXcrHu+FMgAXxH0IUANejKtPUta4wzxGuc9s5wCydZ5ZwqnEiChs/Q KZTvBvbsMXrFKaBPTy6KpXx6E4U/wUbTVMwYngFBdY3H1Eou6EW9UZ8edPnVPSmzLQ39Qp0N0KR CG0p4/lrp4ibHahMgtL+3iKVJqXD X-Google-Smtp-Source: AGHT+IGGkWWLaNNzOzd7hKMrdf41hfYgyJmTTQbUi197zNRcg+XO4S8rTNRAVGB7tDq/vKYEFmIXRw== X-Received: by 2002:a17:906:6a23:b0:ab6:dace:e763 with SMTP id a640c23a62f3a-aba5017e5d9mr408825466b.38.1739472387157; Thu, 13 Feb 2025 10:46:27 -0800 (PST) Received: from giga-mm.. ([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aba533998e2sm181360466b.134.2025.02.13.10.46.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 10:46:26 -0800 (PST) From: Alexander Sverdlin To: linux-riscv@lists.infradead.org, linux-rtc@vger.kernel.org Cc: Jingbao Qiu , Inochi Amaoto , alexandre.belloni@bootlin.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, unicorn_wang@outlook.com, inochiama@outlook.com, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, dlan@gentoo.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Alexander Sverdlin Subject: [PATCH v10 2/2] rtc: sophgo: add rtc support for Sophgo CV1800 SoC Date: Thu, 13 Feb 2025 19:46:15 +0100 Message-ID: <20250213184622.2099324-3-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250213184622.2099324-1-alexander.sverdlin@gmail.com> References: <20250213184622.2099324-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jingbao Qiu Implement the RTC driver for CV1800, which able to provide time alarm. Signed-off-by: Jingbao Qiu Signed-off-by: Alexander Sverdlin --- Changes since v9: - further simplified bitmask macros; - unconditional RTC start (rtc_enable_sec_counter()), otherwise didn't start on SG2000; - dropped ANA_CALIB modification (has been forgotten in v8 with the drop of SW calibration to switch to HW calibration); - successfully tested on SG2000; drivers/rtc/Kconfig | 10 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-cv1800.c | 223 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 234 insertions(+) create mode 100644 drivers/rtc/rtc-cv1800.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 0bbbf778ecfa..019622db3e93 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1159,6 +1159,16 @@ config RTC_DRV_DS2404 This driver can also be built as a module. If so, the module will be called rtc-ds2404. =20 +config RTC_DRV_CV1800 + tristate "Sophgo CV1800 RTC" + depends on ARCH_SOPHGO || COMPILE_TEST + help + If you say yes here you get support the RTC driver + for Sophgo CV1800 chip. + + This driver can also be built as a module. If so, the + module will be called rtc-cv1800. + config RTC_DRV_DA9052 tristate "Dialog DA9052/DA9053 RTC" depends on PMIC_DA9052 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 489b4ab07068..621b30a33dda 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_RTC_DRV_CADENCE) +=3D rtc-cadence.o obj-$(CONFIG_RTC_DRV_CMOS) +=3D rtc-cmos.o obj-$(CONFIG_RTC_DRV_CPCAP) +=3D rtc-cpcap.o obj-$(CONFIG_RTC_DRV_CROS_EC) +=3D rtc-cros-ec.o +obj-$(CONFIG_RTC_DRV_CV1800) +=3D rtc-cv1800.o obj-$(CONFIG_RTC_DRV_DA9052) +=3D rtc-da9052.o obj-$(CONFIG_RTC_DRV_DA9055) +=3D rtc-da9055.o obj-$(CONFIG_RTC_DRV_DA9063) +=3D rtc-da9063.o diff --git a/drivers/rtc/rtc-cv1800.c b/drivers/rtc/rtc-cv1800.c new file mode 100644 index 000000000000..63d36f68a119 --- /dev/null +++ b/drivers/rtc/rtc-cv1800.c @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * rtc-cv1800.c: RTC driver for Sophgo cv1800 RTC + * + * Author: Jingbao Qiu + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SEC_PULSE_GEN 0x1004 +#define ALARM_TIME 0x1008 +#define ALARM_ENABLE 0x100C +#define SET_SEC_CNTR_VAL 0x1010 +#define SET_SEC_CNTR_TRIG 0x1014 +#define SEC_CNTR_VAL 0x1018 + +/* + * When in VDDBKUP domain, this MACRO register + * does not power down + */ +#define MACRO_RO_T 0x14A8 +#define MACRO_RG_SET_T 0x1498 + +#define ALARM_ENABLE_MASK BIT(0) +#define SET_SEC_CNTR_VAL_INIT GENMASK(29, 28) +#define SEL_SEC_PULSE BIT(31) + +struct cv1800_rtc_priv { + struct rtc_device *rtc_dev; + struct regmap *rtc_map; + struct clk *clk; + int irq; +}; + +static const struct regmap_config cv1800_rtc_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, +}; + +static int cv1800_rtc_alarm_irq_enable(struct device *dev, unsigned int en= abled) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + + regmap_write(info->rtc_map, ALARM_ENABLE, enabled); + + return 0; +} + +static int cv1800_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alr= m) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + unsigned long alarm_time; + + alarm_time =3D rtc_tm_to_time64(&alrm->time); + + cv1800_rtc_alarm_irq_enable(dev, 0); + + regmap_write(info->rtc_map, ALARM_TIME, alarm_time); + + cv1800_rtc_alarm_irq_enable(dev, alrm->enabled); + + return 0; +} + +static int cv1800_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *al= arm) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + u32 enabled; + u32 time; + + regmap_read(info->rtc_map, ALARM_ENABLE, &enabled); + + alarm->enabled =3D enabled & ALARM_ENABLE_MASK; + + regmap_read(info->rtc_map, ALARM_TIME, &time); + + rtc_time64_to_tm(time, &alarm->time); + + return 0; +} + +static void rtc_enable_sec_counter(struct cv1800_rtc_priv *info) +{ + u32 sec_ro_t; + u32 sec; + + /* select inner sec pulse */ + regmap_update_bits(info->rtc_map, SEC_PULSE_GEN, SEL_SEC_PULSE, 0); + + sec =3D SET_SEC_CNTR_VAL_INIT; + + /* load from MACRO register */ + regmap_read(info->rtc_map, MACRO_RO_T, &sec_ro_t); + if (sec_ro_t > (SET_SEC_CNTR_VAL_INIT)) + sec =3D sec_ro_t; + + regmap_write(info->rtc_map, SET_SEC_CNTR_VAL, sec); + regmap_write(info->rtc_map, SET_SEC_CNTR_TRIG, 1); +} + +static int cv1800_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + u32 sec; + + regmap_read(info->rtc_map, SEC_CNTR_VAL, &sec); + + rtc_time64_to_tm(sec, tm); + + return 0; +} + +static int cv1800_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + unsigned long sec; + + sec =3D rtc_tm_to_time64(tm); + + regmap_write(info->rtc_map, SET_SEC_CNTR_VAL, sec); + regmap_write(info->rtc_map, SET_SEC_CNTR_TRIG, 1); + + regmap_write(info->rtc_map, MACRO_RG_SET_T, sec); + + return 0; +} + +static irqreturn_t cv1800_rtc_irq_handler(int irq, void *dev_id) +{ + struct cv1800_rtc_priv *info =3D dev_id; + + rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); + + regmap_write(info->rtc_map, ALARM_ENABLE, 0); + + return IRQ_HANDLED; +} + +static const struct rtc_class_ops cv1800_rtc_ops =3D { + .read_time =3D cv1800_rtc_read_time, + .set_time =3D cv1800_rtc_set_time, + .read_alarm =3D cv1800_rtc_read_alarm, + .set_alarm =3D cv1800_rtc_set_alarm, + .alarm_irq_enable =3D cv1800_rtc_alarm_irq_enable, +}; + +static int cv1800_rtc_probe(struct platform_device *pdev) +{ + struct cv1800_rtc_priv *rtc; + u32 ctrl_val; + void __iomem *base; + int ret; + + rtc =3D devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + rtc->rtc_map =3D devm_regmap_init_mmio(&pdev->dev, base, + &cv1800_rtc_regmap_config); + if (IS_ERR(rtc->rtc_map)) + return PTR_ERR(rtc->rtc_map); + + rtc->irq =3D platform_get_irq(pdev, 0); + if (rtc->irq < 0) + return rtc->irq; + + rtc->clk =3D devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(rtc->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(rtc->clk), + "clk not found\n"); + + platform_set_drvdata(pdev, rtc); + + device_init_wakeup(&pdev->dev, 1); + + rtc->rtc_dev =3D devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rtc->rtc_dev)) + return PTR_ERR(rtc->rtc_dev); + + rtc->rtc_dev->ops =3D &cv1800_rtc_ops; + rtc->rtc_dev->range_max =3D U32_MAX; + + ret =3D devm_request_irq(&pdev->dev, rtc->irq, cv1800_rtc_irq_handler, + IRQF_TRIGGER_HIGH, "rtc alarm", rtc); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "cannot register interrupt handler\n"); + + rtc_enable_sec_counter(rtc); + + return devm_rtc_register_device(rtc->rtc_dev); +} + +static const struct of_device_id cv1800_dt_ids[] =3D { + { .compatible =3D "sophgo,cv1800-rtc" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, cv1800_dt_ids); + +static struct platform_driver cv1800_rtc_driver =3D { + .driver =3D { + .name =3D "sophgo-cv1800-rtc", + .of_match_table =3D cv1800_dt_ids, + }, + .probe =3D cv1800_rtc_probe, +}; + +module_platform_driver(cv1800_rtc_driver); +MODULE_AUTHOR("Jingbao Qiu"); +MODULE_DESCRIPTION("Sophgo cv1800 RTC Driver"); +MODULE_LICENSE("GPL"); --=20 2.48.1