From nobody Fri Dec 19 04:56:23 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 54B4226E167; Thu, 13 Feb 2025 18:03:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469815; cv=none; b=DJkZnvEiLayYujiNmK4z+PUJlG4/chJ5TXc7+uJT1ozISdFzEDT/HLF0/7H+MY3AldyTjmjNcM4OIKcz9fczEWlKuiHFtYIi0e3+A7GFKFEdZ5/SW5+i7myDNmWHDaozI1iFUzeQ/wwhJgl4UTAW5239RT/3FhJ/xd3LgHA8lkc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469815; c=relaxed/simple; bh=nFLzdJMmng0/cPrvH9BD7ODJNvkZv6eLc+v3ZGguiYs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iwPC2XO8f5bl0ePMOfugS4CtrWyF2J1AVRO6URb7wdG/ahQu6eq+QCWWNf74EGq8LMemQrJffp6Q33TPgTV5RE2+xpv4NFd6iS2v74hlCoZHLMcnxkzULqAkZEXC7FmDFluwMviQVlMl3WUJesUudDnZmcOkIR16hkPp69GpoNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3E51B26AC; Thu, 13 Feb 2025 10:03:54 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B3543F5A1; Thu, 13 Feb 2025 10:03:31 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland Subject: [PATCH v5 4/8] perf: arm_pmuv3: Add support for ARM Rainier PMU Date: Thu, 13 Feb 2025 18:03:05 +0000 Message-ID: <20250213180309.485528-5-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250213180309.485528-1-vincenzo.frascino@arm.com> References: <20250213180309.485528-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the ARM Rainier CPU core PMU. Note: Coherently, add dt bindings for the same PMU. Signed-off-by: Vincenzo Frascino --- Documentation/devicetree/bindings/arm/pmu.yaml | 1 + drivers/perf/arm_pmuv3.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation= /devicetree/bindings/arm/pmu.yaml index a148ff54f2b8..295963a3cae7 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -67,6 +67,7 @@ properties: - arm,neoverse-v2-pmu - arm,neoverse-v3-pmu - arm,neoverse-v3ae-pmu + - arm,rainier-pmu - brcm,vulcan-pmu - cavium,thunder-pmu - nvidia,denver-pmu diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 0e360feb3432..3785522a08e7 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -1369,6 +1369,7 @@ PMUV3_INIT_SIMPLE(armv8_neoverse_v1) PMUV3_INIT_SIMPLE(armv8_neoverse_v2) PMUV3_INIT_SIMPLE(armv8_neoverse_v3) PMUV3_INIT_SIMPLE(armv8_neoverse_v3ae) +PMUV3_INIT_SIMPLE(armv8_rainier) =20 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) PMUV3_INIT_SIMPLE(armv8_nvidia_denver) @@ -1416,6 +1417,7 @@ static const struct of_device_id armv8_pmu_of_device_= ids[] =3D { {.compatible =3D "arm,neoverse-v2-pmu", .data =3D armv8_neoverse_v2_pmu_i= nit}, {.compatible =3D "arm,neoverse-v3-pmu", .data =3D armv8_neoverse_v3_pmu_i= nit}, {.compatible =3D "arm,neoverse-v3ae-pmu", .data =3D armv8_neoverse_v3ae_p= mu_init}, + {.compatible =3D "arm,rainier-pmu", .data =3D armv8_rainier_pmu_init}, {.compatible =3D "cavium,thunder-pmu", .data =3D armv8_cavium_thunder_pmu= _init}, {.compatible =3D "brcm,vulcan-pmu", .data =3D armv8_brcm_vulcan_pmu_init}, {.compatible =3D "nvidia,carmel-pmu", .data =3D armv8_nvidia_carmel_pmu_i= nit}, --=20 2.43.0