From nobody Thu Dec 18 20:20:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 61E99269890; Thu, 13 Feb 2025 18:03:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469808; cv=none; b=qiCfnUpNqNf8A078UBSCAwaiiRwohCMyAwH67MEvMO6MivFf6ytxqTS50apH/eo8JAhKRjjQPSo65WO3lou1VwBCdcYfQPC7cHq41NCrIQ3e+jifT5gEV5r7iMgI4+ewevSceUzKriLd7Lx/VtBMcQstX9fOu64ZMeZTXgxdVB8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469808; c=relaxed/simple; bh=alOB/Br9RTOAeChsNpTtYQOV4peB0PY01d4EnCBvcbY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=B3vjHECgAwsp3oDL9H7KMRTSRKLrm1zKsYEyoh5ON5z+V0hxrvvYsmkKdTbFB+i5pGX9ckbCYHzVIyBzUC2/kj0v3ySzCaRkRi5Z01hI1tbBlAb8+dt2vBGUw40t/MHuX6iRMV8XR+B7GYWzjOugjjEPMe5yjHsrd+ej50juYzw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5735926AC; Thu, 13 Feb 2025 10:03:47 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 96FF03F5A1; Thu, 13 Feb 2025 10:03:24 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Krzysztof Kozlowski Subject: [PATCH v5 1/8] dt-bindings: arm: Add Morello compatibility Date: Thu, 13 Feb 2025 18:03:02 +0000 Message-ID: <20250213180309.485528-2-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250213180309.485528-1-vincenzo.frascino@arm.com> References: <20250213180309.485528-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatibility to Arm Morello System Development Platform. Note: Morello is at the same time the name of an Architecture [1], an SoC [2] and a Board [2]. To distinguish in between Architecture/SoC and Board we refer to the first as arm,morello and to the second as arm,morello-sdp. [1] https://developer.arm.com/Architectures/Morello [2] https://www.morello-project.org/ Acked-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino --- Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b= /Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index 8dd6b6446394..40e7910756c8 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -118,6 +118,10 @@ properties: items: - const: arm,foundation-aarch64 - const: arm,vexpress + - description: Arm Morello System Development Platform + items: + - const: arm,morello-sdp + - const: arm,morello =20 arm,vexpress,position: description: When daughterboards are stacked on one site, their positi= on --=20 2.43.0 From nobody Thu Dec 18 20:20:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B1C5926B09A; Thu, 13 Feb 2025 18:03:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469811; cv=none; b=KJiq/Hb7sNVTky+v9FeSbrXX1z/3kG0IjKWhU6oohZM+TjeKDz2OOnWWDicOrhZ3s28/R0++XqQlyLE75KlzTwPzqG4P+CdSd7FNgeob34oOTTReqMaqBY9kQTZV+IrYWUzLfOF+xOZBcQ7rHHUhjxWtXSWhGRvcxXJdEOR024U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469811; c=relaxed/simple; bh=hhSMDrnYWM0XfhOjrWsUcqBSX+Tit8Rh46MH2d1ny0E=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PzhoJlAYVnIqvy9dGP/G3WEqVKM0mhHsKuID9SyPr8vDfnSs7fx639GdGF3BSl2o8F8Q0pterwuajfX4OEck47VVd9Z+NKLeUnAvSJSDtm+FmTQ1crrSUa6uOVqlJZzlpTTabDaienaFaWZ+n3fBO6xNwv7CR7056tUWhv/KtA0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9F0C6113E; Thu, 13 Feb 2025 10:03:49 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0A4903F5A1; Thu, 13 Feb 2025 10:03:26 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland Subject: [PATCH v5 2/8] dt-bindings: arm: Add Morello fvp compatibility Date: Thu, 13 Feb 2025 18:03:03 +0000 Message-ID: <20250213180309.485528-3-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250213180309.485528-1-vincenzo.frascino@arm.com> References: <20250213180309.485528-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add compatibility to Arm Morello Fixed Virtual Platform. Signed-off-by: Vincenzo Frascino --- Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b= /Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index 40e7910756c8..e71e3e33c4be 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -122,6 +122,10 @@ properties: items: - const: arm,morello-sdp - const: arm,morello + - description: Arm Morello Fixed Virtual Platform + items: + - const: arm,morello-fvp + - const: arm,morello =20 arm,vexpress,position: description: When daughterboards are stacked on one site, their positi= on --=20 2.43.0 From nobody Thu Dec 18 20:20:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 04AC526E14E; Thu, 13 Feb 2025 18:03:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469813; cv=none; b=YY7VeF2UB5DIFk7EZrNFsFE0VLg05b4St/Tat3+6ylUGXKw/Sy4Pa5zdRwkX4vruh+LcfZT2qAyXMeukI8YOQhknVbUQtPudgE2ViHGwjWmifIeQ5u3Tk4iN4QQ2Llq3BMK6I+N1cyJPmyS21wqsyuWNk5qYXeOpwuj0Xe2qhNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469813; c=relaxed/simple; bh=vV0p1mhn8GKvnqTCnbhTpWW/fIw6GhJlSmcfWmuz1Zk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Yg9g7iNqIDsCLHhKk+BwMfidICdV3yg5GriPf+IUeDwxr7BO5BNxKF25FeYxvOO2KaIrJxcMCwOIy5mejU+5E5RA0NfRrWX6JOZwAiTuUBrtDlB9UzRacgM3j8u7QYRn3cLtQg6A9zxsouZMWsynKIkDYxTZM+GQGv6koz0eqCQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E89B9113E; Thu, 13 Feb 2025 10:03:51 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 524F53F5A1; Thu, 13 Feb 2025 10:03:29 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland Subject: [PATCH v5 3/8] dt-bindings: arm: Add Rainier compatibility Date: Thu, 13 Feb 2025 18:03:04 +0000 Message-ID: <20250213180309.485528-4-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250213180309.485528-1-vincenzo.frascino@arm.com> References: <20250213180309.485528-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Arm Morello System Development Platform uses Rainier CPUs. Add compatibility to Rainier. Signed-off-by: Vincenzo Frascino Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentatio= n/devicetree/bindings/arm/cpus.yaml index 73dd73d2d4fa..2e666b2a4dcd 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -177,6 +177,7 @@ properties: - arm,neoverse-v2 - arm,neoverse-v3 - arm,neoverse-v3ae + - arm,rainier - brcm,brahma-b15 - brcm,brahma-b53 - brcm,vulcan --=20 2.43.0 From nobody Thu Dec 18 20:20:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 54B4226E167; Thu, 13 Feb 2025 18:03:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469815; cv=none; b=DJkZnvEiLayYujiNmK4z+PUJlG4/chJ5TXc7+uJT1ozISdFzEDT/HLF0/7H+MY3AldyTjmjNcM4OIKcz9fczEWlKuiHFtYIi0e3+A7GFKFEdZ5/SW5+i7myDNmWHDaozI1iFUzeQ/wwhJgl4UTAW5239RT/3FhJ/xd3LgHA8lkc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469815; c=relaxed/simple; bh=nFLzdJMmng0/cPrvH9BD7ODJNvkZv6eLc+v3ZGguiYs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iwPC2XO8f5bl0ePMOfugS4CtrWyF2J1AVRO6URb7wdG/ahQu6eq+QCWWNf74EGq8LMemQrJffp6Q33TPgTV5RE2+xpv4NFd6iS2v74hlCoZHLMcnxkzULqAkZEXC7FmDFluwMviQVlMl3WUJesUudDnZmcOkIR16hkPp69GpoNg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3E51B26AC; Thu, 13 Feb 2025 10:03:54 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B3543F5A1; Thu, 13 Feb 2025 10:03:31 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland Subject: [PATCH v5 4/8] perf: arm_pmuv3: Add support for ARM Rainier PMU Date: Thu, 13 Feb 2025 18:03:05 +0000 Message-ID: <20250213180309.485528-5-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250213180309.485528-1-vincenzo.frascino@arm.com> References: <20250213180309.485528-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for the ARM Rainier CPU core PMU. Note: Coherently, add dt bindings for the same PMU. Signed-off-by: Vincenzo Frascino --- Documentation/devicetree/bindings/arm/pmu.yaml | 1 + drivers/perf/arm_pmuv3.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation= /devicetree/bindings/arm/pmu.yaml index a148ff54f2b8..295963a3cae7 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -67,6 +67,7 @@ properties: - arm,neoverse-v2-pmu - arm,neoverse-v3-pmu - arm,neoverse-v3ae-pmu + - arm,rainier-pmu - brcm,vulcan-pmu - cavium,thunder-pmu - nvidia,denver-pmu diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 0e360feb3432..3785522a08e7 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -1369,6 +1369,7 @@ PMUV3_INIT_SIMPLE(armv8_neoverse_v1) PMUV3_INIT_SIMPLE(armv8_neoverse_v2) PMUV3_INIT_SIMPLE(armv8_neoverse_v3) PMUV3_INIT_SIMPLE(armv8_neoverse_v3ae) +PMUV3_INIT_SIMPLE(armv8_rainier) =20 PMUV3_INIT_SIMPLE(armv8_nvidia_carmel) PMUV3_INIT_SIMPLE(armv8_nvidia_denver) @@ -1416,6 +1417,7 @@ static const struct of_device_id armv8_pmu_of_device_= ids[] =3D { {.compatible =3D "arm,neoverse-v2-pmu", .data =3D armv8_neoverse_v2_pmu_i= nit}, {.compatible =3D "arm,neoverse-v3-pmu", .data =3D armv8_neoverse_v3_pmu_i= nit}, {.compatible =3D "arm,neoverse-v3ae-pmu", .data =3D armv8_neoverse_v3ae_p= mu_init}, + {.compatible =3D "arm,rainier-pmu", .data =3D armv8_rainier_pmu_init}, {.compatible =3D "cavium,thunder-pmu", .data =3D armv8_cavium_thunder_pmu= _init}, {.compatible =3D "brcm,vulcan-pmu", .data =3D armv8_brcm_vulcan_pmu_init}, {.compatible =3D "nvidia,carmel-pmu", .data =3D armv8_nvidia_carmel_pmu_i= nit}, --=20 2.43.0 From nobody Thu Dec 18 20:20:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A529C26FA40; Thu, 13 Feb 2025 18:03:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469818; cv=none; b=jBg2kczbuVXIFfCszphbp1uFTzpWyz43M0T+LtRHyhzXQCz8jo0MCO9SCJrGLG7ZLE7Yn3bRNL/01h3tZtaoW/nPGe6BzjYBFmgr+rFiH/4uqkT4n2HOcrqVwh4ZzQmIOvtZLA6wb5IbJpnuktPYPd2qX+QQ9MMaZ+8So/fnxXo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469818; c=relaxed/simple; bh=wSGkRHix23Rg/RD0EtFj6NYDI+obYIqaysIit5V1FIw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gRVI6nPpLJ7myM/AJ79N/2TjnQQPTeK86v/z8AChz8pXYOPGcbaHUlNIU8aZp533UXnYQGP36APie4vXvOWnX3jloI/T3bG3faVWWR0LIMEpetCdbRv9UG2hqjYW4L1sFfSc8SBTTGsc1LivG63xJOckfU8TsUmKNlcI8vXSCFg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 86537113E; Thu, 13 Feb 2025 10:03:56 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E48D63F5A1; Thu, 13 Feb 2025 10:03:33 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland Subject: [PATCH v5 5/8] arm64: dts: morello: Add support for common functionalities Date: Thu, 13 Feb 2025 18:03:06 +0000 Message-ID: <20250213180309.485528-6-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250213180309.485528-1-vincenzo.frascino@arm.com> References: <20250213180309.485528-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. The Morello Platform (soc) and the Fixed Virtual Platfom (fvp) share some functionalities that have conveniently been included in morello.dtsi to avoid duplication. Introduce morello.dtsi. Note: Morello fvp will be introduced with a future patch series. Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/morello.dtsi | 323 +++++++++++++++++++++++++++ 1 file changed, 323 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello.dtsi diff --git a/arch/arm64/boot/dts/arm/morello.dtsi b/arch/arm64/boot/dts/arm= /morello.dtsi new file mode 100644 index 000000000000..e35e5e482720 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello.dtsi @@ -0,0 +1,323 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2020-2024, Arm Limited. All rights reserved. + */ + +#include + +/ { + interrupt-parent =3D <&gic>; + + #address-cells =3D <2>; + #size-cells =3D <2>; + + soc_refclk50mhz: clock-50000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <50000000>; + clock-output-names =3D "apb_pclk"; + }; + + soc_refclk85mhz: clock-85000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <85000000>; + clock-output-names =3D "iofpga:aclk"; + }; + + cpus { + #address-cells =3D <2>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x0>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_0>; + clocks =3D <&scmi_dvfs 0>; + + l2_0: l2-cache-0 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + + l3_0: l3-cache { + compatible =3D "cache"; + cache-level =3D <3>; + cache-size =3D <0x100000>; + cache-unified; + }; + }; + }; + + cpu1: cpu@100 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_1>; + clocks =3D <&scmi_dvfs 0>; + + l2_1: l2-cache-1 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu2: cpu@10000 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x10000>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_2>; + clocks =3D <&scmi_dvfs 1>; + + l2_2: l2-cache-2 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + + cpu3: cpu@10100 { + compatible =3D "arm,rainier"; + reg =3D <0x0 0x10100>; + device_type =3D "cpu"; + enable-method =3D "psci"; + /* 4 ways set associative */ + i-cache-size =3D <0x10000>; + i-cache-line-size =3D <64>; + i-cache-sets =3D <512>; + d-cache-size =3D <0x10000>; + d-cache-line-size =3D <64>; + d-cache-sets =3D <512>; + next-level-cache =3D <&l2_3>; + clocks =3D <&scmi_dvfs 1>; + + l2_3: l2-cache-3 { + compatible =3D "cache"; + cache-level =3D <2>; + /* 8 ways set associative */ + cache-size =3D <0x100000>; + cache-line-size =3D <64>; + cache-sets =3D <2048>; + cache-unified; + next-level-cache =3D <&l3_0>; + }; + }; + }; + + firmware { + interrupt-parent =3D <&gic>; + + scmi { + compatible =3D "arm,scmi"; + mbox-names =3D "tx", "rx"; + mboxes =3D <&mailbox 1 0>, <&mailbox 1 1>; + shmem =3D <&cpu_scp_hpri0>, <&cpu_scp_hpri1>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + scmi_dvfs: protocol@13 { + reg =3D <0x13>; + #clock-cells =3D <1>; + }; + + scmi_clk: protocol@14 { + reg =3D <0x14>; + #clock-cells =3D <1>; + }; + }; + }; + + /* The first bank of memory, memory map is actually provided by UEFI. */ + memory@80000000 { + device_type =3D "memory"; + /* [0x80000000-0xffffffff] */ + reg =3D <0x00000000 0x80000000 0x0 0x7f000000>; + }; + + memory@8080000000 { + device_type =3D "memory"; + /* [0x8080000000-0x83f7ffffff] */ + reg =3D <0x00000080 0x80000000 0x3 0x78000000>; + }; + + pmu { + compatible =3D "arm,rainier-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + secure-firmware@ff000000 { + reg =3D <0x0 0xff000000 0x0 0x01000000>; + no-map; + }; + }; + + spe-pmu { + compatible =3D "arm,statistical-profiling-extension-v1"; + interrupts =3D ; + }; + + soc: soc { + compatible =3D "simple-bus"; + #address-cells =3D <2>; + #size-cells =3D <2>; + interrupt-parent =3D <&gic>; + ranges; + + uart0: serial@2a400000 { + compatible =3D "arm,pl011", "arm,primecell"; + reg =3D <0x0 0x2a400000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&soc_refclk50mhz>, <&soc_refclk50mhz>; + clock-names =3D "uartclk", "apb_pclk"; + + status =3D "disabled"; + }; + + gic: interrupt-controller@2c010000 { + compatible =3D "arm,gic-v3"; + reg =3D <0x0 0x30000000 0x0 0x10000>, /* GICD */ + <0x0 0x300c0000 0x0 0x80000>; /* GICR */ + + interrupts =3D ; + + #interrupt-cells =3D <3>; + interrupt-controller; + + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + its1: msi-controller@30040000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30040000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its2: msi-controller@30060000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30060000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its_ccix: msi-controller@30080000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x30080000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + + its_pcie: msi-controller@300a0000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x0 0x300a0000 0x0 0x20000>; + + msi-controller; + #msi-cells =3D <1>; + }; + }; + + smmu_dp: iommu@2ce00000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x2ce00000 0x0 0x40000>; + + interrupts =3D , + , + ; + interrupt-names =3D "eventq", "gerror", "cmdq-sync"; + #iommu-cells =3D <1>; + }; + + mailbox: mhu@45000000 { + compatible =3D "arm,mhu-doorbell", "arm,primecell"; + reg =3D <0x0 0x45000000 0x0 0x1000>; + + interrupts =3D , + ; + #mbox-cells =3D <2>; + clocks =3D <&soc_refclk50mhz>; + clock-names =3D "apb_pclk"; + }; + + sram: sram@45200000 { + compatible =3D "mmio-sram"; + reg =3D <0x0 0x06000000 0x0 0x8000>; + ranges =3D <0 0x0 0x06000000 0x8000>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + cpu_scp_hpri0: scp-sram@0 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x0 0x80>; + }; + + cpu_scp_hpri1: scp-sram@80 { + compatible =3D "arm,scmi-shmem"; + reg =3D <0x80 0x80>; + }; + }; + }; + + timer { + compatible =3D "arm,armv8-timer"; + interrupts =3D , + , + , + ; + }; +}; --=20 2.43.0 From nobody Thu Dec 18 20:20:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CBF9126FA4B; Thu, 13 Feb 2025 18:03:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469820; cv=none; b=pTP0ZcOhSBZgvsOS5EcQgMXdltLHiRlDQLpgXOolvLJpyBS7nk9sP7J0hpmSO/mlXp4AyrKsfwpJMqKp9IGMuAWWmpmdlKiUnS/ROlQL1bCxaxrLhGJSGSSUxLl0hP9xR0ezWImVgtSxCgSRVHjnxEwbhG6w8o6Xq88uflxRBwg= ARC-Message-Signature: i=1; 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Thu, 13 Feb 2025 10:03:36 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland Subject: [PATCH v5 6/8] arm64: dts: morello: Add support for soc dts Date: Thu, 13 Feb 2025 18:03:07 +0000 Message-ID: <20250213180309.485528-7-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250213180309.485528-1-vincenzo.frascino@arm.com> References: <20250213180309.485528-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello SoC dts. Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/Makefile | 1 + arch/arm64/boot/dts/arm/morello-sdp.dts | 157 ++++++++++++++++++++++++ 2 files changed, 158 insertions(+) create mode 100644 arch/arm64/boot/dts/arm/morello-sdp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index d908e96d7ddc..869667bef7c0 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,3 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-sdp.dts b/arch/arm64/boot/dts/= arm/morello-sdp.dts new file mode 100644 index 000000000000..cee49dee7571 --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-sdp.dts @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model =3D "Arm Morello System Development Platform"; + compatible =3D "arm,morello-sdp", "arm,morello"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + dpu_aclk: clock-350000000 { + /* 77.1 MHz derived from 24 MHz reference clock */ + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <350000000>; + clock-output-names =3D "aclk"; + }; + + dpu_pixel_clk: clock-148500000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <148500000>; + clock-output-names =3D "pxclk"; + }; + + i2c0: i2c@1c0f0000 { + compatible =3D "cdns,i2c-r1p14"; + reg =3D <0x0 0x1c0f0000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&dpu_aclk>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + clock-frequency =3D <100000>; + + hdmi_tx: hdmi-transmitter@70 { + compatible =3D "nxp,tda998x"; + reg =3D <0x70>; + video-ports =3D <0x234501>; + port { + tda998x_0_input: endpoint { + remote-endpoint =3D <&dp_pl0_out0>; + }; + }; + }; + }; + + dp0: display@2cc00000 { + compatible =3D "arm,mali-d32", "arm,mali-d71"; + reg =3D <0x0 0x2cc00000 0x0 0x20000>; + interrupts =3D <0 69 4>; + clocks =3D <&dpu_aclk>; + clock-names =3D "aclk"; + iommus =3D <&smmu_dp 0>, <&smmu_dp 1>, <&smmu_dp 2>, <&smmu_dp 3>, + <&smmu_dp 8>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + pl0: pipeline@0 { + reg =3D <0>; + clocks =3D <&dpu_pixel_clk>; + clock-names =3D "pxclk"; + port { + dp_pl0_out0: endpoint { + remote-endpoint =3D <&tda998x_0_input>; + }; + }; + }; + }; + + smmu_ccix: iommu@4f000000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x4f000000 0x0 0x40000>; + + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent =3D <&its1 0>; + #iommu-cells =3D <1>; + dma-coherent; + }; + + smmu_pcie: iommu@4f400000 { + compatible =3D "arm,smmu-v3"; + reg =3D <0x0 0x4f400000 0x0 0x40000>; + + interrupts =3D , + , + , + ; + interrupt-names =3D "eventq", "gerror", "priq", "cmdq-sync"; + msi-parent =3D <&its2 0>; + #iommu-cells =3D <1>; + dma-coherent; + }; + + pcie_ctlr: pcie@28c0000000 { + device_type =3D "pci"; + compatible =3D "pci-host-ecam-generic"; + reg =3D <0x28 0xC0000000 0 0x10000000>; + ranges =3D <0x01000000 0x00 0x00000000 0x00 0x6f000000 0x00 0x00800000>, + <0x02000000 0x00 0x60000000 0x00 0x60000000 0x00 0x0f000000>, + <0x42000000 0x09 0x00000000 0x09 0x00000000 0x1f 0xc0000000>; + bus-range =3D <0 255>; + linux,pci-domain =3D <0>; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>; + msi-map =3D <0 &its_pcie 0 0x10000>; + iommu-map =3D <0 &smmu_pcie 0 0x10000>; + }; + + ccix_pcie_ctlr: pcie@4fc0000000 { + device_type =3D "pci"; + compatible =3D "pci-host-ecam-generic"; + reg =3D <0x4f 0xC0000000 0 0x10000000>; + ranges =3D <0x01000000 0x00 0x00000000 0x00 0x7f000000 0x00 0x00800000>, + <0x02000000 0x00 0x70000000 0x00 0x70000000 0x00 0x0f000000>, + <0x42000000 0x30 0x00000000 0x30 0x00000000 0x1f 0xc0000000>; + linux,pci-domain =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + dma-coherent; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>; + msi-map =3D <0 &its_ccix 0 0x10000>; + iommu-map =3D <0 &smmu_ccix 0 0x10000>; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.43.0 From nobody Thu Dec 18 20:20:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id DF34D26FA65; Thu, 13 Feb 2025 18:03:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 23B0A113E; Thu, 13 Feb 2025 10:04:01 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 824643F5A1; Thu, 13 Feb 2025 10:03:38 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland Subject: [PATCH v5 7/8] arm64: dts: morello: Add support for fvp dts Date: Thu, 13 Feb 2025 18:03:08 +0000 Message-ID: <20250213180309.485528-8-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250213180309.485528-1-vincenzo.frascino@arm.com> References: <20250213180309.485528-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Morello architecture is an experimental extension to Armv8.2-A, which extends the AArch64 state with the principles proposed in version 7 of the Capability Hardware Enhanced RISC Instructions (CHERI) ISA. Introduce Morello fvp dts. Signed-off-by: Vincenzo Frascino --- arch/arm64/boot/dts/arm/Makefile | 2 +- arch/arm64/boot/dts/arm/morello-fvp.dts | 78 +++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/arm/morello-fvp.dts diff --git a/arch/arm64/boot/dts/arm/Makefile b/arch/arm64/boot/dts/arm/Mak= efile index 869667bef7c0..f30ee045dc95 100644 --- a/arch/arm64/boot/dts/arm/Makefile +++ b/arch/arm64/boot/dts/arm/Makefile @@ -7,4 +7,4 @@ dtb-$(CONFIG_ARCH_VEXPRESS) +=3D rtsm_ve-aemv8a.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D vexpress-v2f-1xv7-ca53x2.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D fvp-base-revc.dtb dtb-$(CONFIG_ARCH_VEXPRESS) +=3D corstone1000-fvp.dtb corstone1000-mps3.dtb -dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb +dtb-$(CONFIG_ARCH_VEXPRESS) +=3D morello-sdp.dtb morello-fvp.dtb diff --git a/arch/arm64/boot/dts/arm/morello-fvp.dts b/arch/arm64/boot/dts/= arm/morello-fvp.dts new file mode 100644 index 000000000000..c8d38bebd1ec --- /dev/null +++ b/arch/arm64/boot/dts/arm/morello-fvp.dts @@ -0,0 +1,78 @@ + +// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) +/* + * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + */ + +/dts-v1/; +#include "morello.dtsi" + +/ { + model =3D "Arm Morello Fixed Virtual Platform"; + compatible =3D "arm,morello-fvp", "arm,morello"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + bp_refclock24mhz: clock-24000000 { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <24000000>; + clock-output-names =3D "bp:clock24mhz"; + }; + + block_0: virtio_block@1c170000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c170000 0x0 0x200>; + interrupts =3D ; + }; + + net_0: virtio_net@1c180000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c180000 0x0 0x200>; + interrupts =3D ; + }; + + rng_0: virtio_rng@1c190000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c190000 0x0 0x200>; + interrupts =3D ; + }; + + p9_0: virtio_p9@1c1a0000 { + compatible =3D "virtio,mmio"; + reg =3D <0x0 0x1c1a0000 0x0 0x200>; + interrupts =3D ; + }; + + kmi_0: kmi@1c150000 { + compatible =3D "arm,pl050", "arm,primecell"; + reg =3D <0x0 0x1c150000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names =3D "KMIREFCLK", "apb_pclk"; + }; + + kmi_1: kmi@1c160000 { + compatible =3D "arm,pl050", "arm,primecell"; + reg =3D <0x0 0x1c160000 0x0 0x1000>; + interrupts =3D ; + clocks =3D <&bp_refclock24mhz>, <&bp_refclock24mhz>; + clock-names =3D "KMIREFCLK", "apb_pclk"; + }; + + eth_0: ethernet@1d100000 { + compatible =3D "smsc,lan91c111"; + reg =3D <0x0 0x1d100000 0x0 0x10000>; + interrupts =3D ; + }; +}; + +&uart0 { + status =3D "okay"; +}; --=20 2.43.0 From nobody Thu Dec 18 20:20:43 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 91FFD270EAB; Thu, 13 Feb 2025 18:03:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469825; cv=none; b=UcuemRZvK53uRz88nVw99lNc0LDG61nI12z5wOwMnH1sG3Dv4ZcF25uvWeeHcSdcvchphH6Ba6nTdJGMbinGQMRuy2YHLnvc3vBCLh7X4ExmL+y6Ud+fjnoKyI/EwG2M0sCsIfk1dp1YcwlFdq7KOEJATk49Fw0IWxkhVX0AzV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739469825; c=relaxed/simple; bh=HJwDEao0RAvUu8WKq0YYlRxI1wgjKwLyaZ7pIUNX4ao=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Etuh/TqmV0/3mGDcLZXTQuY5TVhDQ90lnRT4T0zXNYQB7uVS8+Nwo0txe1Bbhv3UOvP1PbtQaLRkpWGl+6Uourl/G/wjtf2dkDWnpHQv557zAVBhKrMBpIJ4xbIhzanctZKmGotUGJm+Lv8hHzXCppkNZIMD1zXy0SY8XMsN/PA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8BB12113E; Thu, 13 Feb 2025 10:04:03 -0800 (PST) Received: from e119884-lin.cambridge.arm.com (e119884-lin.cambridge.arm.com [10.1.196.72]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CB3DA3F5A1; Thu, 13 Feb 2025 10:03:40 -0800 (PST) From: Vincenzo Frascino To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Vincenzo Frascino , Linus Walleij , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Liviu Dudau , Sudeep Holla , Lorenzo Pieralisi , Russell King , Will Deacon , Mark Rutland , Krzysztof Kozlowski Subject: [PATCH v5 8/8] MAINTAINERS: Add Vincenzo Frascino as Arm Morello Maintainer Date: Thu, 13 Feb 2025 18:03:09 +0000 Message-ID: <20250213180309.485528-9-vincenzo.frascino@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250213180309.485528-1-vincenzo.frascino@arm.com> References: <20250213180309.485528-1-vincenzo.frascino@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add Vincenzo Frascino as Arm Morello Software Development Platform Maintainer. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Vincenzo Frascino --- MAINTAINERS | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 873aa2cce4d7..9161de8e7447 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2751,6 +2751,12 @@ F: arch/arm/boot/dts/socionext/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut =20 +ARM/MORELLO PLATFORM +M: Vincenzo Frascino +L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) +S: Maintained +F: arch/arm64/boot/dts/arm/morello* + ARM/MOXA ART SOC M: Krzysztof Kozlowski L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) --=20 2.43.0