From nobody Thu Dec 18 20:02:17 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D858C1FF5F7; Thu, 13 Feb 2025 14:59:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739458788; cv=none; b=C/AinTZrdePO7C5g+P36eftVZyZRF8d702mbGwAXgoOwCg31Zd50W8iO2Dyc3x3xBKIsYDleOOIrexUaCoXUtyNxbL/tzeIWFAGhPd/UyWnnQckC+3d1PwpBqWebQPAFU4trqL6n30BsjGwRyWABRk/jci0NRrIyidaFTBDIpOk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739458788; c=relaxed/simple; bh=Mh/H6vQ6A1hrURy8whbQOLd0UQiv3ywbjr/FbGu1Dl8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nvU3Y8ObCZ1Gf7TTX/ykKGWBFPlc4fevq0EKcAwGsdAOwtqkvgzjfHsDRVB5ZYIBTf3FFegr9T9gzVECfRPT0cyVddx8dYb36c/8JxVTCaSAAb5tX8a7H534IkT9p+9ICJnIN0iPW3Zr2JTqgsxTubgZpHWfnNeMjXBKdUe5GUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=lOE83DM1; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="lOE83DM1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739458785; bh=Mh/H6vQ6A1hrURy8whbQOLd0UQiv3ywbjr/FbGu1Dl8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lOE83DM1Rcs8YdJsFqk4qL57kFELrRb9e5OCj354qcjnKANYO9f194cfqHPZxHPQB TeKRkANuFRgWu30YOxGwRHYq1XznwOFnyPQKegml7a2OtsXNFK2pUS7DQpb+6XSblc cJDcYVy+g+CJjU4o4foTxm0F7q20FmoG+hAMnbJVsf20uNT2ULcyCXqx6oIKkVWxm/ +bOMeNPbK0b/Uhmh6e7YLniM7ZN6rO3feGFiFXGJkHYVrFxjP6PhvRW44M3B0GOZZV zpR1j7DpNemDDN8Dft1s6UPy41mGay6allNkE6mTTUYkuZzAGp7FksoeL10omi7RDj abdo9KV7wzqNg== Received: from trenzalore.hitronhub.home (unknown [23.233.251.139]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5428F17E0860; Thu, 13 Feb 2025 15:59:42 +0100 (CET) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Dragan Simic , Jonas Karlman , Chris Morgan , Kever Yang , Tim Lunn , FUKAUMI Naoki , Michael Riesch , Detlev Casanova , Weizhao Ouyang , Elon Zhang , Alexey Charkov , Stephen Chen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 1/2] dt-bindings: arm: rockchip: Add Radxa ROCK 4D board Date: Thu, 13 Feb 2025 09:57:15 -0500 Message-ID: <20250213145921.133412-2-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250213145921.133412-1-detlev.casanova@collabora.com> References: <20250213145921.133412-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The board is based on the Rockchip rk3576 SoC. Signed-off-by: Detlev Casanova Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Document= ation/devicetree/bindings/arm/rockchip.yaml index 522a6f0450eae..9ddb20890627f 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -862,6 +862,11 @@ properties: - const: radxa,rock-4c-plus - const: rockchip,rk3399 =20 + - description: Radxa ROCK 4D + items: + - const: radxa,rock-4d + - const: rockchip,rk3576 + - description: Radxa ROCK 4SE items: - const: radxa,rock-4se --=20 2.48.1 From nobody Thu Dec 18 20:02:17 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DBD1D201025; Thu, 13 Feb 2025 14:59:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739458792; cv=none; b=oOAqs+0aJ+Fjw+fW79Z8hLS3Fuxor2VCi6zZThuEvl/fAyrruGfyh04JM5TM8Q63QCx5cbK0QOTm0I83uyU1r9H1zifzR+NeHA4QT1DQwqCkpijwsGRKyZGVactnIjPpsBIgqqkxuFt14OrDzx6l9feGu7RQIgmFPzHYBvSYo/4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739458792; c=relaxed/simple; bh=7czLAGYHApKjd/6EXMOX9zWOBBjQfbkIyn1sSCTIrnE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=i6Ee0pNnjm7Fwz9kzrUN1gjHVSzyErM/fbLpXmhskkt0qTwXlZDAvFnshf35gk7SsgyKbu0hEtzK8Ee2YAksXqO1fYosOacylaI/ndlFLxjXMnPrGcNs9z5VKQ0opHrZS/x1eBJGWFctj5dqXuHIxuBHMrJCGzeMuAVizGn4w4o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=eQHqSQBp; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="eQHqSQBp" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739458788; bh=7czLAGYHApKjd/6EXMOX9zWOBBjQfbkIyn1sSCTIrnE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=eQHqSQBp31CHpF7VtOXDZoxRDxfhduw4p1W36xkcW224Qy+fLNrGtIutLml0n9Qb2 In4yapT6BJSPAt7sJ7kb8PVzqw7RPCqWT1giiILf225DJDRFpndBrd+2dQ2fXrgTk5 gbuMVaSps1rA+DYQv2LyZTIVVG34qmWIcGk+FbbuI6RELZ8ucdMQ9sHIuFatuOHMOm 1dLKuaGlnExI9FcPieplb5NMNGmxhYd0qX8WNI/T01ECC9rycaJns792FHI7z7pp1W NggAX9Uz5vgxgstKU2n2PmoZpoW2hFrs5EwH/7YFPp2yNrD+IAPC13iumhPEO03erC 7SEgf5oIke/aw== Received: from trenzalore.hitronhub.home (unknown [23.233.251.139]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: detlev) by bali.collaboradmins.com (Postfix) with ESMTPSA id 7992717E1540; Thu, 13 Feb 2025 15:59:45 +0100 (CET) From: Detlev Casanova To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Dragan Simic , Jonas Karlman , Chris Morgan , Kever Yang , Tim Lunn , FUKAUMI Naoki , Michael Riesch , Detlev Casanova , Weizhao Ouyang , Elon Zhang , Alexey Charkov , Stephen Chen , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, kernel@collabora.com Subject: [PATCH v2 2/2] arm64: dts: rockchip: Add Radxa ROCK 4D device tree Date: Thu, 13 Feb 2025 09:57:16 -0500 Message-ID: <20250213145921.133412-3-detlev.casanova@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250213145921.133412-1-detlev.casanova@collabora.com> References: <20250213145921.133412-1-detlev.casanova@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stephen Chen The Radxa ROCK 4D board is based on the Rockchip rk3576 SoC. The device tree adds support for basic devices: - UART - SD Card - Ethernet - USB - RTC It has 4 USB ports but only 3 are usable as the top left one is used for maskrom. It has a USB-C port that is only used for powering the board. Signed-off-by: Stephen Chen Signed-off-by: Detlev Casanova --- arch/arm64/boot/dts/rockchip/Makefile | 1 + .../boot/dts/rockchip/rk3576-rock-4d.dts | 651 ++++++++++++++++++ 2 files changed, 652 insertions(+) create mode 100644 arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index def1222c1907e..a112aeb37948a 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-= display-vz.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-io-expander.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-armsom-sige5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-evb1-v10.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3576-rock-4d.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3582-radxa-e52c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-armsom-sige7.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-armsom-w3.dtb diff --git a/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts b/arch/arm64/b= oot/dts/rockchip/rk3576-rock-4d.dts new file mode 100644 index 0000000000000..f356742f9d643 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3576-rock-4d.dts @@ -0,0 +1,651 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2024 Radxa Computer (Shenzhen) Co., Ltd. + * + */ + +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include "rk3576.dtsi" + +/ { + model =3D "Radxa ROCK 4D"; + compatible =3D "radxa,rock-4d", "rockchip,rk3576"; + + aliases { + ethernet0 =3D &gmac0; + }; + + chosen { + stdout-path =3D "serial0:1500000n8"; + }; + + leds: leds { + compatible =3D "gpio-leds"; + + power-led { + color =3D ; + function =3D LED_FUNCTION_STATUS; + gpios =3D <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; + linux,default-trigger =3D "default-on"; + }; + + user-led { + color =3D ; + function =3D LED_FUNCTION_HEARTBEAT; + gpios =3D <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>; + linux,default-trigger =3D "heartbeat"; + }; + }; + + vcc_12v0_dcin: regulator-vcc-12v0-dcin { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_12v0_dcin"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + }; + + vcc_5v0_sys: regulator-vcc-5v0-sys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc_12v0_dcin>; + }; + + vcc_5v0_device: regulator-vcc-5v0-device { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_5v0_device"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <&vcc_12v0_dcin>; + }; + + vcc_2v0_pldo_s3: regulator-vcc-2v0-pldo-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_2v0_pldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <2000000>; + regulator-max-microvolt =3D <2000000>; + vin-supply =3D <&vcc_5v0_sys>; + }; + + vcc_1v1_nldo_s3: regulator-vcc-1v1-nldo-s3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v1_nldo_s3"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + vin-supply =3D <&vcc_5v0_sys>; + }; + + vcc_3v3_rtc_s5: regulator-vcc-3v3-rtc-s5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_rtc_s5"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_5v0_sys>; + }; + + vcc_1v8_s0: regulator-vcc-1v8-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v8_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_1v8_s3>; + }; + + vcc_3v3_s0: regulator-vcc-3v3-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_3v3_s3>; + }; + + vcc_3v3_ufs_s0: regulator-vcc-ufs-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_ufs_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <&vcc_5v0_sys>; + }; + + vcc_1v8_ufs_vccq2_s0: regulator-vcc1v8-ufs-vccq2-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v8_ufs_vccq2_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + vin-supply =3D <&vcc_1v8_s3>; + }; + + vcc_1v2_ufs_vccq_s0: regulator-vcc-1v2-ufs-vccq-s0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_1v2_ufs_vccq_s0"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <&vcc_5v0_sys>; + }; + + vcc_3v3_pcie: regulator-vcc-3v3-pcie { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc_3v3_pcie"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + gpio =3D <&gpio2 RK_PD3 GPIO_ACTIVE_HIGH>; + startup-delay-us =3D <5000>; + vin-supply =3D <&vcc_5v0_sys>; + }; + + vcc_5v0_host: regulator-vcc-5v0-host { + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc5v0_host"; + regulator-boot-on; + regulator-always-on; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + gpio =3D <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>; + vin-supply =3D <&vcc_5v0_device>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&usb_host_pwren>; + }; +}; + +&cpu_l0 { + cpu-supply =3D <&vdd_cpu_lit_s0>; +}; + +&gmac0 { + phy-mode =3D "rgmii-id"; + clock_in_out =3D "output"; + + snps,reset-gpio =3D <&gpio2 RK_PB5 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 20000 100000>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <ð0m0_miim + ð0m0_tx_bus2 + ð0m0_rx_bus2 + ð0m0_rgmii_clk + ð0m0_rgmii_bus + ðm0_clk0_25m_out>; + + phy-handle =3D <&rgmii_phy0>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&vdd_gpu_s0>; + status =3D "okay"; +}; + +&i2c1 { + status =3D "okay"; + + pmic@23 { + compatible =3D "rockchip,rk806"; + reg =3D <0x23>; + + interrupt-parent =3D <&gpio0>; + interrupts =3D <6 IRQ_TYPE_LEVEL_LOW>; + + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pmic_pins + &rk806_dvs1_null + &rk806_dvs2_null + &rk806_dvs3_null>; + + system-power-controller; + + vcc1-supply =3D <&vcc_5v0_sys>; + vcc2-supply =3D <&vcc_5v0_sys>; + vcc3-supply =3D <&vcc_5v0_sys>; + vcc4-supply =3D <&vcc_5v0_sys>; + vcc5-supply =3D <&vcc_5v0_sys>; + vcc6-supply =3D <&vcc_5v0_sys>; + vcc7-supply =3D <&vcc_5v0_sys>; + vcc8-supply =3D <&vcc_5v0_sys>; + vcc9-supply =3D <&vcc_5v0_sys>; + vcc10-supply =3D <&vcc_5v0_sys>; + vcc11-supply =3D <&vcc_2v0_pldo_s3>; + vcc12-supply =3D <&vcc_5v0_sys>; + vcc13-supply =3D <&vcc_1v1_nldo_s3>; + vcc14-supply =3D <&vcc_1v1_nldo_s3>; + vcca-supply =3D <&vcc_5v0_sys>; + + gpio-controller; + #gpio-cells =3D <2>; + + rk806_dvs1_null: dvs1-null-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun0"; + }; + + rk806_dvs2_null: dvs2-null-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun0"; + }; + + rk806_dvs3_null: dvs3-null-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun0"; + }; + + rk806_dvs1_slp: dvs1-slp-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun1"; + }; + + rk806_dvs1_pwrdn: dvs1-pwrdn-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun2"; + }; + + rk806_dvs1_rst: dvs1-rst-pins { + pins =3D "gpio_pwrctrl1"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_slp: dvs2-slp-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun1"; + }; + + rk806_dvs2_pwrdn: dvs2-pwrdn-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun2"; + }; + + rk806_dvs2_rst: dvs2-rst-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun3"; + }; + + rk806_dvs2_dvs: dvs2-dvs-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun4"; + }; + + rk806_dvs2_gpio: dvs2-gpio-pins { + pins =3D "gpio_pwrctrl2"; + function =3D "pin_fun5"; + }; + + rk806_dvs3_slp: dvs3-slp-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun1"; + }; + + rk806_dvs3_pwrdn: dvs3-pwrdn-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun2"; + }; + + rk806_dvs3_rst: dvs3-rst-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun3"; + }; + + rk806_dvs3_dvs: dvs3-dvs-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun4"; + }; + + rk806_dvs3_gpio: dvs3-gpio-pins { + pins =3D "gpio_pwrctrl3"; + function =3D "pin_fun5"; + }; + + regulators { + vdd_cpu_big_s0: dcdc-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_big_s0"; + regulator-enable-ramp-delay =3D <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_npu_s0: dcdc-reg2 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_npu_s0"; + regulator-enable-ramp-delay =3D <400>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_cpu_lit_s0: dcdc-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <950000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_cpu_lit_s0"; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vcc_3v3_s3: dcdc-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc_3v3_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <3300000>; + }; + }; + + vdd_gpu_s0: dcdc-reg5 { + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <900000>; + regulator-ramp-delay =3D <12500>; + regulator-name =3D "vdd_gpu_s0"; + regulator-enable-ramp-delay =3D <400>; + regulator-state-mem { + regulator-off-in-suspend; + regulator-suspend-microvolt =3D <850000>; + }; + }; + + vddq_ddr_s0: dcdc-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vddq_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_logic_s0: dcdc-reg7 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <800000>; + regulator-name =3D "vdd_logic_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_1v8_s3: dcdc-reg8 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc_1v8_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd2_ddr_s3: dcdc-reg9 { + regulator-always-on; + regulator-boot-on; + regulator-name =3D "vdd2_ddr_s3"; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vdd_ddr_s0: dcdc-reg10 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "vdd_ddr_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_1v8_s0: pldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca_1v8_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo2_s0: pldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pldo2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_1v2_s0: pldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-name =3D "vdda_1v2_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca_3v3_s0: pldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcca_3v3_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd_s0: pldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vccio_sd_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcca1v8_pldo6_s3: pldo-reg6 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcca1v8_pldo6_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <1800000>; + }; + }; + + vdd_0v75_s3: nldo-reg1 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdd_0v75_s3"; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt =3D <750000>; + }; + }; + + vdda_ddr_pll_s0: nldo-reg2 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdda_ddr_pll_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda0v75_hdmi_s0: nldo-reg3 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <837500>; + regulator-max-microvolt =3D <837500>; + regulator-name =3D "vdda0v75_hdmi_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v85_s0: nldo-reg4 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <850000>; + regulator-max-microvolt =3D <850000>; + regulator-name =3D "vdda_0v85_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdda_0v75_s0: nldo-reg5 { + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <750000>; + regulator-name =3D "vdda_0v75_s0"; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c2 { + status =3D "okay"; + + hym8563: rtc@51 { + compatible =3D "haoyu,hym8563"; + reg =3D <0x51>; + clock-output-names =3D "hym8563"; + interrupt-parent =3D <&gpio0>; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hym8563_int>; + wakeup-source; + #clock-cells =3D <0>; + }; +}; + +&mdio0 { + rgmii_phy0: phy@1 { + compatible =3D "ethernet-phy-ieee802.3-c22"; + reg =3D <0x1>; + clocks =3D <&cru REFCLKO25M_GMAC0_OUT>; + }; +}; + +&pinctrl { + hym8563 { + hym8563_int: hym8563-int { + rockchip,pins =3D <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + leds { + led_rgb_r: led-red-en { + rockchip,pins =3D <4 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + led_rgb_g: led-green-en { + rockchip,pins =3D <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb { + usb_host_pwren: usb-host-pwren { + rockchip,pins =3D <4 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width =3D <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency =3D <200000000>; + no-sdio; + no-mmc; + sd-uhs-sdr104; + vmmc-supply =3D <&vcc_3v3_s3>; + vqmmc-supply =3D <&vccio_sd_s0>; + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0m0_xfer>; + status =3D "okay"; +}; + +&combphy1_psu { + status =3D "okay"; +}; + +&u2phy0 { + status =3D "okay"; +}; + +&u2phy1 { + status =3D "okay"; +}; + +&usb_drd1_dwc3 { + dr_mode =3D "host"; + status =3D "okay"; +}; --=20 2.48.1