From nobody Fri Dec 19 02:50:44 2025 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C04D220DD5B; Thu, 13 Feb 2025 09:40:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739439660; cv=none; b=P2qhe2YatEV7IBIjgabfJSlLF0R5f60ovgfcj+tUwaY+s0KR7ViCiFdqoUvvFvgYTuUfpVXRVZKfvciAVt/xraiOXvY7fpfexrH2+imgtIih24fcUt6iQ/sCERnscxeZtXB+XA9zQJ7cQcEQ3OXP/CIBR6nN06Yj7YgpkoqYyGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739439660; c=relaxed/simple; bh=122zqtZiKS3kEtcfZ9feBjNttG8g45OLOdftdwpMMeA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Cpnz4Eb4uIJV4gIhRBQtqbFa6cdVTv1l4lx3YmU4S+1U4deToVCU2tL2io0JDwK2cSQN619Bw/fqfsj8yVvvXzw9ACy+RWiVtOSZwnfhZwZrOdI8cpkzx+zvlGUJgaR5Eo4H6wbxTdB8oOn/WwMPBRXG++sx2zF2o4F4m4M0ZJM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=c4mbrRrJ; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="c4mbrRrJ" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-54504a6955aso480310e87.2; Thu, 13 Feb 2025 01:40:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1739439656; x=1740044456; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vXrXivtvEQLh4adLUP4GGOdvzjuOxYfBxi9mEWJalRs=; b=c4mbrRrJGHhFx19pHBMSmNDkd/GxZwGjqMbbJLfpGDymwdIIvFSkUxauPMr2aeYkUy 5pIQm1Ubo5j85tYPS9XOy15xMqlLjxEVVUVqM8kA4sWT7Zo7LUhyuCErdkghoc0MbNwg 7bZi5PiJ+mnVi5h60K5KLzFuIPTOKnyvdn2zP4Rbymp7oQbzw9lDV8o1TysvscznKLS2 A+Lqxx0r4fDqMqhWIxV1xylIJc4wBXTQg55oQ9MK0Cc0ZeApPx9xiYHNqbJYq4bSe8Rz NCyVBuhs9wHMSQwEtVTA1DAuXgk1QUm4FSxEyaKfAuOr/VdNfPRaDrsisnHB+5hsEirN pqvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739439656; x=1740044456; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vXrXivtvEQLh4adLUP4GGOdvzjuOxYfBxi9mEWJalRs=; b=VB0rf+fM1dIFQZ72tLPhqifHbx1ri40t/SgUQ5yd01X9SKKYjktE2+fHgsSIWYzBF7 51LIL5rFRAD3ZicUHxYSFLYGuOqQj8DSwjEHL88gFDDsEhLeQU3L53W1S3g7Mcufgu/d FIuKljwaEbhz8lvhFkglYi21JnFRZgMVWsHTKJCRV3/G9Jhhe6CaIGLnpTJn6jv0JLL/ SYuXitoaN1hLY27BsAGV56euuY0/4uMnJmJrYqcEEyNqhOU6mT+F26tNojuwEIwXytMw oN7H8vxFeHf0yMXChCmokwZ48rmEP5h0TPdPJGYojpyQV9RHOjiuOPmx5Zv+WXToI2FQ 4daQ== X-Forwarded-Encrypted: i=1; AJvYcCVoSgMVghIus1YnQcSzAR7YIRWIdYfy/eyHsVc6WHWT8eCFbFAPwCbiu8fD+Z9ipDsvSofCLTT+DkF2@vger.kernel.org, AJvYcCXTmSAx7U10l5u77rP3md2OPtQm+D9z7I3r30JkSV4FSK14SApws5g9THA/iAHtCsUErDfYkUPgEw/i@vger.kernel.org X-Gm-Message-State: AOJu0YxjD97+ej1nvbCkFBNhzuDqSXNh2Y2sqMuHDULR/q7iWcjzOMoF vD4v5eQ7KWlHKpA/51+MNfqcL4chtuV/cdgVl5b+i0LU/SHP2cAnl9TEgM9mhFhb X-Gm-Gg: ASbGnctV3pgzP41hU/r9WuJ0MuWkJRTXVSAqP/ii+WEsvSiznG3J5KNkJu+77xxY/ep A/rQobF6I7UKWs18Mvpmr8lw7vuf/lDcdeu0nzXSjf+io164S7fvZdOxKiw3wjVntLl4D3U2o7l s/EOhjwI6paiNdlsf0DLDQBICaRYs9H9aE8AZWoj2XpFi+cieQN28wFZ17rkNRglaXRZ86Y51jK 11ea7CUGYZZiZ7TjYFV1+JB5bo4n0sPYZ6ZUuLveCpnKZWvcgDMfPdpPVKBp6N02YwNclysb2VR ScwAwgsWLIS2CbDo8XT07ApwrSl4UqI= X-Google-Smtp-Source: AGHT+IFCCGYbVQL84jr1QCXcHIWbGfBA/gZiSDbm59JZik6/Tl6V0NyLBbgRGNNv01sE2JUH4IgWTw== X-Received: by 2002:a05:6512:1111:b0:545:6cf:6f3e with SMTP id 2adb3069b0e04-5451dde81aemr834931e87.49.1739439656372; Thu, 13 Feb 2025 01:40:56 -0800 (PST) Received: from localhost.localdomain ([178.176.176.188]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5451f10cae7sm119518e87.183.2025.02.13.01.40.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 01:40:55 -0800 (PST) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Conor Dooley , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cheo Fusi , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v11 1/3] dt-bindings: pwm: Add binding for Allwinner D1/T113-S3/R329 PWM controller Date: Thu, 13 Feb 2025 12:40:12 +0300 Message-Id: <20250213094018.134081-2-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250213094018.134081-1-privatesub2@gmail.com> References: <20250213094018.134081-1-privatesub2@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allwinner's D1, T113-S3 and R329 SoCs have a new pwm controller witch is different from the previous pwm-sun4i. The D1 and T113 are identical in terms of peripherals, they differ only in the architecture of the CPU core, and even share the majority of their DT. Because of that, using the same compatible makes sense. The R329 is a different SoC though, and should have a different compatible string added, especially as there is a difference in the number of channels. D1 and T113s SoCs have one PWM controller with 8 channels. R329 SoC has two PWM controllers in both power domains, one of them has 9 channels (CPUX one) and the other has 6 (CPUS one). Add a device tree binding for them. Signed-off-by: Aleksandr Shubin Reviewed-by: Conor Dooley --- .../bindings/pwm/allwinner,sun20i-pwm.yaml | 84 +++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/allwinner,sun20i-= pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yam= l b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml new file mode 100644 index 000000000000..8955e203f638 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun20i-pwm.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/allwinner,sun20i-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner D1, T113-S3 and R329 PWM + +maintainers: + - Aleksandr Shubin + - Brandon Cheo Fusi + +properties: + compatible: + oneOf: + - const: allwinner,sun20i-d1-pwm + - items: + - const: allwinner,sun50i-r329-pwm + - const: allwinner,sun20i-d1-pwm + + reg: + maxItems: 1 + + "#pwm-cells": + const: 3 + + clocks: + items: + - description: Bus clock + - description: 24 MHz oscillator + - description: APB clock + + clock-names: + items: + - const: bus + - const: hosc + - const: apb + + resets: + maxItems: 1 + + allwinner,npwms: + $ref: /schemas/types.yaml#/definitions/uint32 + description: The number of PWM channels configured for this instance + enum: [6, 9] + +allOf: + - $ref: pwm.yaml# + + - if: + properties: + compatible: + contains: + const: allwinner,sun50i-r329-pwm + + then: + required: + - allwinner,npwms + +unevaluatedProperties: false + +required: + - compatible + - reg + - "#pwm-cells" + - clocks + - clock-names + - resets + +examples: + - | + #include + #include + + pwm: pwm@2000c00 { + compatible =3D "allwinner,sun20i-d1-pwm"; + reg =3D <0x02000c00 0x400>; + clocks =3D <&ccu CLK_BUS_PWM>, <&dcxo>, <&ccu CLK_APB0>; + clock-names =3D "bus", "hosc", "apb"; + resets =3D <&ccu RST_BUS_PWM>; + #pwm-cells =3D <0x3>; + }; + +... --=20 2.25.1 From nobody Fri Dec 19 02:50:44 2025 Received: from mail-lf1-f41.google.com (mail-lf1-f41.google.com [209.85.167.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 133EB20DD72; Thu, 13 Feb 2025 09:41:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739439669; cv=none; b=AWHFYGmYcuZf/1YtMgRN5FD33Byj4dtzHLWjWrPQYgL5YJvYHzTJKSeXnANKt7NvXwGotEnD9RUiCjAeVPGF4wBWOESsX1E5bgjZy4UcrGM9GfMfp4UaENoPhvp/QddCp6uu+JDbRJ1hOYimPJll6Xn0/Gwz2ym0/PG5uo2SXvo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739439669; c=relaxed/simple; bh=poSdOQLJ0aa+ypG4bhoxUZ6eDX7/QqkKUD+mmfU8Dto=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=ODG6tG4mYejD/xe8OiWdBkG3DpzCXv3fNZ0s+WuHlIRXdBPE71N4rX9e2WYHkCFh27irvOzR9748AexG6V8u0gUD7Zfzhp0ycUBNVKAKfOezNwAazilcE/T9UxsTmIQXjTPep3zdl7in6vJ6FLIWwITYf6NvQLBi1aBTHolt/pI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NSNjgpv9; arc=none smtp.client-ip=209.85.167.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NSNjgpv9" Received: by mail-lf1-f41.google.com with SMTP id 2adb3069b0e04-5450408455dso679850e87.0; Thu, 13 Feb 2025 01:41:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1739439665; x=1740044465; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9NmeS9foi57N6w4no4pH/e8F+/9zjxmhS+0FDke+vdk=; b=NSNjgpv96KHRWwMJm86WeQCqxmbi9Duz8d7CNB8jZhPDrv0CddlEV4rigx0hN6FQEl L4DI7GH9RoCXQ8RjRBb/ban2rQY/znywl5uWNMqN3i65myL63ZGSk+8mPXDG6DArIlDK xOgS/0Z3If52pOC5cWaUvlydHia6QBoISgYiv6v0JqpUXFm70nSDU0Q8bi1E91ylXiBT FK5W7zHYI2/Ms6SHT2LOOi4n3azcUDLNeQ429o3h8oSnHVof2Tu3TpnvjXQ5hecJBoBV u03Yvw+6JZjfaxQ7j/0uYEat2DhQ/KlXv7oUuIMQcp+IRSW3C8ytNfXFGdHo5VHGJ9/s 92zw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739439665; x=1740044465; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9NmeS9foi57N6w4no4pH/e8F+/9zjxmhS+0FDke+vdk=; b=KpvrfBpRGIrjBVQVT2hQcI953+BbOyZEMLPpeBFynFbqW/R8NoDTozgJzhKIxPjxlb EQ/g7N60d0M2/7Luh4DjwPNpaJVhsMTWaQ8uSDOAyyoUurGM/scqlzNGOrfw3QeYkoiS eUEBCLuNc7Z6Yb17IdO7veOXblVgvMhCp7tu2bV3TLAm5SrwYIZvwsBz7qXusB2NWSFO eUg8C6P3ucvoroPqWoi/S3A2aV6hcrAQIKtFZ8oZGe/T6u7n4E4qz0puGN9uQDRKXvRc b1lr4NWe2Ewt0T/gGKT5kxzauSRnh61MzM0OBlqmOrqay5IqNhbMIB+4AKfH0aMklCCy kAeA== X-Forwarded-Encrypted: i=1; AJvYcCUjh5aYAz35pbVoSDsTZwBGS/U1C4a39DX8lLwFoaafIDPMMVhjqlCyzP8YHwa5pP6wHM+owI9OPzEI@vger.kernel.org, AJvYcCVFQJPCMSXK6fM9WnKUUTsRh9zK174Pg9StfuVxNZFqp2nu4GkPAAT9hxMWQJYKybv276fZzlyhsxw2@vger.kernel.org X-Gm-Message-State: AOJu0YxA7Z6+Hp/SR5oKX4GKey32YvjvjARnkAyT+GZDaE1ZehXhZZbz ZHT8xfcChr7xM2FndGGXjmZBoQHF7u7HnZ6EiN+HS+wXubhNhHwlgDjoz0kNMKtJ X-Gm-Gg: ASbGncsGR03XBckQFLtQKJ0o04kYo8MkNqo/SPERWkI5+vjMcB0xy7KoJJAgZ5SoTEX +ykSj721q+JaGdZGOxs9Tgw1X+1dmf6UtNQDsvwxNkZZ5/PQg1g4ZqFs5OBahfPK0pz3beDH0wU LzNYVpIaConBqxo6exZezP1l5ozKo5whyLO4Wr4SskjP+vIUCG9FaRs2c5YqMWNKkDUxn3Duemf BuU3VUUKdjLqfFcK9CHMVE+O3ri8P283nja4dLnsuQ71Eb7eqnNOp5z3b8Atj5L34Y/N4YEq1zz cLGCn3DJW3Y8i26RGo0Rd8oaFMuypPA= X-Google-Smtp-Source: AGHT+IHH0kPe6LBC8uhMeUjIrHu12aHBMxWW4e5nB5bx4fSeJedqf8Yf3xtC90RHKNWC0VLXDt4VJA== X-Received: by 2002:a05:6512:3f0d:b0:545:532:fd2f with SMTP id 2adb3069b0e04-5451dd9274emr743078e87.12.1739439664464; Thu, 13 Feb 2025 01:41:04 -0800 (PST) Received: from localhost.localdomain ([178.176.176.188]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5451f10cae7sm119518e87.183.2025.02.13.01.41.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 01:41:04 -0800 (PST) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , Brandon Cheo Fusi , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v11 2/3] pwm: Add Allwinner's D1/T113-S3/R329 SoCs PWM support Date: Thu, 13 Feb 2025 12:40:13 +0300 Message-Id: <20250213094018.134081-3-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250213094018.134081-1-privatesub2@gmail.com> References: <20250213094018.134081-1-privatesub2@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Allwinner's D1, T113-S3 and R329 SoCs have a quite different PWM controllers with ones supported by pwm-sun4i driver. This patch adds a PWM controller driver for Allwinner's D1, T113-S3 and R329 SoCs. The main difference between these SoCs is the number of channels defined by the DT property. Co-developed-by: Brandon Cheo Fusi Signed-off-by: Brandon Cheo Fusi Signed-off-by: Aleksandr Shubin --- drivers/pwm/Kconfig | 10 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-sun20i.c | 370 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 381 insertions(+) create mode 100644 drivers/pwm/pwm-sun20i.c diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 0915c1e7df16..778151aa3860 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -652,6 +652,16 @@ config PWM_SUN4I To compile this driver as a module, choose M here: the module will be called pwm-sun4i. =20 +config PWM_SUN20I + tristate "Allwinner D1/T113s/R329 PWM support" + depends on ARCH_SUNXI || COMPILE_TEST + depends on COMMON_CLK + help + Generic PWM framework driver for Allwinner D1/T113s/R329 SoCs. + + To compile this driver as a module, choose M here: the module + will be called pwm-sun20i. + config PWM_SUNPLUS tristate "Sunplus PWM support" depends on ARCH_SUNPLUS || COMPILE_TEST diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index 9081e0c0e9e0..85ad1fe0dde1 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -60,6 +60,7 @@ obj-$(CONFIG_PWM_STM32) +=3D pwm-stm32.o obj-$(CONFIG_PWM_STM32_LP) +=3D pwm-stm32-lp.o obj-$(CONFIG_PWM_STMPE) +=3D pwm-stmpe.o obj-$(CONFIG_PWM_SUN4I) +=3D pwm-sun4i.o +obj-$(CONFIG_PWM_SUN20I) +=3D pwm-sun20i.o obj-$(CONFIG_PWM_SUNPLUS) +=3D pwm-sunplus.o obj-$(CONFIG_PWM_TEGRA) +=3D pwm-tegra.o obj-$(CONFIG_PWM_TIECAP) +=3D pwm-tiecap.o diff --git a/drivers/pwm/pwm-sun20i.c b/drivers/pwm/pwm-sun20i.c new file mode 100644 index 000000000000..409fa8e9bc45 --- /dev/null +++ b/drivers/pwm/pwm-sun20i.c @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PWM Controller Driver for sunxi platforms (D1, T113-S3 and R329) + * + * Limitations: + * - When the parameters change, the current running period is not complet= ed + * and new settings are applied immediately. + * - The PWM output goes to a HIGH-Z state when the channel is disabled. + * - Changing the clock configuration (SUN20I_PWM_CLK_CFG) + * - may cause a brief output glitch. + * + * Copyright (c) 2023 Aleksandr Shubin + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SUN20I_PWM_CLK_CFG(pair) (0x20 + ((pair) * 0x4)) +#define SUN20I_PWM_CLK_CFG_SRC GENMASK(8, 7) +#define SUN20I_PWM_CLK_CFG_DIV_M GENMASK(3, 0) +#define SUN20I_PWM_CLK_DIV_M_MAX 8 + +#define SUN20I_PWM_CLK_GATE 0x40 +#define SUN20I_PWM_CLK_GATE_BYPASS(chan) BIT((chan) + 16) +#define SUN20I_PWM_CLK_GATE_GATING(chan) BIT(chan) + +#define SUN20I_PWM_ENABLE 0x80 +#define SUN20I_PWM_ENABLE_EN(chan) BIT(chan) + +#define SUN20I_PWM_CTL(chan) (0x100 + (chan) * 0x20) +#define SUN20I_PWM_CTL_ACT_STA BIT(8) +#define SUN20I_PWM_CTL_PRESCAL_K GENMASK(7, 0) +#define SUN20I_PWM_CTL_PRESCAL_K_MAX field_max(SUN20I_PWM_CTL_PRESCAL_K) + +#define SUN20I_PWM_PERIOD(chan) (0x104 + (chan) * 0x20) +#define SUN20I_PWM_PERIOD_ENTIRE_CYCLE GENMASK(31, 16) +#define SUN20I_PWM_PERIOD_ACT_CYCLE GENMASK(15, 0) + +#define SUN20I_PWM_PCNTR_SIZE BIT(16) + +/* + * SUN20I_PWM_MAGIC is used to quickly compute the values of the clock div= iders + * div_m (SUN20I_PWM_CLK_CFG_DIV_M) & prescale_k (SUN20I_PWM_CTL_PRESCAL_K) + * without using a loop. These dividers limit the # of cycles in a period + * to SUN20I_PWM_PCNTR_SIZE (65536) by applying a scaling factor of + * 1/(div_m * (prescale_k + 1)) to the clock source. + * + * SUN20I_PWM_MAGIC is derived by solving for div_m and prescale_k + * such that for a given requested period, + * + * i) div_m is minimized for any prescale_k =E2=89=A4 SUN20I_PWM_CTL_PRESC= AL_K_MAX, + * ii) prescale_k is minimized. + * + * The derivation proceeds as follows, with val =3D # of cycles for reques= ted + * period: + * + * for a given value of div_m we want the smallest prescale_k such that + * + * (val >> div_m) // (prescale_k + 1) =E2=89=A4 65536 (=3D SUN20I_PWM_PCNT= R_SIZE) + * + * This is equivalent to: + * + * (val >> div_m) =E2=89=A4 65536 * (prescale_k + 1) + prescale_k + * =E2=9F=BA (val >> div_m) =E2=89=A4 65537 * prescale_k + 65536 + * =E2=9F=BA (val >> div_m) - 65536 =E2=89=A4 65537 * prescale_k + * =E2=9F=BA ((val >> div_m) - 65536) / 65537 =E2=89=A4 prescale_k + * + * As prescale_k is integer, this becomes + * + * ((val >> div_m) - 65536) // 65537 =E2=89=A4 prescale_k + * + * And is minimized at + * + * ((val >> div_m) - 65536) // 65537 + * + * Now we pick the smallest div_m that satifies prescale_k =E2=89=A4 255 + * (i.e SUN20I_PWM_CTL_PRESCAL_K_MAX), + * + * ((val >> div_m) - 65536) // 65537 =E2=89=A4 255 + * =E2=9F=BA (val >> div_m) - 65536 =E2=89=A4 255 * 65537 + 65536 + * =E2=9F=BA val >> div_m =E2=89=A4 255 * 65537 + 2 * 65536 + * =E2=9F=BA val >> div_m < (255 * 65537 + 2 * 65536 + 1) + * =E2=9F=BA div_m =3D fls((val) / (255 * 65537 + 2 * 65536 + 1)) + * + * Suggested by Uwe Kleine-K=C3=B6nig + */ +#define SUN20I_PWM_MAGIC (255 * 65537 + 2 * 65536 + 1) +#define SUN20I_PWM_DIV_CONST 65537 + +struct sun20i_pwm_chip { + struct clk *clk_hosc, *clk_apb; + void __iomem *base; +}; + +static inline struct sun20i_pwm_chip *to_sun20i_pwm_chip(struct pwm_chip *= chip) +{ + return pwmchip_get_drvdata(chip); +} + +static inline u32 sun20i_pwm_readl(struct sun20i_pwm_chip *chip, + unsigned long offset) +{ + return readl(chip->base + offset); +} + +static inline void sun20i_pwm_writel(struct sun20i_pwm_chip *chip, + u32 val, unsigned long offset) +{ + writel(val, chip->base + offset); +} + +static int sun20i_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *pwm, + struct pwm_state *state) +{ + struct sun20i_pwm_chip *sun20i_chip =3D to_sun20i_pwm_chip(chip); + u16 ent_cycle, act_cycle, prescale_k; + u64 clk_rate, tmp; + u8 div_m; + u32 val; + + val =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm / 2)); + div_m =3D FIELD_GET(SUN20I_PWM_CLK_CFG_DIV_M, val); + if (div_m > SUN20I_PWM_CLK_DIV_M_MAX) + div_m =3D SUN20I_PWM_CLK_DIV_M_MAX; + + /* + * If CLK_CFG_SRC is 0, use the hosc clock; + * otherwise (any nonzero value) use the APB clock. + */ + if (FIELD_GET(SUN20I_PWM_CLK_CFG_SRC, val) =3D=3D 0) + clk_rate =3D clk_get_rate(sun20i_chip->clk_hosc); + else + clk_rate =3D clk_get_rate(sun20i_chip->clk_apb); + + val =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(pwm->hwpwm)); + state->polarity =3D (SUN20I_PWM_CTL_ACT_STA & val) ? + PWM_POLARITY_NORMAL : PWM_POLARITY_INVERSED; + + prescale_k =3D FIELD_GET(SUN20I_PWM_CTL_PRESCAL_K, val) + 1; + + val =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_ENABLE); + state->enabled =3D (SUN20I_PWM_ENABLE_EN(pwm->hwpwm) & val) ? true : fals= e; + + val =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_PERIOD(pwm->hwpwm)); + + act_cycle =3D FIELD_GET(SUN20I_PWM_PERIOD_ACT_CYCLE, val); + ent_cycle =3D FIELD_GET(SUN20I_PWM_PERIOD_ENTIRE_CYCLE, val); + + /* + * The duration of the active phase should not be longer + * than the duration of the period + */ + if (act_cycle > ent_cycle) + act_cycle =3D ent_cycle; + + /* + * We have act_cycle <=3D ent_cycle <=3D 0xffff, prescale_k <=3D 0x100, + * div_m <=3D 8. So the multiplication fits into an u64 without + * overflow. + */ + tmp =3D ((u64)(act_cycle) * prescale_k << div_m) * NSEC_PER_SEC; + state->duty_cycle =3D DIV_ROUND_UP_ULL(tmp, clk_rate); + tmp =3D ((u64)(ent_cycle) * prescale_k << div_m) * NSEC_PER_SEC; + state->period =3D DIV_ROUND_UP_ULL(tmp, clk_rate); + + return 0; +} + +static int sun20i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct sun20i_pwm_chip *sun20i_chip =3D to_sun20i_pwm_chip(chip); + u64 bus_rate, hosc_rate, val, ent_cycle, act_cycle; + u32 clk_gate, clk_cfg, pwm_en, ctl, reg_period; + u32 prescale_k, div_m; + bool use_bus_clk; + + pwm_en =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_ENABLE); + + if (state->enabled !=3D pwm->state.enabled) { + clk_gate =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_GATE); + + if (!state->enabled) { + clk_gate &=3D ~SUN20I_PWM_CLK_GATE_GATING(pwm->hwpwm); + pwm_en &=3D ~SUN20I_PWM_ENABLE_EN(pwm->hwpwm); + sun20i_pwm_writel(sun20i_chip, pwm_en, SUN20I_PWM_ENABLE); + sun20i_pwm_writel(sun20i_chip, clk_gate, SUN20I_PWM_CLK_GATE); + + return 0; + } + } + + ctl =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CTL(pwm->hwpwm)); + clk_cfg =3D sun20i_pwm_readl(sun20i_chip, SUN20I_PWM_CLK_CFG(pwm->hwpwm /= 2)); + hosc_rate =3D clk_get_rate(sun20i_chip->clk_hosc); + bus_rate =3D clk_get_rate(sun20i_chip->clk_apb); + if (pwm_en & SUN20I_PWM_ENABLE_EN(pwm->hwpwm ^ 1)) { + /* If the neighbor channel is enabled, use the current clock settings */ + use_bus_clk =3D FIELD_GET(SUN20I_PWM_CLK_CFG_SRC, clk_cfg) !=3D 0; + val =3D mul_u64_u64_div_u64(state->period, + (use_bus_clk ? bus_rate : hosc_rate), + NSEC_PER_SEC); + + div_m =3D FIELD_GET(SUN20I_PWM_CLK_CFG_DIV_M, clk_cfg); + } else { + /* + * Select the clock source based on the period. + * Since bus_rate > hosc_rate, which means bus_rate + * can provide a higher frequency than hosc_rate. + */ + use_bus_clk =3D false; + val =3D mul_u64_u64_div_u64(state->period, hosc_rate, NSEC_PER_SEC); + /* + * If the calculated value is =E2=89=A4 1, the period is too short + * for proper PWM operation + */ + if (val <=3D 1) { + use_bus_clk =3D true; + val =3D mul_u64_u64_div_u64(state->period, bus_rate, NSEC_PER_SEC); + if (val <=3D 1) + return -EINVAL; + } + div_m =3D fls(DIV_ROUND_DOWN_ULL(val, SUN20I_PWM_MAGIC)); + if (div_m > SUN20I_PWM_CLK_DIV_M_MAX) + return -EINVAL; + + /* Set up the CLK_DIV_M and clock CLK_SRC */ + clk_cfg =3D FIELD_PREP(SUN20I_PWM_CLK_CFG_DIV_M, div_m); + clk_cfg |=3D FIELD_PREP(SUN20I_PWM_CLK_CFG_SRC, use_bus_clk); + + sun20i_pwm_writel(sun20i_chip, clk_cfg, SUN20I_PWM_CLK_CFG(pwm->hwpwm / = 2)); + } + + /* Calculate prescale_k and determine the number of cycles for a full PWM= period */ + ent_cycle =3D val >> div_m; + prescale_k =3D DIV_ROUND_DOWN_ULL(ent_cycle, SUN20I_PWM_DIV_CONST); + if (prescale_k > SUN20I_PWM_CTL_PRESCAL_K_MAX) + prescale_k =3D SUN20I_PWM_CTL_PRESCAL_K_MAX; + + /* ent_cycle must not be zero */ + if (ent_cycle =3D=3D 0) + return -EINVAL; + do_div(ent_cycle, prescale_k + 1); + + /* For N cycles, PPRx.PWM_ENTIRE_CYCLE =3D (N-1) */ + reg_period =3D FIELD_PREP(SUN20I_PWM_PERIOD_ENTIRE_CYCLE, ent_cycle - 1); + + /* Calculate the active cycles (duty cycle) */ + val =3D mul_u64_u64_div_u64(state->duty_cycle, + (use_bus_clk ? bus_rate : hosc_rate), + NSEC_PER_SEC); + act_cycle =3D val >> div_m; + do_div(act_cycle, prescale_k + 1); + + /* + * The formula of the output period and the duty-cycle for PWM are as fol= lows. + * T period =3D PWM0_PRESCALE_K / PWM01_CLK * (PPR0.PWM_ENTIRE_CYCLE + 1) + * T high-level =3D PWM0_PRESCALE_K / PWM01_CLK * PPR0.PWM_ACT_CYCLE + * Duty-cycle =3D T high-level / T period + */ + reg_period |=3D FIELD_PREP(SUN20I_PWM_PERIOD_ACT_CYCLE, act_cycle); + sun20i_pwm_writel(sun20i_chip, reg_period, SUN20I_PWM_PERIOD(pwm->hwpwm)); + + ctl =3D FIELD_PREP(SUN20I_PWM_CTL_PRESCAL_K, prescale_k); + if (state->polarity =3D=3D PWM_POLARITY_NORMAL) + ctl |=3D SUN20I_PWM_CTL_ACT_STA; + + sun20i_pwm_writel(sun20i_chip, ctl, SUN20I_PWM_CTL(pwm->hwpwm)); + + if (state->enabled !=3D pwm->state.enabled) { + clk_gate &=3D ~SUN20I_PWM_CLK_GATE_BYPASS(pwm->hwpwm); + clk_gate |=3D SUN20I_PWM_CLK_GATE_GATING(pwm->hwpwm); + pwm_en |=3D SUN20I_PWM_ENABLE_EN(pwm->hwpwm); + sun20i_pwm_writel(sun20i_chip, pwm_en, SUN20I_PWM_ENABLE); + sun20i_pwm_writel(sun20i_chip, clk_gate, SUN20I_PWM_CLK_GATE); + } + + return 0; +} + +static const struct pwm_ops sun20i_pwm_ops =3D { + .apply =3D sun20i_pwm_apply, + .get_state =3D sun20i_pwm_get_state, +}; + +static const struct of_device_id sun20i_pwm_dt_ids[] =3D { + { .compatible =3D "allwinner,sun20i-d1-pwm" }, + { } +}; +MODULE_DEVICE_TABLE(of, sun20i_pwm_dt_ids); + +static int sun20i_pwm_probe(struct platform_device *pdev) +{ + struct pwm_chip *chip; + struct sun20i_pwm_chip *sun20i_chip; + struct clk *clk_bus; + struct reset_control *rst; + u32 npwm; + int ret; + + ret =3D of_property_read_u32(pdev->dev.of_node, "allwinner,npwms", &npwm); + if (ret < 0) + npwm =3D 8; /* Default value */ + + if (npwm > 16) { + dev_info(&pdev->dev, "Limiting number of PWM lines from %u to 16", npwm); + npwm =3D 16; + } + + chip =3D devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*sun20i_chip)); + if (IS_ERR(chip)) + return PTR_ERR(chip); + sun20i_chip =3D to_sun20i_pwm_chip(chip); + + sun20i_chip->base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(sun20i_chip->base)) + return PTR_ERR(sun20i_chip->base); + + clk_bus =3D devm_clk_get_enabled(&pdev->dev, "bus"); + if (IS_ERR(clk_bus)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk_bus), + "Failed to get bus clock\n"); + + sun20i_chip->clk_hosc =3D devm_clk_get_enabled(&pdev->dev, "hosc"); + if (IS_ERR(sun20i_chip->clk_hosc)) + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_hosc), + "Failed to get hosc clock\n"); + + sun20i_chip->clk_apb =3D devm_clk_get_enabled(&pdev->dev, "apb"); + if (IS_ERR(sun20i_chip->clk_apb)) + return dev_err_probe(&pdev->dev, PTR_ERR(sun20i_chip->clk_apb), + "Failed to get apb clock\n"); + + if (clk_get_rate(sun20i_chip->clk_apb) <=3D clk_get_rate(sun20i_chip->clk= _hosc)) + dev_info(&pdev->dev, "APB clock must be greater than hosc clock"); + + rst =3D devm_reset_control_get_exclusive_deasserted(&pdev->dev, NULL); + if (IS_ERR(rst)) + return dev_err_probe(&pdev->dev, PTR_ERR(rst), + "Failed to get reset control\n"); + + chip->ops =3D &sun20i_pwm_ops; + + ret =3D devm_pwmchip_add(&pdev->dev, chip); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, "Failed to add PWM chip\n"); + + return 0; +} + +static struct platform_driver sun20i_pwm_driver =3D { + .driver =3D { + .name =3D "sun20i-pwm", + .of_match_table =3D sun20i_pwm_dt_ids, + }, + .probe =3D sun20i_pwm_probe, +}; +module_platform_driver(sun20i_pwm_driver); + +MODULE_AUTHOR("Aleksandr Shubin "); +MODULE_DESCRIPTION("Allwinner sun20i PWM driver"); +MODULE_LICENSE("GPL"); --=20 2.25.1 From nobody Fri Dec 19 02:50:44 2025 Received: from mail-lf1-f43.google.com (mail-lf1-f43.google.com [209.85.167.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3F6F21148B; Thu, 13 Feb 2025 09:41:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739439675; cv=none; b=MWt2kbYeS8k5k6JP7gRg7eOMIznZu5m0YphUm1WHg6tFHmFSxIiIcdZDiAhpntqzA/0IFJi47RQkYEyf6tfZpoGAFBh0XQ1NWcaCqHwecdiq0lXR0AyO5EMb6ROZljVCbTc4zvVPnn8AKN4U+F0svnxEaoXhShw8Q01A0TBjTZA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739439675; c=relaxed/simple; bh=BHjvuHtxcGbYTJxuDTg/fs/1zRBNwMIIEfEqMmhl7qw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eVqagJFD5g1rvry+16P3EZEtIVSpZttv1rCgcmVQouEsA73OmcKtCUg3FzJLGkAAaJn2uSWgceuj8JQscCMuQjgSHqDiAGUMHXu9oPz7FxhzFzo3SVdz6VKH7TwtgOx3hkQXj2QiXKh37Kvz9AU+/xzDmLsw5TXZsUlTrz9gcb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=NQLL/MzJ; arc=none smtp.client-ip=209.85.167.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="NQLL/MzJ" Received: by mail-lf1-f43.google.com with SMTP id 2adb3069b0e04-5451d1d56a7so738198e87.0; Thu, 13 Feb 2025 01:41:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1739439671; x=1740044471; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RYYMYkxftkNwTdyqS8CRT4NccxOq5tlDjvnPZc99yTM=; b=NQLL/MzJvnRr0uOfpjLksWEst1PwfbumlXH7KFX2BSH2vcLguLQ2ZmPSVOWz69X4HF ySfD+l5UDUfv3/Z3RXPZP7aD2ZtSC8KFW0OoFUHFS50v3JMyF7FS51xMGTXYNYcYpOL3 B2rZHrZ7prqLji19WGx4+SWbgDfEeOO01WUgqWN3TF87tfP5jykaAMJ3cFvNpmd/J4GD zcQWYBEWt0K0t0Nw/VNs4a7PgnLNJdgWr0g/Mw7YyHvm5Sm2WAbMyhkpuO6HgVixSR6C 8W3zwzBPy7LmIB8bu3RONRlOQopHtJemrX+7fvgthLBSOj3QJNRKtGcgTtTBtMMU8BSO S7wg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1739439671; x=1740044471; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RYYMYkxftkNwTdyqS8CRT4NccxOq5tlDjvnPZc99yTM=; b=oymqbpseLzj/PO/t66yL5Tl26gTyyzWAK9D8cVhT2JZd+ErOebZlGJo3RMkec4UJ1Q bpPMysmj6zlug6L5TfEceGOcXVehjSL6N6SM/6Dn59s3Uzp9ndoYc4zl1IpyBEahTjTe BmzUlbcZ60XtkoawbeuViOBYI175FCiVcTUp3rg7p54LxigZ7yg8WQVTfkhFxVHGVYrm OGknPPMswXG1iwXoOvRpME+HpvxjmB6rG7cvNc0qWHH9hsOXj9TnUakm2DEju7WNpnDE tIwcydIDrHsERe2C6xbOgGsCQvUfe+99+wP0qCChlVoeJrQJ9Zch1oJEH14PUfaM9z1C oMwA== X-Forwarded-Encrypted: i=1; AJvYcCUPqxq99TYIi9y2XCVts47q/FVmjt2RHjBSVpjX85qcXy1QfL1awgkSJ7s4Yt2ssRXSaN7/NAYIVjmN@vger.kernel.org, AJvYcCWRaatzD1L9DMI+u6n3uWiISrMn68RZ9/iZ53cD5KqQfu+8H3nCfjNkyOiryoai1GTG6JhEVOT2K32A@vger.kernel.org X-Gm-Message-State: AOJu0Yz/nEdCyOwzsc92Fl3JhOxhhwvOYRXlVLGf1utshgZPPgYxsTmG iBwcnVuSGbzvd7pIVEGIZ7lqeteHJzzlsh7vzLhBVBWF9K7gIWta6VpRPJ2Iys9X X-Gm-Gg: ASbGncvCLi9s1C6Kn/CreJvLkHKdi98s331gghlCLLpNHC+42AKPR5JjE+xZHx6zfVB VwyD7T8FQmmAD1uTcYd/VBLZ7WX840ZJ++5+NYro3UNX2Oa5c8OswJRqPEHEBSVdn6Sk8dO46mi aDMkzx3Xn6saQE0QEfwmcHjcgHWtY3So3lQ/VYfT0Ih8LraVaaBWrHgRLjcs+ChKCVAq4uacfOO uZo2SVQk6bRBMcR0EPE9V5S8Nbj4fCU7Tsrh+6cnhUSfSbkUxgDZ4YYnpe43S5WZmR5KcwEgk5L nbFtLzZ7iQN3VVr1jRkcS4kXIgyiLWs= X-Google-Smtp-Source: AGHT+IEU1Xe2lAmPO6iNBTAj5sggwrT8IjsKe7vRboIZMPv0WTY0Zwji2mjdrlZbGMkJm2gu+P6b7Q== X-Received: by 2002:a05:6512:3d1b:b0:545:8f7:8596 with SMTP id 2adb3069b0e04-5451e5080e4mr706332e87.17.1739439671065; Thu, 13 Feb 2025 01:41:11 -0800 (PST) Received: from localhost.localdomain ([178.176.176.188]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5451f10cae7sm119518e87.183.2025.02.13.01.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 01:41:10 -0800 (PST) From: Aleksandr Shubin To: linux-kernel@vger.kernel.org Cc: Aleksandr Shubin , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Cheo Fusi , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-riscv@lists.infradead.org Subject: [PATCH v11 3/3] riscv: dts: allwinner: d1: Add pwm node Date: Thu, 13 Feb 2025 12:40:14 +0300 Message-Id: <20250213094018.134081-4-privatesub2@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250213094018.134081-1-privatesub2@gmail.com> References: <20250213094018.134081-1-privatesub2@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" D1 and T113s contain a pwm controller with 8 channels. This controller is supported by the sun20i-pwm driver. Add a device tree node for it. Signed-off-by: Aleksandr Shubin Reviewed-by: Jernej Skrabec --- arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv= /boot/dts/allwinner/sunxi-d1s-t113.dtsi index e4175adb028d..2c26cb8b2b07 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -145,6 +145,18 @@ uart3_pb_pins: uart3-pb-pins { }; }; =20 + pwm: pwm@2000c00 { + compatible =3D "allwinner,sun20i-d1-pwm"; + reg =3D <0x02000c00 0x400>; + clocks =3D <&ccu CLK_BUS_PWM>, + <&dcxo>, + <&ccu CLK_APB0>; + clock-names =3D "bus", "hosc", "apb"; + resets =3D <&ccu RST_BUS_PWM>; + status =3D "disabled"; + #pwm-cells =3D <0x3>; + }; + ccu: clock-controller@2001000 { compatible =3D "allwinner,sun20i-d1-ccu"; reg =3D <0x2001000 0x1000>; --=20 2.25.1