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Thu, 13 Feb 2025 09:04:20 -0800 (PST) Received: from [127.0.0.2] ([2a02:2454:ff21:ef41:29d1:1370:c895:9654]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4395a1b84bcsm55990785e9.40.2025.02.13.09.04.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 13 Feb 2025 09:04:20 -0800 (PST) From: Stephan Gerhold Date: Thu, 13 Feb 2025 18:04:00 +0100 Subject: [PATCH] irqchip/qcom-pdc: Workaround hardware register bug on X1E80100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250213-x1e80100-pdc-hw-wa-v1-1-f8c248a48cba@linaro.org> X-B4-Tracking: v=1; b=H4sIAP8lrmcC/x3MQQ5AMBBA0avIrE0yUxrqKmKBDmaDtAlNxN01l m/x/wNRgkqErnggyKVRjz2DywLmbdxXQfXZYMhYMsyYWFpiIjz9jNuN94hTU7XeOVlq6yCHZ5B F0z/th/f9AK6l91hkAAAA X-Change-ID: 20250211-x1e80100-pdc-hw-wa-b738d99ef459 To: Thomas Gleixner Cc: Bjorn Andersson , Konrad Dybcio , Rajendra Nayak , Maulik Shah , Srinivas Kandagatla , Abel Vesa , Johan Hovold , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 On X1E80100, there is a hardware bug in the register logic of the IRQ_ENABLE_BANK register. While read accesses work on the normal address, all write accesses must be made to a shifted address. Without a workaround for this, the wrong interrupt gets enabled in the PDC and it is impossible to wakeup from deep suspend (CX collapse). This has not caused problems so far, because the deep suspend state was not enabled. We need a workaround now since work is ongoing to fix this. Introduce a workaround for the problem by matching the qcom,x1e80100-pdc compatible and shift the write address by the necessary offset. Signed-off-by: Stephan Gerhold Tested-by: Johan Hovold --- drivers/irqchip/qcom-pdc.c | 51 ++++++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 48 insertions(+), 3 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 74b2f124116e3415d77269959c1ed5e7d7efd671..9ce44121db21ac05b370046feb0= 9c17122f80b19 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -21,9 +21,11 @@ #include =20 #define PDC_MAX_GPIO_IRQS 256 +#define PDC_DRV_OFFSET 0x10000 =20 /* Valid only on HW version < 3.2 */ #define IRQ_ENABLE_BANK 0x10 +#define IRQ_ENABLE_BANK_MAX (IRQ_ENABLE_BANK + BITS_TO_BYTES(PDC_MAX_GPIO_= IRQS)) #define IRQ_i_CFG 0x110 =20 /* Valid only on HW version >=3D 3.2 */ @@ -46,13 +48,20 @@ struct pdc_pin_region { =20 static DEFINE_RAW_SPINLOCK(pdc_lock); static void __iomem *pdc_base; +static void __iomem *pdc_drv1; static struct pdc_pin_region *pdc_region; static int pdc_region_cnt; static unsigned int pdc_version; +static bool pdc_x1e_quirk; + +static void _pdc_reg_write(void __iomem *base, int reg, u32 i, u32 val) +{ + writel_relaxed(val, base + reg + i * sizeof(u32)); +} =20 static void pdc_reg_write(int reg, u32 i, u32 val) { - writel_relaxed(val, pdc_base + reg + i * sizeof(u32)); + _pdc_reg_write(pdc_base, reg, i, val); } =20 static u32 pdc_reg_read(int reg, u32 i) @@ -60,6 +69,26 @@ static u32 pdc_reg_read(int reg, u32 i) return readl_relaxed(pdc_base + reg + i * sizeof(u32)); } =20 +static void pdc_x1e_irq_enable_write(u32 bank, u32 enable) +{ + void __iomem *base =3D pdc_base; /* DRV2 */ + + /* + * Workaround hardware bug in the register logic on X1E80100: + * - For bank 0-1, writes need to be made to DRV1, bank 3 and 4. + * - For bank 2-4, writes need to be made to DRV2, bank 0-2. + * - Bank 5 works as expected. + */ + if (bank <=3D 1) { + base =3D pdc_drv1; + bank +=3D 3; + } else if (bank <=3D 4) { + bank -=3D 2; + } + + _pdc_reg_write(base, IRQ_ENABLE_BANK, bank, enable); +} + static void __pdc_enable_intr(int pin_out, bool on) { unsigned long enable; @@ -72,7 +101,11 @@ static void __pdc_enable_intr(int pin_out, bool on) =20 enable =3D pdc_reg_read(IRQ_ENABLE_BANK, index); __assign_bit(mask, &enable, on); - pdc_reg_write(IRQ_ENABLE_BANK, index, enable); + + if (pdc_x1e_quirk) + pdc_x1e_irq_enable_write(index, enable); + else + pdc_reg_write(IRQ_ENABLE_BANK, index, enable); } else { enable =3D pdc_reg_read(IRQ_i_CFG, pin_out); __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on); @@ -324,10 +357,21 @@ static int qcom_pdc_init(struct device_node *node, st= ruct device_node *parent) if (res_size > resource_size(&res)) pr_warn("%pOF: invalid reg size, please fix DT\n", node); =20 + if (of_device_is_compatible(node, "qcom,x1e80100-pdc")) { + pdc_drv1 =3D ioremap(res.start - PDC_DRV_OFFSET, IRQ_ENABLE_BANK_MAX); + if (!pdc_drv1) { + pr_err("%pOF: unable to map PDC DRV1 region\n", node); + return -ENXIO; + } + + pdc_x1e_quirk =3D true; + } + pdc_base =3D ioremap(res.start, res_size); if (!pdc_base) { pr_err("%pOF: unable to map PDC registers\n", node); - return -ENXIO; + ret =3D -ENXIO; + goto fail; } =20 pdc_version =3D pdc_reg_read(PDC_VERSION_REG, 0); @@ -363,6 +407,7 @@ static int qcom_pdc_init(struct device_node *node, stru= ct device_node *parent) fail: kfree(pdc_region); iounmap(pdc_base); + iounmap(pdc_drv1); return ret; } =20 --- base-commit: 2014c95afecee3e76ca4a56956a936e23283f05b change-id: 20250211-x1e80100-pdc-hw-wa-b738d99ef459 Best regards, --=20 Stephan Gerhold