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(unknown [10.28.34.196]) by maili.marvell.com (Postfix) with ESMTP id 5751C5B693C; Wed, 12 Feb 2025 03:49:55 -0800 (PST) From: Linu Cherian To: , , CC: , , , , , , , , , , , Linu Cherian Subject: [PATCH v14 6/8] coresight: tmc: Stop trace capture on FlIn Date: Wed, 12 Feb 2025 17:19:16 +0530 Message-ID: <20250212114918.548431-7-lcherian@marvell.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250212114918.548431-1-lcherian@marvell.com> References: <20250212114918.548431-1-lcherian@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: G2ABLdvJqEv5MRdu483MMcPrAsSnWma6 X-Proofpoint-ORIG-GUID: G2ABLdvJqEv5MRdu483MMcPrAsSnWma6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-12_04,2025-02-11_01,2024-11-22_01 Content-Type: text/plain; charset="utf-8" Configure TMC ETR and ETF to flush and stop trace capture on FlIn event based on sysfs attribute, /sys/bus/coresight/devices/tmc_etXn/stop_on_flush. Signed-off-by: Linu Cherian --- Changelog from v13: No changes. .../hwtracing/coresight/coresight-tmc-core.c | 31 +++++++++++++++++++ .../hwtracing/coresight/coresight-tmc-etf.c | 12 ++++--- .../hwtracing/coresight/coresight-tmc-etr.c | 12 ++++--- drivers/hwtracing/coresight/coresight-tmc.h | 2 ++ 4 files changed, 47 insertions(+), 10 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 045d37606750..d5122e12daa7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -532,9 +532,40 @@ static ssize_t buffer_size_store(struct device *dev, =20 static DEVICE_ATTR_RW(buffer_size); =20 +static ssize_t stop_on_flush_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + return sprintf(buf, "%#x\n", drvdata->stop_on_flush); +} + +static ssize_t stop_on_flush_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t size) +{ + int ret; + u8 val; + struct tmc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + ret =3D kstrtou8(buf, 0, &val); + if (ret) + return ret; + if (val) + drvdata->stop_on_flush =3D true; + else + drvdata->stop_on_flush =3D false; + + return size; +} + +static DEVICE_ATTR_RW(stop_on_flush); + + static struct attribute *coresight_tmc_attrs[] =3D { &dev_attr_trigger_cntr.attr, &dev_attr_buffer_size.attr, + &dev_attr_stop_on_flush.attr, NULL, }; =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index 0f9155a10ac2..bdc3a7e9ba06 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -19,6 +19,7 @@ static int tmc_set_etf_buffer(struct coresight_device *cs= dev, static int __tmc_etb_enable_hw(struct tmc_drvdata *drvdata) { int rc =3D 0; + u32 ffcr; =20 CS_UNLOCK(drvdata->base); =20 @@ -32,10 +33,12 @@ static int __tmc_etb_enable_hw(struct tmc_drvdata *drvd= ata) } =20 writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE); - writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | - TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT | - TMC_FFCR_TRIGON_TRIGIN, - drvdata->base + TMC_FFCR); + + ffcr =3D TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN | + TMC_FFCR_FON_TRIG_EVT | TMC_FFCR_TRIGON_TRIGIN; + if (drvdata->stop_on_flush) + ffcr |=3D TMC_FFCR_STOP_ON_FLUSH; + writel_relaxed(ffcr, drvdata->base + TMC_FFCR); =20 writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); tmc_enable_hw(drvdata); @@ -225,7 +228,6 @@ static int tmc_enable_etf_sink_sysfs(struct coresight_d= evice *csdev) used =3D true; drvdata->buf =3D buf; } - ret =3D tmc_etb_enable_hw(drvdata); if (!ret) { coresight_set_mode(csdev, CS_MODE_SYSFS); diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index c92556e1b4db..eda7cdad0e2b 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1060,7 +1060,7 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvd= ata) =20 static int __tmc_etr_enable_hw(struct tmc_drvdata *drvdata) { - u32 axictl, sts; + u32 axictl, sts, ffcr; struct etr_buf *etr_buf =3D drvdata->etr_buf; int rc =3D 0; =20 @@ -1106,10 +1106,12 @@ static int __tmc_etr_enable_hw(struct tmc_drvdata *= drvdata) writel_relaxed(sts, drvdata->base + TMC_STS); } =20 - writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | - TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT | - TMC_FFCR_TRIGON_TRIGIN, - drvdata->base + TMC_FFCR); + ffcr =3D TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI | TMC_FFCR_FON_FLIN | + TMC_FFCR_FON_TRIG_EVT | TMC_FFCR_TRIGON_TRIGIN; + if (drvdata->stop_on_flush) + ffcr |=3D TMC_FFCR_STOP_ON_FLUSH; + writel_relaxed(ffcr, drvdata->base + TMC_FFCR); + writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG); tmc_enable_hw(drvdata); =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracin= g/coresight/coresight-tmc.h index e3707b69abff..482a425faa41 100644 --- a/drivers/hwtracing/coresight/coresight-tmc.h +++ b/drivers/hwtracing/coresight/coresight-tmc.h @@ -220,6 +220,7 @@ struct tmc_resrv_buf { * @pid: Process ID of the process that owns the session that is using * this component. For example this would be the pid of the Perf * process. + * @stop_on_flush: Stop on flush trigger user configuration. * @buf: Snapshot of the trace data for ETF/ETB. * @etr_buf: details of buffer used in TMC-ETR * @len: size of the available trace for ETF/ETB. @@ -251,6 +252,7 @@ struct tmc_drvdata { spinlock_t spinlock; pid_t pid; bool reading; + bool stop_on_flush; union { char *buf; /* TMC ETB */ struct etr_buf *etr_buf; /* TMC ETR */ --=20 2.34.1