From nobody Fri Dec 19 06:03:06 2025 Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB7BA20B210; Wed, 12 Feb 2025 15:47:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739375273; cv=none; b=PgbaB36jVzxWo6i+YxXV4JRLZAbiKLnG0XtweCFEfbO1H+N6Qb4HkCIaGVT+/hqHDusIxbcqMgVJuVhwoAVOUYTSzXNn0Hh9eSq5lU9ik8P1Pr3NOfK5K1iswBfQNoYInGqgQy22NvcWpS3mhrynn0kRBx9ehu9YtJ6CwE5Gbsc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739375273; c=relaxed/simple; bh=1jztkzYD9KJ/1fJA6MUcU0W065d9PyvnLOCcHtgK/nM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R3Dqu8ITmfvqm1msPVnZGOXwaarNAI0PT4b5BXdHS8NC/rzlGvJlsDIGj7zp9JWZiaGGJ7v7GaOXnBmDaphfr3gB4d1cea4hUwzBonIapcVcf3Avno00TNZZKi4qsvW9YNAB3thvpru3pv3/RcVmMwrDBxVXnCrwcn64Vb1RlDc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=AsR2Kr+r; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="AsR2Kr+r" Received: by mail.gandi.net (Postfix) with ESMTPSA id CC5D8440FF; Wed, 12 Feb 2025 15:47:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1739375268; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w7OFME9i2IUPBCJlachFUyekEY4wChv9lVNTlta/qgw=; b=AsR2Kr+r0EsfCT0bRR50j86StsO7qBNICof/C8pNBJ9MSjy+WFLvVLL5dcJDVzjlT1+q3r 57rTr179uIMOj88U4BHO1/nsJdJXgCOeFm6VxNOu5NGcHEJUjju9ZvFVAidGTBVIf9545+ JRaA5ObSMEGC0kM8OYoJ04DKOpS3eQmVTcQA2f4z4NPMPyhfDEUF5nt1aWJak5xeM8S+tI /7JAwzJWgqRI+KWpdgEEy/MAt26N34VUK0/SDa/IQiUyirEqvNuwMTA+KZg3Ur8KIFY5do wrwQ1rq0OHH7OQI2NLoVsGq8scg5HX5wHJxOPuDUSNJZh43HYrweV3mtIAXUUQ== From: =?utf-8?q?Alexis_Lothor=C3=A9?= Date: Wed, 12 Feb 2025 16:46:21 +0100 Subject: [PATCH 02/12] wifi: wilc1000: add a read-modify-write API for registers accesses Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250212-wilc3000_bt-v1-2-9609b784874e@bootlin.com> References: <20250212-wilc3000_bt-v1-0-9609b784874e@bootlin.com> In-Reply-To: <20250212-wilc3000_bt-v1-0-9609b784874e@bootlin.com> To: =?utf-8?q?Alexis_Lothor=C3=A9?= , Marcel Holtmann , Luiz Augusto von Dentz , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ajay Singh , Claudiu Beznea , Kalle Valo , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Simon Horman , Nicolas Ferre , Alexandre Belloni Cc: Marek Vasut , Thomas Petazzoni , linux-bluetooth@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-wireless@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org X-Mailer: b4 0.14.2 X-GND-State: clean X-GND-Score: -100 X-GND-Cause: gggruggvucftvghtrhhoucdtuddrgeefvddrtddtgdeggedvkecutefuodetggdotefrodftvfcurfhrohhfihhlvgemucfitefpfffkpdcuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedtudenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephfffufggtgfgkfhfjgfvvefosehtkeertdertdejnecuhfhrohhmpeetlhgvgihishcunfhothhhohhrrocuoegrlhgvgihishdrlhhothhhohhrvgessghoohhtlhhinhdrtghomheqnecuggftrfgrthhtvghrnhepgeevgefhteffuefhheekkeelffffvdeugffgveejffdtvdffudehtedtieevteetnecukfhppedvrgdtvdemkeegvdekmehfleegtgemvgdttdemmehfkeehnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepvdgrtddvmeekgedvkeemfhelgegtmegvtddtmeemfhekhedphhgvlhhopegludelvddrudeikedruddrudeljegnpdhmrghilhhfrhhomheprghlvgigihhsrdhlohhthhhorhgvsegsohhothhlihhnrdgtohhmpdhnsggprhgtphhtthhopedvgedprhgtphhtthhopegtohhnohhrodgutheskhgvrhhnvghlrdhorhhgpdhrtghpthhtoheprhhosghhsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlihhnuhigqdhkvghrnhgvlhesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopeguvghvihgtvghtrhgvvgesvhhgvghrrdhkvghrnhgvlhdrohhrghdpr hgtphhtthhopehkrhiikhdoughtsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehkuhgsrgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtoheplhhinhhugidqrghrmhdqkhgvrhhnvghlsehlihhsthhsrdhinhhfrhgruggvrggurdhorhhgpdhrtghpthhtoheplhhuihiirdguvghnthiisehgmhgrihhlrdgtohhm X-GND-Sasl: alexis.lothore@bootlin.com Many places in wilc driver need to modify a single bit in a register, and then perform the following sequence: read the register, set/reset the needed bit, write the register. This sequence is performed in multiple places in the driver, with a varying amount of checks around possible errors. Replace all those sequences with a new hif_rmw_reg helper. Make sure to perform the write only if needed. Signed-off-by: Alexis Lothor=C3=A9 --- Since the registers meaning and effect is pretty opaque, this commit tries to remain conservative and converts only the "real" read-modify-write sequences: bare writes seemingly trying to affect a single bit but actually affecting the whole register are left untouched. --- drivers/net/wireless/microchip/wilc1000/sdio.c | 68 ++++++------ drivers/net/wireless/microchip/wilc1000/spi.c | 18 +++ drivers/net/wireless/microchip/wilc1000/wlan.c | 145 +++++++++------------= ---- drivers/net/wireless/microchip/wilc1000/wlan.h | 3 + 4 files changed, 105 insertions(+), 129 deletions(-) diff --git a/drivers/net/wireless/microchip/wilc1000/sdio.c b/drivers/net/w= ireless/microchip/wilc1000/sdio.c index af970f9991110807ebd880681ad0e8aaf8a0b9bc..7eab1c493774e197e43bdf26506= 3aa8c5e6dff14 100644 --- a/drivers/net/wireless/microchip/wilc1000/sdio.c +++ b/drivers/net/wireless/microchip/wilc1000/sdio.c @@ -916,6 +916,7 @@ static int wilc_sdio_sync_ext(struct wilc *wilc, int ni= nt) { struct sdio_func *func =3D dev_to_sdio_func(wilc->dev); struct wilc_sdio *sdio_priv =3D wilc->bus_data; + u32 int_en_mask =3D 0; =20 if (nint > MAX_NUM_INT) { dev_err(&func->dev, "Too many interrupts (%d)...\n", nint); @@ -923,61 +924,42 @@ static int wilc_sdio_sync_ext(struct wilc *wilc, int = nint) } =20 if (sdio_priv->irq_gpio) { - u32 reg; int ret, i; =20 /** * interrupt pin mux select **/ - ret =3D wilc_sdio_read_reg(wilc, WILC_PIN_MUX_0, ®); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, WILC_PIN_MUX_0, BIT(8), + BIT(8)); if (ret) { - dev_err(&func->dev, "Failed read reg (%08x)...\n", - WILC_PIN_MUX_0); - return ret; - } - reg |=3D BIT(8); - ret =3D wilc_sdio_write_reg(wilc, WILC_PIN_MUX_0, reg); - if (ret) { - dev_err(&func->dev, "Failed write reg (%08x)...\n", - WILC_PIN_MUX_0); + dev_err(&func->dev, "Failed to set interrupt mux\n"); return ret; } =20 /** * interrupt enable **/ - ret =3D wilc_sdio_read_reg(wilc, WILC_INTR_ENABLE, ®); - if (ret) { - dev_err(&func->dev, "Failed read reg (%08x)...\n", - WILC_INTR_ENABLE); - return ret; - } - for (i =3D 0; (i < 5) && (nint > 0); i++, nint--) - reg |=3D BIT((27 + i)); - ret =3D wilc_sdio_write_reg(wilc, WILC_INTR_ENABLE, reg); + int_en_mask |=3D BIT(WILC_INTR_ENABLE_BIT_BASE + i); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, WILC_INTR_ENABLE, + int_en_mask, int_en_mask); if (ret) { - dev_err(&func->dev, "Failed write reg (%08x)...\n", - WILC_INTR_ENABLE); + dev_err(&func->dev, "Failed to enable interrupts\n"); return ret; } - if (nint) { - ret =3D wilc_sdio_read_reg(wilc, WILC_INTR2_ENABLE, ®); - if (ret) { - dev_err(&func->dev, - "Failed read reg (%08x)...\n", - WILC_INTR2_ENABLE); - return ret; - } =20 + if (nint) { + int_en_mask =3D 0; for (i =3D 0; (i < 3) && (nint > 0); i++, nint--) - reg |=3D BIT(i); + int_en_mask |=3D BIT(i); =20 - ret =3D wilc_sdio_write_reg(wilc, WILC_INTR2_ENABLE, reg); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, + WILC_INTR2_ENABLE, + int_en_mask, + int_en_mask); if (ret) { dev_err(&func->dev, - "Failed write reg (%08x)...\n", - WILC_INTR2_ENABLE); + "Failed to enable internal interrupts\n"); return ret; } } @@ -985,6 +967,23 @@ static int wilc_sdio_sync_ext(struct wilc *wilc, int n= int) return 0; } =20 +static int wilc_sdio_rmw_reg(struct wilc *wilc, u32 reg, u32 mask, u32 dat= a) +{ + u32 old_val, new_val; + int ret =3D 0; + + ret =3D wilc_sdio_read_reg(wilc, reg, &old_val); + if (ret) + return ret; + + new_val =3D old_val & ~mask; + new_val |=3D data; + if (new_val !=3D old_val) + ret =3D wilc_sdio_write_reg(wilc, reg, new_val); + + return ret; +} + /* Global sdio HIF function table */ static const struct wilc_hif_func wilc_hif_sdio =3D { .hif_init =3D wilc_sdio_init, @@ -1003,6 +1002,7 @@ static const struct wilc_hif_func wilc_hif_sdio =3D { .disable_interrupt =3D wilc_sdio_disable_interrupt, .hif_reset =3D wilc_sdio_reset, .hif_is_init =3D wilc_sdio_is_init, + .hif_rmw_reg =3D wilc_sdio_rmw_reg }; =20 static int wilc_sdio_suspend(struct device *dev) diff --git a/drivers/net/wireless/microchip/wilc1000/spi.c b/drivers/net/wi= reless/microchip/wilc1000/spi.c index 5bcabb7decea0fc8d0065a240f4acefabca3346a..aae4262045ff3e5f3668493ef23= 5486e601996f7 100644 --- a/drivers/net/wireless/microchip/wilc1000/spi.c +++ b/drivers/net/wireless/microchip/wilc1000/spi.c @@ -1355,6 +1355,23 @@ static int wilc_spi_sync_ext(struct wilc *wilc, int = nint) return 0; } =20 +static int wilc_spi_rmw_reg(struct wilc *wilc, u32 reg, u32 mask, u32 data) +{ + u32 old_val, new_val; + int ret =3D 0; + + ret =3D wilc_spi_read_reg(wilc, reg, &old_val); + if (ret) + return ret; + + new_val =3D old_val & ~mask; + new_val |=3D data; + if (new_val !=3D old_val) + ret =3D wilc_spi_write_reg(wilc, reg, new_val); + + return ret; +} + /* Global spi HIF function table */ static const struct wilc_hif_func wilc_hif_spi =3D { .hif_init =3D wilc_spi_init, @@ -1371,4 +1388,5 @@ static const struct wilc_hif_func wilc_hif_spi =3D { .hif_sync_ext =3D wilc_spi_sync_ext, .hif_reset =3D wilc_spi_reset, .hif_is_init =3D wilc_spi_is_init, + .hif_rmw_reg =3D wilc_spi_rmw_reg }; diff --git a/drivers/net/wireless/microchip/wilc1000/wlan.c b/drivers/net/w= ireless/microchip/wilc1000/wlan.c index 9d80adc45d6be14c8818e8ef1643db6875cf57d2..f2b13bd44273ebe2ee474eda047= e82bf1287bd6e 100644 --- a/drivers/net/wireless/microchip/wilc1000/wlan.c +++ b/drivers/net/wireless/microchip/wilc1000/wlan.c @@ -578,53 +578,27 @@ static int chip_allow_sleep_wilc1000(struct wilc *wil= c) pr_warn("FW not responding\n"); =20 /* Clear bit 1 */ - ret =3D hif_func->hif_read_reg(wilc, wakeup_reg, ®); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, wakeup_reg, wakeup_bit, 0); if (ret) return ret; - if (reg & wakeup_bit) { - reg &=3D ~wakeup_bit; - ret =3D hif_func->hif_write_reg(wilc, wakeup_reg, reg); - if (ret) - return ret; - } =20 - ret =3D hif_func->hif_read_reg(wilc, from_host_to_fw_reg, ®); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, from_host_to_fw_reg, + from_host_to_fw_bit, 0); if (ret) return ret; - if (reg & from_host_to_fw_bit) { - reg &=3D ~from_host_to_fw_bit; - ret =3D hif_func->hif_write_reg(wilc, from_host_to_fw_reg, reg); - if (ret) - return ret; - } =20 return 0; } =20 static int chip_allow_sleep_wilc3000(struct wilc *wilc) { - u32 reg =3D 0; int ret; - const struct wilc_hif_func *hif_func =3D wilc->hif_func; + u32 wake_bit =3D wilc->io_type =3D=3D WILC_HIF_SDIO ? WILC_SDIO_WAKEUP_BI= T : + WILC_SPI_WAKEUP_BIT; =20 - if (wilc->io_type =3D=3D WILC_HIF_SDIO) { - ret =3D hif_func->hif_read_reg(wilc, WILC_SDIO_WAKEUP_REG, ®); - if (ret) - return ret; - ret =3D hif_func->hif_write_reg(wilc, WILC_SDIO_WAKEUP_REG, - reg & ~WILC_SDIO_WAKEUP_BIT); - if (ret) - return ret; - } else { - ret =3D hif_func->hif_read_reg(wilc, WILC_SPI_WAKEUP_REG, ®); - if (ret) - return ret; - ret =3D hif_func->hif_write_reg(wilc, WILC_SPI_WAKEUP_REG, - reg & ~WILC_SPI_WAKEUP_BIT); - if (ret) - return ret; - } - return 0; + ret =3D wilc->hif_func->hif_rmw_reg(wilc, WILC_SDIO_WAKEUP_REG, wake_bit, + 0); + return ret; } =20 static int chip_allow_sleep(struct wilc *wilc) @@ -699,10 +673,10 @@ static int chip_wakeup_wilc1000(struct wilc *wilc) =20 static int chip_wakeup_wilc3000(struct wilc *wilc) { - u32 wakeup_reg_val, clk_status_reg_val, trials =3D 0; - u32 wakeup_reg, wakeup_bit; + u32 clk_status_reg_val, trials =3D 0; u32 clk_status_reg, clk_status_bit; - int wake_seq_trials =3D 5; + int wake_seq_trials =3D 5, ret; + u32 wakeup_reg, wakeup_bit; const struct wilc_hif_func *hif_func =3D wilc->hif_func; =20 if (wilc->io_type =3D=3D WILC_HIF_SDIO) { @@ -717,10 +691,12 @@ static int chip_wakeup_wilc3000(struct wilc *wilc) clk_status_bit =3D WILC3000_SPI_CLK_STATUS_BIT; } =20 - hif_func->hif_read_reg(wilc, wakeup_reg, &wakeup_reg_val); do { - hif_func->hif_write_reg(wilc, wakeup_reg, wakeup_reg_val | - wakeup_bit); + ret =3D hif_func->hif_rmw_reg(wilc, wakeup_reg, wakeup_bit, + wakeup_bit); + if (ret) + dev_warn(wilc->dev, "Failed to set wake bit\n"); + /* Check the clock status */ hif_func->hif_read_reg(wilc, clk_status_reg, &clk_status_reg_val); @@ -745,8 +721,10 @@ static int chip_wakeup_wilc3000(struct wilc *wilc) * edge on the next loop */ if ((clk_status_reg_val & clk_status_bit) =3D=3D 0) { - hif_func->hif_write_reg(wilc, wakeup_reg, - wakeup_reg_val & (~wakeup_bit)); + ret =3D hif_func->hif_rmw_reg(wilc, wakeup_reg, + wakeup_bit, 0); + if (ret) + dev_warn(wilc->dev, "Failed to set CLK bit\n"); /* added wait before wakeup sequence retry */ usleep_range(200, 300); } @@ -996,11 +974,11 @@ int wilc_wlan_handle_txq(struct wilc *wilc, u32 *txq_= count) break; =20 if (entries =3D=3D 0) { - ret =3D func->hif_read_reg(wilc, WILC_HOST_TX_CTRL, ®); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, + WILC_HOST_TX_CTRL, BIT(0), 0); if (ret) - break; - reg &=3D ~BIT(0); - ret =3D func->hif_write_reg(wilc, WILC_HOST_TX_CTRL, reg); + dev_warn(wilc->dev, + "Failed to reset TX CTRL bit\n"); } } while (0); =20 @@ -1267,9 +1245,12 @@ int wilc_wlan_firmware_download(struct wilc *wilc, c= onst u8 *buffer, if (ret) return ret; =20 - wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); - reg &=3D ~BIT(10); - ret =3D wilc->hif_func->hif_write_reg(wilc, WILC_GLB_RESET_0, reg); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, WILC_GLB_RESET_0, BIT(10), 0); + if (ret) { + dev_err(wilc->dev, "Failed to reset WLAN CPU\n"); + release_bus(wilc, WILC_BUS_RELEASE_ALLOW_SLEEP); + return ret; + } wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); if (reg & BIT(10)) pr_err("%s: Failed to reset\n", __func__); @@ -1357,16 +1338,12 @@ int wilc_wlan_start(struct wilc *wilc) if (ret) goto release; =20 - wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); - if ((reg & BIT(10)) =3D=3D BIT(10)) { - reg &=3D ~BIT(10); - wilc->hif_func->hif_write_reg(wilc, WILC_GLB_RESET_0, reg); - wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); - } - - reg |=3D BIT(10); - ret =3D wilc->hif_func->hif_write_reg(wilc, WILC_GLB_RESET_0, reg); - wilc->hif_func->hif_read_reg(wilc, WILC_GLB_RESET_0, ®); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, WILC_GLB_RESET_0, BIT(10), 0); + if (!ret) + ret =3D wilc->hif_func->hif_rmw_reg(wilc, WILC_GLB_RESET_0, + BIT(10), BIT(10)); + if (ret) + dev_warn(wilc->dev, "Failed to reset WLAN CPU\n"); =20 release: rv =3D release_bus(wilc, WILC_BUS_RELEASE_ONLY); @@ -1375,44 +1352,31 @@ int wilc_wlan_start(struct wilc *wilc) =20 int wilc_wlan_stop(struct wilc *wilc, struct wilc_vif *vif) { - u32 reg =3D 0; int ret, rv; =20 ret =3D acquire_bus(wilc, WILC_BUS_ACQUIRE_AND_WAKEUP); if (ret) return ret; =20 - ret =3D wilc->hif_func->hif_read_reg(wilc, GLOBAL_MODE_CONTROL, ®); - if (ret) - goto release; - - reg &=3D ~WILC_GLOBAL_MODE_ENABLE_WIFI; - ret =3D wilc->hif_func->hif_write_reg(wilc, GLOBAL_MODE_CONTROL, reg); - if (ret) - goto release; - - ret =3D wilc->hif_func->hif_read_reg(wilc, PWR_SEQ_MISC_CTRL, ®); - if (ret) - goto release; - - reg &=3D ~WILC_PWR_SEQ_ENABLE_WIFI_SLEEP; - ret =3D wilc->hif_func->hif_write_reg(wilc, PWR_SEQ_MISC_CTRL, reg); - if (ret) - goto release; - - ret =3D wilc->hif_func->hif_read_reg(wilc, WILC_GP_REG_0, ®); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, GLOBAL_MODE_CONTROL, + WILC_GLOBAL_MODE_ENABLE_WIFI, 0); if (ret) { - netdev_err(vif->ndev, "Error while reading reg\n"); + netdev_err(vif->ndev, "Failed to disable wlan control\n"); goto release; } =20 - ret =3D wilc->hif_func->hif_write_reg(wilc, WILC_GP_REG_0, - (reg | WILC_ABORT_REQ_BIT)); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, PWR_SEQ_MISC_CTRL, + WILC_PWR_SEQ_ENABLE_WIFI_SLEEP, 0); if (ret) { - netdev_err(vif->ndev, "Error while writing reg\n"); + netdev_err(vif->ndev, "Failed to unmux wlan power seq\n"); goto release; } =20 + ret =3D wilc->hif_func->hif_rmw_reg(wilc, WILC_GP_REG_0, + WILC_ABORT_REQ_BIT, 1); + if (ret) + netdev_err(vif->ndev, "Failed to stop wlan CPU\n"); + ret =3D 0; release: /* host comm is disabled - we can't issue sleep command anymore: */ @@ -1641,19 +1605,10 @@ static int init_chip(struct net_device *dev) goto release; =20 if ((wilc->chipid & 0xfff) !=3D 0xa0) { - ret =3D wilc->hif_func->hif_read_reg(wilc, - WILC_CORTUS_RESET_MUX_SEL, - ®); - if (ret) { - netdev_err(dev, "fail read reg 0x1118\n"); - goto release; - } - reg |=3D BIT(0); - ret =3D wilc->hif_func->hif_write_reg(wilc, - WILC_CORTUS_RESET_MUX_SEL, - reg); + ret =3D wilc->hif_func->hif_rmw_reg(wilc, + WILC_CORTUS_RESET_MUX_SEL, BIT(0), BIT(0)); if (ret) { - netdev_err(dev, "fail write reg 0x1118\n"); + netdev_err(dev, "Failed to enable WLAN global reset\n"); goto release; } ret =3D wilc->hif_func->hif_write_reg(wilc, diff --git a/drivers/net/wireless/microchip/wilc1000/wlan.h b/drivers/net/w= ireless/microchip/wilc1000/wlan.h index b9e7f9222eadde6d736e1d0a403f84ec19399632..65e79371014d9e60755cb0aa38e= 04d351e67bcfb 100644 --- a/drivers/net/wireless/microchip/wilc1000/wlan.h +++ b/drivers/net/wireless/microchip/wilc1000/wlan.h @@ -58,6 +58,7 @@ #define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88) #define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00) #define WILC_INTR_ENABLE WILC_INTR_REG_BASE +#define WILC_INTR_ENABLE_BIT_BASE 27 #define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4) =20 #define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10) @@ -403,6 +404,7 @@ struct wilc_hif_func { void (*disable_interrupt)(struct wilc *nic); int (*hif_reset)(struct wilc *wilc); bool (*hif_is_init)(struct wilc *wilc); + int (*hif_rmw_reg)(struct wilc *wilc, u32 reg, u32 mask, u32 data); }; =20 #define WILC_MAX_CFG_FRAME_SIZE 1468 @@ -472,4 +474,5 @@ int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode,= struct wid *wids, int wilc_wlan_init(struct net_device *dev); int wilc_get_chipid(struct wilc *wilc); int wilc_load_mac_from_nv(struct wilc *wilc); + #endif --=20 2.48.0