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So not reuse sm8650 dp controller driver and will add a new driver patch for qcs8300 mst feature. Modify the corresponding dt-bingding file to compatible with the qcs8300-dp. Signed-off-by: Yongxing Mou --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 359e364d79b20469d41cd8416a55b6a5d5c7d8ce..59075d7f05147f1f477f236a76f= ee6ec5d8c5ad8 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -18,6 +18,7 @@ properties: compatible: oneOf: - enum: + - qcom,qcs8300-dp - qcom,sa8775p-dp - qcom,sc7180-dp - qcom,sc7280-dp @@ -37,10 +38,6 @@ properties: - qcom,sm8450-dp - qcom,sm8550-dp - const: qcom,sm8350-dp - - items: - - enum: - - qcom,qcs8300-dp - - const: qcom,sm8650-dp =20 reg: minItems: 4 --=20 2.34.1 From nobody Thu Dec 18 10:00:33 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0973F20409F; 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Signed-off-by: Yongxing Mou --- .../devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml | 14 ++++++++--= ---- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mds= s.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.ya= ml index eb7f36387f748793ebf662baded4a13a61b3ce39..610742ceebf8ee5e140a409bfeb= 92d9f43085214 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcs8300-mdss.yaml @@ -53,7 +53,6 @@ patternProperties: compatible: items: - const: qcom,qcs8300-dp - - const: qcom,sm8650-dp =20 required: - compatible @@ -164,7 +163,7 @@ examples: }; =20 displayport-controller@af54000 { - compatible =3D "qcom,qcs8300-dp", "qcom,sm8650-dp"; + compatible =3D "qcom,qcs8300-dp"; =20 pinctrl-0 =3D <&dp_hot_plug_det>; pinctrl-names =3D "default"; @@ -181,15 +180,18 @@ examples: <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK>, <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK>; 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Wed, 12 Feb 2025 07:16:00 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51C7Fxxj000691 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Feb 2025 07:15:59 GMT Received: from cse-cd01-lnx.ap.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 11 Feb 2025 23:15:53 -0800 From: Yongxing Mou Date: Wed, 12 Feb 2025 15:12:26 +0800 Subject: [PATCH 3/4] drm/msm/dp: Populate the max_streams for qcs8300 mst controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250212-mst_qcs8300-v1-3-38a8aa08394b@quicinc.com> References: <20250212-mst_qcs8300-v1-0-38a8aa08394b@quicinc.com> In-Reply-To: <20250212-mst_qcs8300-v1-0-38a8aa08394b@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , "Bjorn Andersson" , Konrad Dybcio CC: , , , , , Yongxing Mou X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Previously, the qcs8300 reused the driver of the sm8650's DP controller because they have the same base address, offset, and number of controllers. However, now we need to enable the MST feature for the qcs8300, so we need a new patch The qcs8300 use the same DPU hardware as sa8775p but only have one DPU and dp controller which supports 4 streams MST, but currently we only enable 2 streams MST. It use the intf0 and intf3 to output the data streams of MST0 and MST1. Signed-off-by: Yongxing Mou --- drivers/gpu/drm/msm/dp/dp_display.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index fbbd39d1e53ba3172757105937a528b5c58ea290..fbe4658af1be2ec8c02e8f56766= 7f1dc93ee5537 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -149,6 +149,13 @@ static const unsigned int stream_intf_map_sa_8775p[][D= P_STREAM_MAX] =3D { {} }; =20 +static const struct msm_dp_desc msm_dp_desc_qcs8300[] =3D { + { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, .max_streams =3D 2, + .intf_map =3D stream_intf_map_sa_8775p[MSM_DP_CONTROLLER_0], + }, + {} +}; + static const struct msm_dp_desc msm_dp_desc_sa8775p[] =3D { { .io_start =3D 0x0af54000, .id =3D MSM_DP_CONTROLLER_0, .wide_bus_suppor= ted =3D true, .max_streams =3D 2, .intf_map =3D stream_intf_map_sa_8775p[MSM_DP_CONTROLLER_0], @@ -205,6 +212,7 @@ static const struct msm_dp_desc msm_dp_desc_x1e80100[] = =3D { }; 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Compatile with qcs8300 dp controller driver and populate the stream clock for qcs8300 DP0 controller in MST mode. Signed-off-by: Yongxing Mou --- arch/arm64/boot/dts/qcom/qcs8300.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qc= om/qcs8300.dtsi index e10db7275accf769500abbebf57a6cbbbc4bf167..5166686981617707ba19245723e= 9215a53300392 100644 --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi @@ -2865,12 +2865,13 @@ mdss_dp0_phy: phy@aec2a00 { }; =20 mdss_dp0: displayport-controller@af54000 { - compatible =3D "qcom,qcs8300-dp", "qcom,sm8650-dp"; + compatible =3D "qcom,qcs8300-dp"; =20 reg =3D <0x0 0x0af54000 0x0 0x200>, <0x0 0x0af54200 0x0 0x200>, <0x0 0x0af55000 0x0 0xc00>, - <0x0 0x0af56000 0x0 0x400>; + <0x0 0x0af56000 0x0 0x400>, + <0x0 0x0af57000 0x0 0x400>; =20 interrupt-parent =3D <&mdss>; interrupts =3D <12>; @@ -2884,10 +2885,13 @@ mdss_dp0: displayport-controller@af54000 { "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks =3D <&dispcc MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>, - <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>; + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>, + <&dispcc MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>; assigned-clock-parents =3D <&mdss_dp0_phy 0>, + <&mdss_dp0_phy 1>, <&mdss_dp0_phy 1>; phys =3D <&mdss_dp0_phy>; phy-names =3D "dp"; --=20 2.34.1