From nobody Thu Dec 18 11:46:38 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FE7C1EE013; Wed, 12 Feb 2025 08:25:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739348714; cv=none; b=tDF0nFHicizhqUASOmMTKhDWoFb3AfaURMNWmRAsCtFwtVe072wRKf3D++/WDQJ7X68Ch26Y5h7mzm7mYveIysOXIwsLtj7NaRBrn8xCzgZ6fzbgMd9TSfJZsvH9nNmWF4zr9FHwAEPuA1Ou0tkrPHDSPx/PLz5eZXLmWtviGJg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739348714; c=relaxed/simple; bh=UxLLrFR3unDkQEVXT9keu7/Y/BnzW500e0pY1YknrSw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=TcRUHQV44O7qE0s+MqlKyVE735jfwkzIrWwwOu4eqn7qelNCd9oHWZ06mLaOxf5+iGvzKo6gMwL9SAJsBhlYZuw46tUQ6BqfYZXrLnvMI7D5bPRo3ASJPvfWrP9m6heecKs2Rk0MSz33ykxHxWruRYh7+6PQpxjlLk8bnnjSvzM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com; spf=pass smtp.mailfrom=quicinc.com; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b=MYDLgWlD; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=quicinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=quicinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=quicinc.com header.i=@quicinc.com header.b="MYDLgWlD" Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51C0oYeI030181; Wed, 12 Feb 2025 08:25:09 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= 4+MbO4I6cRAV6UyKT51mOFpjDAxPBVOlCZ8ub22QxvI=; b=MYDLgWlD8AHtOUSQ gkOXzM8RLv2eMnZ5GcwVnFr8at6sPnSqb9LcvMDY6/gifokQUE+jKMxdURv9OH/o f39aNULAGiXEd3V8d7EG3nUrTC3/PdsGVFv4haM5P6XH/QKHPemtbv1WDwNJNMDF XXSoMDVxkFPbww7mJzkFzYcPpCSzjthaUlJdkhv1RRIfRZN1+HFzKJrKgQhsAGFi 4zHlC4RzgbrjrD1xVfs/mKZG6UKuU5swuj4a63UNk0BuctY5ZJocu3RNakHUuqY6 QZxsPJBSTOhmWqcRyKLrj5eJz5knrso8nBDNsSHBXoCe8G9k+ntuXAL+d34CbiRE VBScug== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 44qxg9m7dy-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Feb 2025 08:25:09 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 51C8P8Od011271 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Feb 2025 08:25:08 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Wed, 12 Feb 2025 00:23:05 -0800 From: Taniya Das Date: Wed, 12 Feb 2025 13:52:20 +0530 Subject: [PATCH v3 2/4] clk: qcom: lpassaudiocc-sc7280: Add support for LPASS resets for QCM6490 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250212-lpass_qcm6490_resets-v3-2-0b1cfb35b38e@quicinc.com> References: <20250212-lpass_qcm6490_resets-v3-0-0b1cfb35b38e@quicinc.com> In-Reply-To: <20250212-lpass_qcm6490_resets-v3-0-0b1cfb35b38e@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: IitNfqJQCIE0OPCcJirzuOhfYsQkrB9P X-Proofpoint-GUID: IitNfqJQCIE0OPCcJirzuOhfYsQkrB9P X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-12_02,2025-02-11_01,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 mlxscore=0 priorityscore=1501 malwarescore=0 spamscore=0 impostorscore=0 mlxlogscore=880 lowpriorityscore=0 phishscore=0 clxscore=1015 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502120064 On the QCM6490 boards the LPASS firmware controls the complete clock controller functionalities. But the LPASS resets are required to be controlled from the high level OS. The Audio SW driver should be able to assert/deassert the audio resets as required. Thus in clock driver add support for the resets. Signed-off-by: Taniya Das --- drivers/clk/qcom/lpassaudiocc-sc7280.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpas= saudiocc-sc7280.c index 45e7264770866f929a3f4663c477330f0bf7aa84..b6439308926371891cc5f9a5e0d= 4e8393641560d 100644 --- a/drivers/clk/qcom/lpassaudiocc-sc7280.c +++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 #include @@ -713,14 +714,24 @@ static const struct qcom_reset_map lpass_audio_cc_sc7= 280_resets[] =3D { [LPASS_AUDIO_SWR_WSA_CGCR] =3D { 0xb0, 1 }, }; =20 +static const struct regmap_config lpass_audio_cc_sc7280_reset_regmap_confi= g =3D { + .name =3D "lpassaudio_cc_reset", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0xc8, +}; + static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc =3D { - .config =3D &lpass_audio_cc_sc7280_regmap_config, + .config =3D &lpass_audio_cc_sc7280_reset_regmap_config, .resets =3D lpass_audio_cc_sc7280_resets, .num_resets =3D ARRAY_SIZE(lpass_audio_cc_sc7280_resets), }; =20 static const struct of_device_id lpass_audio_cc_sc7280_match_table[] =3D { - { .compatible =3D "qcom,sc7280-lpassaudiocc" }, + { .compatible =3D "qcom,qcm6490-lpassaudiocc", .data =3D &lpass_audio_cc_= reset_sc7280_desc }, + { .compatible =3D "qcom,sc7280-lpassaudiocc", .data =3D &lpass_audio_cc_s= c7280_desc }, { } }; MODULE_DEVICE_TABLE(of, lpass_audio_cc_sc7280_match_table); @@ -752,13 +763,17 @@ static int lpass_audio_cc_sc7280_probe(struct platfor= m_device *pdev) struct regmap *regmap; int ret; =20 + desc =3D device_get_match_data(&pdev->dev); + + if (desc->num_resets) + return qcom_cc_probe_by_index(pdev, 1, desc); + ret =3D lpass_audio_setup_runtime_pm(pdev); if (ret) return ret; =20 lpass_audio_cc_sc7280_regmap_config.name =3D "lpassaudio_cc"; lpass_audio_cc_sc7280_regmap_config.max_register =3D 0x2f000; - desc =3D &lpass_audio_cc_sc7280_desc; =20 regmap =3D qcom_cc_map(pdev, desc); if (IS_ERR(regmap)) { @@ -772,7 +787,7 @@ static int lpass_audio_cc_sc7280_probe(struct platform_= device *pdev) regmap_write(regmap, 0x4, 0x3b); regmap_write(regmap, 0x8, 0xff05); =20 - ret =3D qcom_cc_really_probe(&pdev->dev, &lpass_audio_cc_sc7280_desc, reg= map); + ret =3D qcom_cc_really_probe(&pdev->dev, desc, regmap); if (ret) { dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n"); goto exit; --=20 2.45.2