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a=openpgp; fpr=4B5278785C97ACF79C3C688301CA08B7A6C50824 Support a per-implementation number of counters to allow adding support for implementations with less counters. Signed-off-by: Nick Chan --- drivers/perf/apple_m1_cpu_pmu.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 1bf7ce5c09846c699d66bdfcca129f418a9dad9e..ae91848bcd828be197fc21bb219= 5f3e2460edc65 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -19,6 +19,7 @@ #include =20 #define M1_PMU_NR_COUNTERS 10 +#define APPLE_PMU_MAX_NR_COUNTERS 10 =20 #define M1_PMU_CFG_EVENT GENMASK(7, 0) =20 @@ -431,7 +432,7 @@ static irqreturn_t m1_pmu_handle_irq(struct arm_pmu *cp= u_pmu) =20 regs =3D get_irq_regs(); =20 - for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, cpu_pmu->cntr_mask, APPLE_PMU_MAX_NR_COUNTERS) { struct perf_event *event =3D cpuc->events[idx]; struct perf_sample_data data; =20 @@ -479,7 +480,7 @@ static int apple_pmu_get_event_idx(struct pmu_hw_events= *cpuc, * counting on the PMU at any given time, and by placing the * most constraining events first. */ - for_each_set_bit(idx, &affinity, M1_PMU_NR_COUNTERS) { + for_each_set_bit(idx, &affinity, APPLE_PMU_MAX_NR_COUNTERS) { if (!test_and_set_bit(idx, cpuc->used_mask)) return idx; } @@ -554,13 +555,13 @@ static int m2_pmu_map_event(struct perf_event *event) return apple_pmu_map_event_63(event, &m1_pmu_perf_map); } =20 -static void m1_pmu_reset(void *info) +static void apple_pmu_reset_common(void *info, u32 counters) { int i; =20 __m1_pmu_set_mode(PMCR0_IMODE_OFF); =20 - for (i =3D 0; i < M1_PMU_NR_COUNTERS; i++) { + for (i =3D 0; i < counters; i++) { m1_pmu_disable_counter(i); m1_pmu_disable_counter_interrupt(i); m1_pmu_write_hw_counter(0, i); @@ -569,6 +570,11 @@ static void m1_pmu_reset(void *info) isb(); } =20 +static void m1_pmu_reset(void *info) +{ + apple_pmu_reset_common(info, M1_PMU_NR_COUNTERS); +} + static int m1_pmu_set_event_filter(struct hw_perf_event *event, struct perf_event_attr *attr) { @@ -588,7 +594,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event= *event, return 0; } =20 -static int apple_pmu_init_common(struct arm_pmu *cpu_pmu, u32 flags) +static int apple_pmu_init_common(struct arm_pmu *cpu_pmu, u32 flags, u32 c= ounters) { cpu_pmu->handle_irq =3D m1_pmu_handle_irq; cpu_pmu->enable =3D m1_pmu_enable_event; @@ -598,10 +604,9 @@ static int apple_pmu_init_common(struct arm_pmu *cpu_p= mu, u32 flags) cpu_pmu->clear_event_idx =3D m1_pmu_clear_event_idx; cpu_pmu->start =3D m1_pmu_start; cpu_pmu->stop =3D m1_pmu_stop; - cpu_pmu->reset =3D m1_pmu_reset; cpu_pmu->set_event_filter =3D m1_pmu_set_event_filter; =20 - bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS); + bitmap_set(cpu_pmu->cntr_mask, 0, counters); cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =3D &m1_pmu_events_attr_gr= oup; cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =3D &m1_pmu_format_attr_g= roup; return 0; @@ -613,7 +618,8 @@ static int m1_pmu_ice_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_icestorm_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; - return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTER= S); } =20 static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) @@ -621,7 +627,8 @@ static int m1_pmu_fire_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_firestorm_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m1_pmu_map_event; - return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_47BIT, M1_PMU_NR_COUNTER= S); } =20 static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pmu) @@ -629,7 +636,8 @@ static int m2_pmu_avalanche_init(struct arm_pmu *cpu_pm= u) cpu_pmu->name =3D "apple_avalanche_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; - return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_63BIT, M1_PMU_NR_COUNTER= S); } =20 static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) @@ -637,7 +645,8 @@ static int m2_pmu_blizzard_init(struct arm_pmu *cpu_pmu) cpu_pmu->name =3D "apple_blizzard_pmu"; cpu_pmu->get_event_idx =3D m1_pmu_get_event_idx; cpu_pmu->map_event =3D m2_pmu_map_event; - return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_63BIT); + cpu_pmu->reset =3D m1_pmu_reset; + return apple_pmu_init_common(cpu_pmu, ARMPMU_EVT_63BIT, M1_PMU_NR_COUNTER= S); } =20 static const struct of_device_id m1_pmu_of_device_ids[] =3D { --=20 2.48.1