From nobody Thu Dec 18 10:01:22 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4B6501FAC25; Tue, 11 Feb 2025 11:34:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739273677; cv=none; b=Rtq3YDfHM0cvyjyWTXG27XCmFA1CgsadSL5sZMl/KBSABSdySZStLusiJSzt4UdSYX0pmGEG9Ctzxy6l49KnDbsB5FtL9n9cWLkPB0uDnP8leJ9I7ClOfb9Mbo+BGW1V7RWw6zfCef6v6E4oBXs1CoFlmrBSj0tXKBOw2XgLUR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739273677; c=relaxed/simple; bh=yf/jrW+B4sKuguE3GNNUyEcYjhTmkvt2TLbnYCDo18c=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LBHyN8O+aQj+wCE/ZfbaFmnh6S5z5ZW6y8629lkc0Ufa0b5d5BtA445hfh/5o2MCfRYL48+eX/wW3gjMRUzehcPebCO8AqifiP4iWj3GWMPkBsNbXvQ1uJ/VyIaWRpnI3Wg6QeHdOokH0FUDWtnva47zI3cv+EP6sv6QtBWOhb8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=lIXMUbQ9; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="lIXMUbQ9" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1739273673; bh=yf/jrW+B4sKuguE3GNNUyEcYjhTmkvt2TLbnYCDo18c=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lIXMUbQ9VxE96j7ElNQR/l5cIz/huaIY7DhEDVLXvNXOplnWJV4xPaFYuU/uW99br wR1ifEXpAn6ArHyBq1Fp7wpVXUq0IQZystOBHWnVMXP8eA3uDKICxD423mES3yJclU dedrB4hXcG5Q6weNBfsWwtiQexScuhloE/zJz+9vAj2D1DMtKOGLlFgU84NI700qIK TcGZz/5pCfhL4KMyA7xyPwMdIuC1+nDn66rRQkHsx3rLdwiwZm4CEKbIxasr/fOvig b4uz2tDwVwFLogM837INFvYZV58o5OyeAORoBs2dfvjg3LtXXMdE+lyV6g77tP1oph q6nvfSMmIHdTw== Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9485E17E1553; Tue, 11 Feb 2025 12:34:32 +0100 (CET) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: p.zabel@pengutronix.de, airlied@gmail.com, simona@ffwll.ch, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, ck.hu@mediatek.com, jitao.shi@mediatek.com, jie.qiu@mediatek.com, junzhi.zhao@mediatek.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com, dmitry.baryshkov@linaro.org, lewis.liao@mediatek.com, ives.chenjh@mediatek.com, tommyyl.chen@mediatek.com, jason-jh.lin@mediatek.com Subject: [PATCH v6 09/42] drm/mediatek: mtk_dpi: Explicitly manage TVD clock in power on/off Date: Tue, 11 Feb 2025 12:33:36 +0100 Message-ID: <20250211113409.1517534-10-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250211113409.1517534-1-angelogioacchino.delregno@collabora.com> References: <20250211113409.1517534-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In preparation for adding support for MT8195's HDMI reserved DPI, add calls to clk_prepare_enable() / clk_disable_unprepare() for the TVD clock: in this particular case, the aforementioned clock is not (and cannot be) parented to neither pixel or engine clocks hence it won't get enabled automatically by the clock framework. Please note that on all of the currently supported MediaTek platforms, the TVD clock is always a parent of either pixel or engine clocks, and this means that the common clock framework is already enabling this clock before the children. On such platforms, this commit will only increase the refcount of the TVD clock without any functional change. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: CK Hu --- drivers/gpu/drm/mediatek/mtk_dpi.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/= mtk_dpi.c index 5c15c8935916..67504eb874d2 100644 --- a/drivers/gpu/drm/mediatek/mtk_dpi.c +++ b/drivers/gpu/drm/mediatek/mtk_dpi.c @@ -501,6 +501,7 @@ static void mtk_dpi_power_off(struct mtk_dpi *dpi) =20 mtk_dpi_disable(dpi); clk_disable_unprepare(dpi->pixel_clk); + clk_disable_unprepare(dpi->tvd_clk); clk_disable_unprepare(dpi->engine_clk); } =20 @@ -517,6 +518,12 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) goto err_refcount; } =20 + ret =3D clk_prepare_enable(dpi->tvd_clk); + if (ret) { + dev_err(dpi->dev, "Failed to enable tvd pll: %d\n", ret); + goto err_engine; + } + ret =3D clk_prepare_enable(dpi->pixel_clk); if (ret) { dev_err(dpi->dev, "Failed to enable pixel clock: %d\n", ret); @@ -526,6 +533,8 @@ static int mtk_dpi_power_on(struct mtk_dpi *dpi) return 0; =20 err_pixel: + clk_disable_unprepare(dpi->tvd_clk); +err_engine: clk_disable_unprepare(dpi->engine_clk); err_refcount: dpi->refcount--; --=20 2.48.1