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([145.224.65.3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd02e2a90sm10456047f8f.98.2025.02.11.02.40.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 02:40:30 -0800 (PST) From: James Clark To: lcherian@marvell.com, coresight@lists.linaro.org Cc: James Clark , Suzuki K Poulose , Mike Leach , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 1/7] coresight: Rename coresight_{set,clear}_claim_tags() Date: Tue, 11 Feb 2025 10:39:37 +0000 Message-Id: <20250211103945.967495-2-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211103945.967495-1-james.clark@linaro.org> References: <20250211103945.967495-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These look like they set the whole tags register as one value, but they only set and clear the self hosted bit using a SET/CLR bits mechanism. Rename the functions to reflect this better. Signed-off-by: James Clark Reviewed-by: Leo Yan --- drivers/hwtracing/coresight/coresight-core.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 0a9380350fb5..523dbb381f90 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -142,14 +142,14 @@ static inline bool coresight_is_claimed_any(struct co= resight_device *csdev) return coresight_read_claim_tags(csdev) !=3D 0; } =20 -static inline void coresight_set_claim_tags(struct coresight_device *csdev) +static inline void coresight_set_self_claim_tag(struct coresight_device *c= sdev) { csdev_access_relaxed_write32(&csdev->access, CORESIGHT_CLAIM_SELF_HOSTED, CORESIGHT_CLAIMSET); isb(); } =20 -static inline void coresight_clear_claim_tags(struct coresight_device *csd= ev) +static inline void coresight_clear_self_claim_tag(struct coresight_device = *csdev) { csdev_access_relaxed_write32(&csdev->access, CORESIGHT_CLAIM_SELF_HOSTED, CORESIGHT_CLAIMCLR); @@ -174,11 +174,11 @@ int coresight_claim_device_unlocked(struct coresight_= device *csdev) if (coresight_is_claimed_any(csdev)) return -EBUSY; =20 - coresight_set_claim_tags(csdev); + coresight_set_self_claim_tag(csdev); if (coresight_is_claimed_self_hosted(csdev)) return 0; - /* There was a race setting the tags, clean up and fail */ - coresight_clear_claim_tags(csdev); + /* There was a race setting the tag, clean up and fail */ + coresight_clear_self_claim_tag(csdev); return -EBUSY; } EXPORT_SYMBOL_GPL(coresight_claim_device_unlocked); @@ -199,7 +199,7 @@ int coresight_claim_device(struct coresight_device *csd= ev) EXPORT_SYMBOL_GPL(coresight_claim_device); =20 /* - * coresight_disclaim_device_unlocked : Clear the claim tags for the devic= e. + * coresight_disclaim_device_unlocked : Clear the claim tag for the device. * Called with CS_UNLOCKed for the component. */ void coresight_disclaim_device_unlocked(struct coresight_device *csdev) @@ -209,7 +209,7 @@ void coresight_disclaim_device_unlocked(struct coresigh= t_device *csdev) return; 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([145.224.65.3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd02e2a90sm10456047f8f.98.2025.02.11.02.40.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 02:40:33 -0800 (PST) From: James Clark To: lcherian@marvell.com, coresight@lists.linaro.org Cc: James Clark , Suzuki K Poulose , Mike Leach , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 2/7] coresight: Convert disclaim functions to take a struct cs_access Date: Tue, 11 Feb 2025 10:39:38 +0000 Message-Id: <20250211103945.967495-3-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211103945.967495-1-james.clark@linaro.org> References: <20250211103945.967495-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The self hosted claim tag will be reset on device probe in a later commit. We'll want to do this before coresight_register() is called so won't have a coresight_device and have to use cs_access instead. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-catu.c | 2 +- drivers/hwtracing/coresight/coresight-core.c | 45 ++++++++----------- .../hwtracing/coresight/coresight-cti-core.c | 6 +-- drivers/hwtracing/coresight/coresight-etb10.c | 2 +- .../coresight/coresight-etm3x-core.c | 4 +- .../coresight/coresight-etm4x-core.c | 2 +- .../hwtracing/coresight/coresight-funnel.c | 2 +- .../coresight/coresight-replicator.c | 4 +- .../hwtracing/coresight/coresight-tmc-etf.c | 8 ++-- .../hwtracing/coresight/coresight-tmc-etr.c | 4 +- include/linux/coresight.h | 4 +- 11 files changed, 38 insertions(+), 45 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtraci= ng/coresight/coresight-catu.c index 275cc0d9f505..d9259c0b6e64 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -474,7 +474,7 @@ static int catu_disable_hw(struct catu_drvdata *drvdata) struct coresight_device *csdev =3D drvdata->csdev; =20 catu_write_control(drvdata, 0); - coresight_disclaim_device_unlocked(csdev); + coresight_disclaim_device_unlocked(&csdev->access); if (catu_wait_for_ready(drvdata)) { dev_info(dev, "Timeout while waiting for READY\n"); rc =3D -EAGAIN; diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 523dbb381f90..a669872b4118 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -127,31 +127,31 @@ coresight_find_out_connection(struct coresight_device= *csdev, return ERR_PTR(-ENODEV); } =20 -static inline u32 coresight_read_claim_tags(struct coresight_device *csdev) +static inline u32 coresight_read_claim_tags(struct csdev_access *csa) { - return csdev_access_relaxed_read32(&csdev->access, CORESIGHT_CLAIMCLR); + return csdev_access_relaxed_read32(csa, CORESIGHT_CLAIMCLR); } =20 -static inline bool coresight_is_claimed_self_hosted(struct coresight_devic= e *csdev) +static inline bool coresight_is_claimed_self_hosted(struct csdev_access *c= sa) { - return coresight_read_claim_tags(csdev) =3D=3D CORESIGHT_CLAIM_SELF_HOSTE= D; + return coresight_read_claim_tags(csa) =3D=3D CORESIGHT_CLAIM_SELF_HOSTED; } =20 static inline bool coresight_is_claimed_any(struct coresight_device *csdev) { - return coresight_read_claim_tags(csdev) !=3D 0; + return coresight_read_claim_tags(&csdev->access) !=3D 0; } =20 -static inline void coresight_set_self_claim_tag(struct coresight_device *c= sdev) +static inline void coresight_set_self_claim_tag(struct csdev_access *csa) { - csdev_access_relaxed_write32(&csdev->access, CORESIGHT_CLAIM_SELF_HOSTED, + csdev_access_relaxed_write32(csa, CORESIGHT_CLAIM_SELF_HOSTED, CORESIGHT_CLAIMSET); isb(); } =20 -static inline void coresight_clear_self_claim_tag(struct coresight_device = *csdev) +static inline void coresight_clear_self_claim_tag(struct csdev_access *csa) { - csdev_access_relaxed_write32(&csdev->access, CORESIGHT_CLAIM_SELF_HOSTED, + csdev_access_relaxed_write32(csa, CORESIGHT_CLAIM_SELF_HOSTED, CORESIGHT_CLAIMCLR); isb(); } @@ -174,11 +174,11 @@ int coresight_claim_device_unlocked(struct coresight_= device *csdev) if (coresight_is_claimed_any(csdev)) return -EBUSY; =20 - coresight_set_self_claim_tag(csdev); - if (coresight_is_claimed_self_hosted(csdev)) + coresight_set_self_claim_tag(&csdev->access); + if (coresight_is_claimed_self_hosted(&csdev->access)) return 0; /* There was a race setting the tag, clean up and fail */ - coresight_clear_self_claim_tag(csdev); + coresight_clear_self_claim_tag(&csdev->access); return -EBUSY; } EXPORT_SYMBOL_GPL(coresight_claim_device_unlocked); @@ -202,14 +202,10 @@ EXPORT_SYMBOL_GPL(coresight_claim_device); * coresight_disclaim_device_unlocked : Clear the claim tag for the device. * Called with CS_UNLOCKed for the component. */ -void coresight_disclaim_device_unlocked(struct coresight_device *csdev) +void coresight_disclaim_device_unlocked(struct csdev_access *csa) { - - if (WARN_ON(!csdev)) - return; - - if (coresight_is_claimed_self_hosted(csdev)) - coresight_clear_self_claim_tag(csdev); + if (coresight_is_claimed_self_hosted(csa)) + coresight_clear_self_claim_tag(csa); else /* * The external agent may have not honoured our claim @@ -220,14 +216,11 @@ void coresight_disclaim_device_unlocked(struct coresi= ght_device *csdev) } EXPORT_SYMBOL_GPL(coresight_disclaim_device_unlocked); =20 -void coresight_disclaim_device(struct coresight_device *csdev) +void coresight_disclaim_device(struct csdev_access *csa) { - if (WARN_ON(!csdev)) - return; - - CS_UNLOCK(csdev->access.base); - coresight_disclaim_device_unlocked(csdev); - CS_LOCK(csdev->access.base); + CS_UNLOCK(csa->base); + coresight_disclaim_device_unlocked(csa); + CS_LOCK(csa->base); } EXPORT_SYMBOL_GPL(coresight_disclaim_device); =20 diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index d2b5a5718c29..073f67a41af9 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -175,7 +175,7 @@ static int cti_disable_hw(struct cti_drvdata *drvdata) writel_relaxed(0, drvdata->base + CTICONTROL); config->hw_enabled =3D false; =20 - coresight_disclaim_device_unlocked(csdev); + coresight_disclaim_device_unlocked(&csdev->access); CS_LOCK(drvdata->base); spin_unlock(&drvdata->spinlock); return ret; @@ -683,7 +683,7 @@ static int cti_cpu_pm_notify(struct notifier_block *nb,= unsigned long cmd, /* CTI regs all static - we have a copy & nothing to save */ drvdata->config.hw_powered =3D false; if (drvdata->config.hw_enabled) - coresight_disclaim_device(csdev); + coresight_disclaim_device(&csdev->access); break; =20 case CPU_PM_ENTER_FAILED: @@ -746,7 +746,7 @@ static int cti_dying_cpu(unsigned int cpu) spin_lock(&drvdata->spinlock); drvdata->config.hw_powered =3D false; if (drvdata->config.hw_enabled) - coresight_disclaim_device(drvdata->csdev); + coresight_disclaim_device(&drvdata->csdev->access); spin_unlock(&drvdata->spinlock); return 0; } diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtrac= ing/coresight/coresight-etb10.c index aea9ac9c4bd0..d8bc3e776c88 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -344,7 +344,7 @@ static void etb_disable_hw(struct etb_drvdata *drvdata) { __etb_disable_hw(drvdata); etb_dump_hw(drvdata); - coresight_disclaim_device(drvdata->csdev); + coresight_disclaim_device(&drvdata->csdev->access); } =20 static int etb_disable(struct coresight_device *csdev) diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index c103f4c70f5d..509f53b69e42 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -599,7 +599,7 @@ static void etm_disable_hw(void *info) config->cntr_val[i] =3D etm_readl(drvdata, ETMCNTVRn(i)); =20 etm_set_pwrdwn(drvdata); - coresight_disclaim_device_unlocked(csdev); + coresight_disclaim_device_unlocked(&csdev->access); =20 CS_LOCK(drvdata->base); =20 @@ -624,7 +624,7 @@ static void etm_disable_perf(struct coresight_device *c= sdev) * power down the tracer. */ etm_set_pwrdwn(drvdata); - coresight_disclaim_device_unlocked(csdev); + coresight_disclaim_device_unlocked(&csdev->access); =20 CS_LOCK(drvdata->base); =20 diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index dd8c74f893db..45b30a4b3eba 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -922,7 +922,7 @@ static void etm4_disable_hw(void *info) etm4x_relaxed_read32(csa, TRCCNTVRn(i)); } =20 - coresight_disclaim_device_unlocked(csdev); + coresight_disclaim_device_unlocked(&csdev->access); etm4_cs_lock(drvdata, csa); =20 dev_dbg(&drvdata->csdev->dev, diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtra= cing/coresight/coresight-funnel.c index 8faf51469bb8..e986922d555b 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -116,7 +116,7 @@ static void dynamic_funnel_disable_hw(struct funnel_drv= data *drvdata, =20 /* Disclaim the device if none of the slaves are now active */ if (!(functl & FUNNEL_ENSx_MASK)) - coresight_disclaim_device_unlocked(csdev); + coresight_disclaim_device_unlocked(&csdev->access); =20 CS_LOCK(drvdata->base); } diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index a1181c9048c0..5d42a9a8c460 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -54,7 +54,7 @@ static void dynamic_replicator_reset(struct replicator_dr= vdata *drvdata) if (!coresight_claim_device_unlocked(csdev)) { writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER0); writel_relaxed(0xff, drvdata->base + REPLICATOR_IDFILTER1); - coresight_disclaim_device_unlocked(csdev); + coresight_disclaim_device_unlocked(&csdev->access); } =20 CS_LOCK(drvdata->base); @@ -167,7 +167,7 @@ static void dynamic_replicator_disable(struct replicato= r_drvdata *drvdata, =20 if ((readl_relaxed(drvdata->base + REPLICATOR_IDFILTER0) =3D=3D 0xff) && (readl_relaxed(drvdata->base + REPLICATOR_IDFILTER1) =3D=3D 0xff)) - coresight_disclaim_device_unlocked(csdev); + coresight_disclaim_device_unlocked(&csdev->access); CS_LOCK(drvdata->base); } =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtr= acing/coresight/coresight-tmc-etf.c index d4f641cd9de6..1e4d874a8448 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etf.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c @@ -53,7 +53,7 @@ static int tmc_etb_enable_hw(struct tmc_drvdata *drvdata) =20 rc =3D __tmc_etb_enable_hw(drvdata); if (rc) - coresight_disclaim_device(drvdata->csdev); + coresight_disclaim_device(&drvdata->csdev->access); return rc; } =20 @@ -99,7 +99,7 @@ static void __tmc_etb_disable_hw(struct tmc_drvdata *drvd= ata) static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata) { __tmc_etb_disable_hw(drvdata); - coresight_disclaim_device(drvdata->csdev); + coresight_disclaim_device(&drvdata->csdev->access); } =20 static int __tmc_etf_enable_hw(struct tmc_drvdata *drvdata) @@ -136,7 +136,7 @@ static int tmc_etf_enable_hw(struct tmc_drvdata *drvdat= a) =20 rc =3D __tmc_etf_enable_hw(drvdata); if (rc) - coresight_disclaim_device(drvdata->csdev); + coresight_disclaim_device(&drvdata->csdev->access); return rc; } =20 @@ -148,7 +148,7 @@ static void tmc_etf_disable_hw(struct tmc_drvdata *drvd= ata) =20 tmc_flush_and_stop(drvdata); tmc_disable_hw(drvdata); - coresight_disclaim_device_unlocked(csdev); + coresight_disclaim_device_unlocked(&csdev->access); CS_LOCK(drvdata->base); } =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index a48bb85d0e7f..7ba4f79191de 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -1066,7 +1066,7 @@ static int tmc_etr_enable_hw(struct tmc_drvdata *drvd= ata, rc =3D __tmc_etr_enable_hw(drvdata); if (rc) { drvdata->etr_buf =3D NULL; - coresight_disclaim_device(drvdata->csdev); + coresight_disclaim_device(&drvdata->csdev->access); } } =20 @@ -1156,7 +1156,7 @@ static void __tmc_etr_disable_hw(struct tmc_drvdata *= drvdata) void tmc_etr_disable_hw(struct tmc_drvdata *drvdata) { __tmc_etr_disable_hw(drvdata); - coresight_disclaim_device(drvdata->csdev); + coresight_disclaim_device(&drvdata->csdev->access); /* Reset the ETR buf used by hardware */ drvdata->etr_buf =3D NULL; } diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 17276965ff1d..937931d107e0 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -653,8 +653,8 @@ extern int coresight_timeout(struct csdev_access *csa, = u32 offset, extern int coresight_claim_device(struct coresight_device *csdev); extern int coresight_claim_device_unlocked(struct coresight_device *csdev); =20 -extern void coresight_disclaim_device(struct coresight_device *csdev); -extern void coresight_disclaim_device_unlocked(struct coresight_device *cs= dev); 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([145.224.65.3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd02e2a90sm10456047f8f.98.2025.02.11.02.40.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 02:40:35 -0800 (PST) From: James Clark To: lcherian@marvell.com, coresight@lists.linaro.org Cc: James Clark , Suzuki K Poulose , Mike Leach , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 3/7] coresight: Only check bottom two claim bits Date: Tue, 11 Feb 2025 10:39:39 +0000 Message-Id: <20250211103945.967495-4-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211103945.967495-1-james.clark@linaro.org> References: <20250211103945.967495-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The use of the whole register and =3D=3D could break the claim mechanism if any of the other bits are used in the future. The referenced doc "PSCI - ARM DEN 0022D" also says to only read and clear the bottom two bits. Use FIELD_GET() to extract only the relevant part. Signed-off-by: James Clark Reviewed-by: Leo Yan --- drivers/hwtracing/coresight/coresight-core.c | 3 ++- drivers/hwtracing/coresight/coresight-priv.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index a669872b4118..7b53165c93af 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -129,7 +129,8 @@ coresight_find_out_connection(struct coresight_device *= csdev, =20 static inline u32 coresight_read_claim_tags(struct csdev_access *csa) { - return csdev_access_relaxed_read32(csa, CORESIGHT_CLAIMCLR); + return FIELD_GET(CORESIGHT_CLAIM_MASK, + csdev_access_relaxed_read32(csa, CORESIGHT_CLAIMCLR)); } =20 static inline bool coresight_is_claimed_self_hosted(struct csdev_access *c= sa) diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index 05f891ca6b5c..cc7ff1e36ef4 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -35,6 +35,7 @@ extern const struct device_type coresight_dev_type[]; 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([145.224.65.3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd02e2a90sm10456047f8f.98.2025.02.11.02.40.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 02:40:38 -0800 (PST) From: James Clark To: lcherian@marvell.com, coresight@lists.linaro.org Cc: James Clark , Suzuki K Poulose , Mike Leach , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 4/7] coresight: Add claim tag warnings and debug messages Date: Tue, 11 Feb 2025 10:39:40 +0000 Message-Id: <20250211103945.967495-5-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211103945.967495-1-james.clark@linaro.org> References: <20250211103945.967495-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a dev_dbg() message so that external debugger conflicts are more visible. There are multiple reasons for -EBUSY so a message for this particular one could be helpful. Add errors for and enumerate all the other cases that are impossible. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-core.c | 48 ++++++++++++-------- drivers/hwtracing/coresight/coresight-priv.h | 5 +- 2 files changed, 34 insertions(+), 19 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 7b53165c93af..7fe5d5d432c4 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -133,16 +133,6 @@ static inline u32 coresight_read_claim_tags(struct csd= ev_access *csa) csdev_access_relaxed_read32(csa, CORESIGHT_CLAIMCLR)); } =20 -static inline bool coresight_is_claimed_self_hosted(struct csdev_access *c= sa) -{ - return coresight_read_claim_tags(csa) =3D=3D CORESIGHT_CLAIM_SELF_HOSTED; -} - -static inline bool coresight_is_claimed_any(struct coresight_device *csdev) -{ - return coresight_read_claim_tags(&csdev->access) !=3D 0; -} - static inline void coresight_set_self_claim_tag(struct csdev_access *csa) { csdev_access_relaxed_write32(csa, CORESIGHT_CLAIM_SELF_HOSTED, @@ -169,18 +159,40 @@ static inline void coresight_clear_self_claim_tag(str= uct csdev_access *csa) */ int coresight_claim_device_unlocked(struct coresight_device *csdev) { + int tag; + struct csdev_access *csa; + if (WARN_ON(!csdev)) return -EINVAL; =20 - if (coresight_is_claimed_any(csdev)) + csa =3D &csdev->access; + tag =3D coresight_read_claim_tags(csa); + + switch (tag) { + case CORESIGHT_CLAIM_FREE: + coresight_set_self_claim_tag(csa); + if (coresight_read_claim_tags(csa) =3D=3D CORESIGHT_CLAIM_SELF_HOSTED) + return 0; + + /* There was a race setting the tag, clean up and fail */ + coresight_clear_self_claim_tag(csa); return -EBUSY; =20 - coresight_set_self_claim_tag(&csdev->access); - if (coresight_is_claimed_self_hosted(&csdev->access)) - return 0; - /* There was a race setting the tag, clean up and fail */ - coresight_clear_self_claim_tag(&csdev->access); - return -EBUSY; + case CORESIGHT_CLAIM_EXTERNAL: + /* External debug is an expected state, so log and report BUSY */ + dev_dbg(&csdev->dev, "Busy: Claimed by external debugger"); + return -EBUSY; + + default: + case CORESIGHT_CLAIM_SELF_HOSTED: + case CORESIGHT_CLAIM_INVALID: + /* + * Warn here because we clear a lingering self hosted tag + * on probe, so other tag combinations are impossible. + */ + dev_err_once(&csdev->dev, "Invalid claim tag state: %x", tag); + return -EBUSY; + } } EXPORT_SYMBOL_GPL(coresight_claim_device_unlocked); =20 @@ -205,7 +217,7 @@ EXPORT_SYMBOL_GPL(coresight_claim_device); */ void coresight_disclaim_device_unlocked(struct csdev_access *csa) { - if (coresight_is_claimed_self_hosted(csa)) + if (coresight_read_claim_tags(csa) =3D=3D CORESIGHT_CLAIM_SELF_HOSTED) coresight_clear_self_claim_tag(csa); else /* diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index cc7ff1e36ef4..a83113225797 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -36,7 +36,10 @@ extern const struct device_type coresight_dev_type[]; * See PSCI - ARM DEN 0022D, Section: 6.8.1 Debug and Trace save and resto= re. */ #define CORESIGHT_CLAIM_MASK GENMASK(1, 0) -#define CORESIGHT_CLAIM_SELF_HOSTED BIT(1) +#define CORESIGHT_CLAIM_FREE 0 +#define CORESIGHT_CLAIM_EXTERNAL 1 +#define CORESIGHT_CLAIM_SELF_HOSTED 2 +#define CORESIGHT_CLAIM_INVALID 3 =20 #define TIMEOUT_US 100 #define BMVAL(val, lsb, msb) ((val & GENMASK(msb, lsb)) >> lsb) --=20 2.34.1 From nobody Thu Dec 18 10:25:57 2025 Received: from mail-wm1-f44.google.com (mail-wm1-f44.google.com [209.85.128.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A46A1F7092 for ; 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([145.224.65.3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd02e2a90sm10456047f8f.98.2025.02.11.02.40.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 02:40:41 -0800 (PST) From: James Clark To: lcherian@marvell.com, coresight@lists.linaro.org Cc: James Clark , Suzuki K Poulose , Mike Leach , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 5/7] coresight: Clear self hosted claim tag on probe Date: Tue, 11 Feb 2025 10:39:41 +0000 Message-Id: <20250211103945.967495-6-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211103945.967495-1-james.clark@linaro.org> References: <20250211103945.967495-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This can be left behind from a crashed kernel after a kexec so clear it when probing each device. Similarly to coresight_disclaim_device_unlocked(), only clear it if it's already set to avoid races with an external debugger. We need a csdev_access struct in etm_init_arch_data() so just replace the iomem pointer with a full csdev_access struct. This means all usages need to be updated to go through csa->base. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-catu.c | 1 + drivers/hwtracing/coresight/coresight-core.c | 48 +++++++++++++++---- .../hwtracing/coresight/coresight-cti-core.c | 2 + drivers/hwtracing/coresight/coresight-etb10.c | 2 + drivers/hwtracing/coresight/coresight-etm.h | 6 +-- .../coresight/coresight-etm3x-core.c | 28 +++++------ .../coresight/coresight-etm3x-sysfs.c | 8 ++-- .../coresight/coresight-etm4x-core.c | 2 + .../hwtracing/coresight/coresight-funnel.c | 2 + .../coresight/coresight-replicator.c | 1 + .../hwtracing/coresight/coresight-tmc-core.c | 1 + include/linux/coresight.h | 3 ++ 12 files changed, 73 insertions(+), 31 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtraci= ng/coresight/coresight-catu.c index d9259c0b6e64..575c2d247a90 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -558,6 +558,7 @@ static int __catu_probe(struct device *dev, struct reso= urce *res) catu_desc.subtype.helper_subtype =3D CORESIGHT_DEV_SUBTYPE_HELPER_CATU; catu_desc.ops =3D &catu_ops; =20 + coresight_reset_claim(&catu_desc.access); drvdata->csdev =3D coresight_register(&catu_desc); if (IS_ERR(drvdata->csdev)) ret =3D PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 7fe5d5d432c4..97f33ffad05e 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -212,20 +212,48 @@ int coresight_claim_device(struct coresight_device *c= sdev) EXPORT_SYMBOL_GPL(coresight_claim_device); =20 /* - * coresight_disclaim_device_unlocked : Clear the claim tag for the device. + * Clear the claim tag for the device. + * Returns an error if the device wasn't already claimed. + */ +int coresight_reset_claim(struct csdev_access *csa) +{ + int ret; + + CS_UNLOCK(csa->base); + ret =3D coresight_reset_claim_unlocked(csa); + CS_LOCK(csa->base); + return ret; +} +EXPORT_SYMBOL_GPL(coresight_reset_claim); + +/* + * Clear the claim tag for the device. Called with CS_UNLOCKed for the com= ponent. + * Returns an error if the device wasn't already claimed. + */ +int coresight_reset_claim_unlocked(struct csdev_access *csa) +{ + if (coresight_read_claim_tags(csa) =3D=3D CORESIGHT_CLAIM_SELF_HOSTED) { + coresight_clear_self_claim_tag(csa); + return 0; + } + + return -EINVAL; +} +EXPORT_SYMBOL_GPL(coresight_reset_claim_unlocked); + +/* + * coresight_disclaim_device_unlocked : Clear the claim tag for the device + * and warn if the device wasn't already claimed. * Called with CS_UNLOCKed for the component. */ void coresight_disclaim_device_unlocked(struct csdev_access *csa) { - if (coresight_read_claim_tags(csa) =3D=3D CORESIGHT_CLAIM_SELF_HOSTED) - coresight_clear_self_claim_tag(csa); - else - /* - * The external agent may have not honoured our claim - * and has manipulated it. Or something else has seriously - * gone wrong in our driver. - */ - WARN_ON_ONCE(1); + /* + * Warn if the external agent hasn't honoured our claim + * and has manipulated it. Or something else has seriously + * gone wrong in our driver. + */ + WARN_ON_ONCE(coresight_reset_claim_unlocked(csa)); } EXPORT_SYMBOL_GPL(coresight_disclaim_device_unlocked); =20 diff --git a/drivers/hwtracing/coresight/coresight-cti-core.c b/drivers/hwt= racing/coresight/coresight-cti-core.c index 073f67a41af9..389a72362f0c 100644 --- a/drivers/hwtracing/coresight/coresight-cti-core.c +++ b/drivers/hwtracing/coresight/coresight-cti-core.c @@ -931,6 +931,8 @@ static int cti_probe(struct amba_device *adev, const st= ruct amba_id *id) cti_desc.ops =3D &cti_ops; cti_desc.groups =3D drvdata->ctidev.con_groups; cti_desc.dev =3D dev; + + coresight_reset_claim(&cti_desc.access); drvdata->csdev =3D coresight_register(&cti_desc); if (IS_ERR(drvdata->csdev)) { ret =3D PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtrac= ing/coresight/coresight-etb10.c index d8bc3e776c88..b598b2c0c9bb 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -772,6 +772,8 @@ static int etb_probe(struct amba_device *adev, const st= ruct amba_id *id) desc.pdata =3D pdata; desc.dev =3D dev; desc.groups =3D coresight_etb_groups; + + coresight_reset_claim(&desc.access); drvdata->csdev =3D coresight_register(&desc); if (IS_ERR(drvdata->csdev)) return PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracin= g/coresight/coresight-etm.h index e02c3ea972c9..a89736309c27 100644 --- a/drivers/hwtracing/coresight/coresight-etm.h +++ b/drivers/hwtracing/coresight/coresight-etm.h @@ -229,7 +229,7 @@ struct etm_config { * @config: structure holding configuration parameters. */ struct etm_drvdata { - void __iomem *base; + struct csdev_access csa; struct clk *atclk; struct coresight_device *csdev; spinlock_t spinlock; @@ -260,7 +260,7 @@ static inline void etm_writel(struct etm_drvdata *drvda= ta, "invalid CP14 access to ETM reg: %#x", off); } } else { - writel_relaxed(val, drvdata->base + off); + writel_relaxed(val, drvdata->csa.base + off); } } =20 @@ -274,7 +274,7 @@ static inline unsigned int etm_readl(struct etm_drvdata= *drvdata, u32 off) "invalid CP14 access to ETM reg: %#x", off); } } else { - val =3D readl_relaxed(drvdata->base + off); + val =3D readl_relaxed(drvdata->csa.base + off); } =20 return val; diff --git a/drivers/hwtracing/coresight/coresight-etm3x-core.c b/drivers/h= wtracing/coresight/coresight-etm3x-core.c index 509f53b69e42..0b010683b883 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-core.c @@ -86,9 +86,9 @@ static void etm_set_pwrup(struct etm_drvdata *drvdata) { u32 etmpdcr; =20 - etmpdcr =3D readl_relaxed(drvdata->base + ETMPDCR); + etmpdcr =3D readl_relaxed(drvdata->csa.base + ETMPDCR); etmpdcr |=3D ETMPDCR_PWD_UP; - writel_relaxed(etmpdcr, drvdata->base + ETMPDCR); + writel_relaxed(etmpdcr, drvdata->csa.base + ETMPDCR); /* Ensure pwrup completes before subsequent cp14 accesses */ mb(); isb(); @@ -101,9 +101,9 @@ static void etm_clr_pwrup(struct etm_drvdata *drvdata) /* Ensure pending cp14 accesses complete before clearing pwrup */ mb(); isb(); - etmpdcr =3D readl_relaxed(drvdata->base + ETMPDCR); + etmpdcr =3D readl_relaxed(drvdata->csa.base + ETMPDCR); etmpdcr &=3D ~ETMPDCR_PWD_UP; - writel_relaxed(etmpdcr, drvdata->base + ETMPDCR); + writel_relaxed(etmpdcr, drvdata->csa.base + ETMPDCR); } =20 /** @@ -365,7 +365,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) struct etm_config *config =3D &drvdata->config; struct coresight_device *csdev =3D drvdata->csdev; =20 - CS_UNLOCK(drvdata->base); + CS_UNLOCK(drvdata->csa.base); =20 rc =3D coresight_claim_device_unlocked(csdev); if (rc) @@ -427,7 +427,7 @@ static int etm_enable_hw(struct etm_drvdata *drvdata) etm_clr_prog(drvdata); =20 done: - CS_LOCK(drvdata->base); + CS_LOCK(drvdata->csa.base); =20 dev_dbg(&drvdata->csdev->dev, "cpu: %d enable smp call done: %d\n", drvdata->cpu, rc); @@ -589,7 +589,7 @@ static void etm_disable_hw(void *info) struct etm_config *config =3D &drvdata->config; struct coresight_device *csdev =3D drvdata->csdev; =20 - CS_UNLOCK(drvdata->base); + CS_UNLOCK(drvdata->csa.base); etm_set_prog(drvdata); =20 /* Read back sequencer and counters for post trace analysis */ @@ -601,7 +601,7 @@ static void etm_disable_hw(void *info) etm_set_pwrdwn(drvdata); coresight_disclaim_device_unlocked(&csdev->access); =20 - CS_LOCK(drvdata->base); + CS_LOCK(drvdata->csa.base); =20 dev_dbg(&drvdata->csdev->dev, "cpu: %d disable smp call done\n", drvdata->cpu); @@ -614,7 +614,7 @@ static void etm_disable_perf(struct coresight_device *c= sdev) if (WARN_ON_ONCE(drvdata->cpu !=3D smp_processor_id())) return; =20 - CS_UNLOCK(drvdata->base); + CS_UNLOCK(drvdata->csa.base); =20 /* Setting the prog bit disables tracing immediately */ etm_set_prog(drvdata); @@ -626,7 +626,7 @@ static void etm_disable_perf(struct coresight_device *c= sdev) etm_set_pwrdwn(drvdata); coresight_disclaim_device_unlocked(&csdev->access); =20 - CS_LOCK(drvdata->base); + CS_LOCK(drvdata->csa.base); =20 /* * perf will release trace ids when _free_aux() @@ -772,7 +772,7 @@ static void etm_init_arch_data(void *info) /* Make sure all registers are accessible */ etm_os_unlock(drvdata); =20 - CS_UNLOCK(drvdata->base); + CS_UNLOCK(drvdata->csa.base); =20 /* First dummy read */ (void)etm_readl(drvdata, ETMPDSR); @@ -803,9 +803,10 @@ static void etm_init_arch_data(void *info) drvdata->nr_ext_out =3D BMVAL(etmccr, 20, 22); drvdata->nr_ctxid_cmp =3D BMVAL(etmccr, 24, 25); =20 + coresight_reset_claim_unlocked(&drvdata->csa); etm_set_pwrdwn(drvdata); etm_clr_pwrup(drvdata); - CS_LOCK(drvdata->base); + CS_LOCK(drvdata->csa.base); } =20 static int __init etm_hp_setup(void) @@ -866,8 +867,7 @@ static int etm_probe(struct amba_device *adev, const st= ruct amba_id *id) if (IS_ERR(base)) return PTR_ERR(base); =20 - drvdata->base =3D base; - desc.access =3D CSDEV_ACCESS_IOMEM(base); + desc.access =3D drvdata->csa =3D CSDEV_ACCESS_IOMEM(base); =20 spin_lock_init(&drvdata->spinlock); =20 diff --git a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm3x-sysfs.c index 68c644be9813..af566b62785c 100644 --- a/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm3x-sysfs.c @@ -50,11 +50,11 @@ static ssize_t etmsr_show(struct device *dev, =20 pm_runtime_get_sync(dev->parent); spin_lock_irqsave(&drvdata->spinlock, flags); - CS_UNLOCK(drvdata->base); + CS_UNLOCK(drvdata->csa.base); =20 val =3D etm_readl(drvdata, ETMSR); =20 - CS_LOCK(drvdata->base); + CS_LOCK(drvdata->csa.base); spin_unlock_irqrestore(&drvdata->spinlock, flags); pm_runtime_put(dev->parent); =20 @@ -949,9 +949,9 @@ static ssize_t seq_curr_state_show(struct device *dev, pm_runtime_get_sync(dev->parent); spin_lock_irqsave(&drvdata->spinlock, flags); =20 - CS_UNLOCK(drvdata->base); + CS_UNLOCK(drvdata->csa.base); val =3D (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK); - CS_LOCK(drvdata->base); + CS_LOCK(drvdata->csa.base); =20 spin_unlock_irqrestore(&drvdata->spinlock, flags); pm_runtime_put(dev->parent); diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 45b30a4b3eba..3609bb74c4ec 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -1337,6 +1337,8 @@ static void etm4_init_arch_data(void *info) drvdata->nrseqstate =3D FIELD_GET(TRCIDR5_NUMSEQSTATE_MASK, etmidr5); /* NUMCNTR, bits[30:28] number of counters available for tracing */ drvdata->nr_cntr =3D FIELD_GET(TRCIDR5_NUMCNTR_MASK, etmidr5); + + coresight_reset_claim_unlocked(csa); etm4_cs_lock(drvdata, csa); cpu_detect_trace_filtering(drvdata); } diff --git a/drivers/hwtracing/coresight/coresight-funnel.c b/drivers/hwtra= cing/coresight/coresight-funnel.c index e986922d555b..be2a47636ef3 100644 --- a/drivers/hwtracing/coresight/coresight-funnel.c +++ b/drivers/hwtracing/coresight/coresight-funnel.c @@ -255,6 +255,7 @@ static int funnel_probe(struct device *dev, struct reso= urce *res) drvdata->base =3D base; desc.groups =3D coresight_funnel_groups; desc.access =3D CSDEV_ACCESS_IOMEM(base); + coresight_reset_claim(&desc.access); } =20 dev_set_drvdata(dev, drvdata); @@ -272,6 +273,7 @@ static int funnel_probe(struct device *dev, struct reso= urce *res) desc.ops =3D &funnel_cs_ops; desc.pdata =3D pdata; desc.dev =3D dev; + drvdata->csdev =3D coresight_register(&desc); if (IS_ERR(drvdata->csdev)) { ret =3D PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index 5d42a9a8c460..679a36effbe8 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -284,6 +284,7 @@ static int replicator_probe(struct device *dev, struct = resource *res) desc.pdata =3D dev->platform_data; desc.dev =3D dev; =20 + coresight_reset_claim(&desc.access); drvdata->csdev =3D coresight_register(&desc); if (IS_ERR(drvdata->csdev)) { ret =3D PTR_ERR(drvdata->csdev); diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index e9876252a789..5ac4e3c706ac 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -558,6 +558,7 @@ static int __tmc_probe(struct device *dev, struct resou= rce *res) dev->platform_data =3D pdata; desc.pdata =3D pdata; =20 + coresight_reset_claim(&desc.access); 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([145.224.65.3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd02e2a90sm10456047f8f.98.2025.02.11.02.40.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 02:40:44 -0800 (PST) From: James Clark To: lcherian@marvell.com, coresight@lists.linaro.org Cc: James Clark , Suzuki K Poulose , Mike Leach , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 6/7] coresight: Remove inlines from static function definitions Date: Tue, 11 Feb 2025 10:39:42 +0000 Message-Id: <20250211103945.967495-7-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211103945.967495-1-james.clark@linaro.org> References: <20250211103945.967495-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These are all static and in one compilation unit so the inline has no effect on the binary. Except if FTRACE is enabled, then some functions which were already not inlined now get the nops added which allows them to be traced. Signed-off-by: James Clark --- drivers/hwtracing/coresight/coresight-catu.c | 11 ++++---- drivers/hwtracing/coresight/coresight-core.c | 16 ++++++------ drivers/hwtracing/coresight/coresight-etb10.c | 2 +- .../coresight/coresight-etm4x-core.c | 8 +++--- .../coresight/coresight-etm4x-sysfs.c | 4 +-- .../hwtracing/coresight/coresight-platform.c | 26 +++++++++---------- .../coresight/coresight-replicator.c | 2 +- drivers/hwtracing/coresight/coresight-stm.c | 6 ++--- .../coresight/coresight-syscfg-configfs.c | 2 +- .../hwtracing/coresight/coresight-tmc-core.c | 8 +++--- .../hwtracing/coresight/coresight-tmc-etr.c | 16 +++++------- drivers/hwtracing/coresight/coresight-trbe.c | 18 ++++++------- 12 files changed, 58 insertions(+), 61 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-catu.c b/drivers/hwtraci= ng/coresight/coresight-catu.c index 575c2d247a90..ffa08ea3c296 100644 --- a/drivers/hwtracing/coresight/coresight-catu.c +++ b/drivers/hwtracing/coresight/coresight-catu.c @@ -113,9 +113,8 @@ typedef u64 cate_t; * containing the data page pointer for @offset. If @daddrp is not NULL, * @daddrp points the DMA address of the beginning of the table. */ -static inline cate_t *catu_get_table(struct tmc_sg_table *catu_table, - unsigned long offset, - dma_addr_t *daddrp) +static cate_t *catu_get_table(struct tmc_sg_table *catu_table, unsigned lo= ng offset, + dma_addr_t *daddrp) { unsigned long buf_size =3D tmc_sg_table_buf_size(catu_table); unsigned int table_nr, pg_idx, pg_offset; @@ -165,12 +164,12 @@ static void catu_dump_table(struct tmc_sg_table *catu= _table) } =20 #else -static inline void catu_dump_table(struct tmc_sg_table *catu_table) +static void catu_dump_table(struct tmc_sg_table *catu_table) { } #endif =20 -static inline cate_t catu_make_entry(dma_addr_t addr) +static cate_t catu_make_entry(dma_addr_t addr) { return addr ? CATU_VALID_ENTRY(addr) : 0; } @@ -390,7 +389,7 @@ static const struct attribute_group *catu_groups[] =3D { }; =20 =20 -static inline int catu_wait_for_ready(struct catu_drvdata *drvdata) +static int catu_wait_for_ready(struct catu_drvdata *drvdata) { struct csdev_access *csa =3D &drvdata->csdev->access; =20 diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtraci= ng/coresight/coresight-core.c index 97f33ffad05e..396218819f26 100644 --- a/drivers/hwtracing/coresight/coresight-core.c +++ b/drivers/hwtracing/coresight/coresight-core.c @@ -127,20 +127,20 @@ coresight_find_out_connection(struct coresight_device= *csdev, return ERR_PTR(-ENODEV); } =20 -static inline u32 coresight_read_claim_tags(struct csdev_access *csa) +static u32 coresight_read_claim_tags(struct csdev_access *csa) { return FIELD_GET(CORESIGHT_CLAIM_MASK, csdev_access_relaxed_read32(csa, CORESIGHT_CLAIMCLR)); } =20 -static inline void coresight_set_self_claim_tag(struct csdev_access *csa) +static void coresight_set_self_claim_tag(struct csdev_access *csa) { csdev_access_relaxed_write32(csa, CORESIGHT_CLAIM_SELF_HOSTED, CORESIGHT_CLAIMSET); isb(); } =20 -static inline void coresight_clear_self_claim_tag(struct csdev_access *csa) +static void coresight_clear_self_claim_tag(struct csdev_access *csa) { csdev_access_relaxed_write32(csa, CORESIGHT_CLAIM_SELF_HOSTED, CORESIGHT_CLAIMCLR); @@ -610,7 +610,7 @@ struct coresight_device *coresight_get_sink_by_id(u32 i= d) * Return true in successful case and power up the device. * Return false when failed to get reference of module. */ -static inline bool coresight_get_ref(struct coresight_device *csdev) +static bool coresight_get_ref(struct coresight_device *csdev) { struct device *dev =3D csdev->dev.parent; =20 @@ -629,7 +629,7 @@ static inline bool coresight_get_ref(struct coresight_d= evice *csdev) * * @csdev: The coresight device to decrement a reference from. */ -static inline void coresight_put_ref(struct coresight_device *csdev) +static void coresight_put_ref(struct coresight_device *csdev) { struct device *dev =3D csdev->dev.parent; =20 @@ -808,7 +808,7 @@ void coresight_release_path(struct list_head *path) } =20 /* return true if the device is a suitable type for a default sink */ -static inline bool coresight_is_def_sink_type(struct coresight_device *csd= ev) +static bool coresight_is_def_sink_type(struct coresight_device *csdev) { /* sink & correct subtype */ if (((csdev->type =3D=3D CORESIGHT_DEV_TYPE_SINK) || @@ -1362,8 +1362,8 @@ EXPORT_SYMBOL_GPL(coresight_unregister); * * Returns the index of the entry, when found. Otherwise, -ENOENT. */ -static inline int coresight_search_device_idx(struct coresight_dev_list *d= ict, - struct fwnode_handle *fwnode) +static int coresight_search_device_idx(struct coresight_dev_list *dict, + struct fwnode_handle *fwnode) { int i; =20 diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtrac= ing/coresight/coresight-etb10.c index b598b2c0c9bb..de6d3a6fb828 100644 --- a/drivers/hwtracing/coresight/coresight-etb10.c +++ b/drivers/hwtracing/coresight/coresight-etb10.c @@ -95,7 +95,7 @@ struct etb_drvdata { static int etb_set_buffer(struct coresight_device *csdev, struct perf_output_handle *handle); =20 -static inline unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdat= a) +static unsigned int etb_get_buffer_depth(struct etb_drvdata *drvdata) { return readl_relaxed(drvdata->base + ETB_RAM_DEPTH_REG); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/h= wtracing/coresight/coresight-etm4x-core.c index 3609bb74c4ec..9e7d423c1ae9 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -84,7 +84,7 @@ static int etm4_probe_cpu(unsigned int cpu); * TRCIDR4.NUMPC > 0b0000 . * TRCSSCSR.PC =3D=3D 0b1 */ -static inline bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, i= nt n) +static bool etm4x_sspcicrn_present(struct etmv4_drvdata *drvdata, int n) { return (n < drvdata->nr_ss_cmp) && drvdata->nr_pe && @@ -185,7 +185,7 @@ static void etm_write_os_lock(struct etmv4_drvdata *drv= data, isb(); } =20 -static inline void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, +static void etm4_os_unlock_csa(struct etmv4_drvdata *drvdata, struct csdev_access *csa) { WARN_ON(drvdata->cpu !=3D smp_processor_id()); @@ -1035,7 +1035,7 @@ static const struct coresight_ops etm4_cs_ops =3D { .source_ops =3D &etm4_source_ops, }; =20 -static inline bool cpu_supports_sysreg_trace(void) +static bool cpu_supports_sysreg_trace(void) { u64 dfr0 =3D read_sysreg_s(SYS_ID_AA64DFR0_EL1); =20 @@ -1343,7 +1343,7 @@ static void etm4_init_arch_data(void *info) cpu_detect_trace_filtering(drvdata); } =20 -static inline u32 etm4_get_victlr_access_type(struct etmv4_config *config) +static u32 etm4_get_victlr_access_type(struct etmv4_config *config) { return etm4_get_access_type(config) << __bf_shf(TRCVICTLR_EXLEVEL_MASK); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/= hwtracing/coresight/coresight-etm4x-sysfs.c index a9f19629f3f8..0465c32f7ed4 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -2440,7 +2440,7 @@ static u32 etmv4_cross_read(const struct etmv4_drvdat= a *drvdata, u32 offset) return reg.data; } =20 -static inline u32 coresight_etm4x_attr_to_offset(struct device_attribute *= attr) +static u32 coresight_etm4x_attr_to_offset(struct device_attribute *attr) { struct dev_ext_attribute *eattr; =20 @@ -2464,7 +2464,7 @@ static ssize_t coresight_etm4x_reg_show(struct device= *dev, return scnprintf(buf, PAGE_SIZE, "0x%x\n", val); } =20 -static inline bool +static bool etm4x_register_implemented(struct etmv4_drvdata *drvdata, u32 offset) { switch (offset) { diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwt= racing/coresight/coresight-platform.c index 8192ba3279f0..0db64c5f4995 100644 --- a/drivers/hwtracing/coresight/coresight-platform.c +++ b/drivers/hwtracing/coresight/coresight-platform.c @@ -139,7 +139,7 @@ coresight_find_csdev_by_fwnode(struct fwnode_handle *r_= fwnode) EXPORT_SYMBOL_GPL(coresight_find_csdev_by_fwnode); =20 #ifdef CONFIG_OF -static inline bool of_coresight_legacy_ep_is_input(struct device_node *ep) +static bool of_coresight_legacy_ep_is_input(struct device_node *ep) { return of_property_read_bool(ep, "slave-mode"); } @@ -159,7 +159,7 @@ static struct device_node *of_coresight_get_port_parent= (struct device_node *ep) return parent; } =20 -static inline struct device_node * +static struct device_node * of_coresight_get_output_ports_node(const struct device_node *node) { return of_get_child_by_name(node, "out-ports"); @@ -327,14 +327,14 @@ static int of_get_coresight_platform_data(struct devi= ce *dev, return 0; } #else -static inline int +static int of_get_coresight_platform_data(struct device *dev, struct coresight_platform_data *pdata) { return -ENOENT; } =20 -static inline int of_coresight_get_cpu(struct device *dev) +static int of_coresight_get_cpu(struct device *dev) { return -ENODEV; } @@ -356,7 +356,7 @@ static const guid_t coresight_graph_uuid =3D GUID_INIT(= 0x3ecbc8b6, 0x1d0e, 0x4fb3, #define ACPI_CORESIGHT_LINK_SLAVE 0 #define ACPI_CORESIGHT_LINK_MASTER 1 =20 -static inline bool is_acpi_guid(const union acpi_object *obj) +static bool is_acpi_guid(const union acpi_object *obj) { return (obj->type =3D=3D ACPI_TYPE_BUFFER) && (obj->buffer.length =3D=3D = 16); } @@ -365,24 +365,24 @@ static inline bool is_acpi_guid(const union acpi_obje= ct *obj) * acpi_guid_matches - Checks if the given object is a GUID object and * that it matches the supplied the GUID. */ -static inline bool acpi_guid_matches(const union acpi_object *obj, +static bool acpi_guid_matches(const union acpi_object *obj, const guid_t *guid) { return is_acpi_guid(obj) && guid_equal((guid_t *)obj->buffer.pointer, guid); } =20 -static inline bool is_acpi_dsd_graph_guid(const union acpi_object *obj) +static bool is_acpi_dsd_graph_guid(const union acpi_object *obj) { return acpi_guid_matches(obj, &acpi_graph_uuid); } =20 -static inline bool is_acpi_coresight_graph_guid(const union acpi_object *o= bj) +static bool is_acpi_coresight_graph_guid(const union acpi_object *obj) { return acpi_guid_matches(obj, &coresight_graph_uuid); } =20 -static inline bool is_acpi_coresight_graph(const union acpi_object *obj) +static bool is_acpi_coresight_graph(const union acpi_object *obj) { const union acpi_object *graphid, *guid, *links; =20 @@ -469,7 +469,7 @@ static inline bool is_acpi_coresight_graph(const union = acpi_object *obj) * }, // End of ACPI Graph Property * }) */ -static inline bool acpi_validate_dsd_graph(const union acpi_object *graph) +static bool acpi_validate_dsd_graph(const union acpi_object *graph) { int i, n; const union acpi_object *rev, *nr_graphs; @@ -553,7 +553,7 @@ acpi_get_dsd_graph(struct acpi_device *adev, struct acp= i_buffer *buf) return NULL; } =20 -static inline bool +static bool acpi_validate_coresight_graph(const union acpi_object *cs_graph) { int nlinks; @@ -794,14 +794,14 @@ acpi_get_coresight_platform_data(struct device *dev, =20 #else =20 -static inline int +static int acpi_get_coresight_platform_data(struct device *dev, struct coresight_platform_data *pdata) { return -ENOENT; } =20 -static inline int acpi_coresight_get_cpu(struct device *dev) +static int acpi_coresight_get_cpu(struct device *dev) { return -ENODEV; } diff --git a/drivers/hwtracing/coresight/coresight-replicator.c b/drivers/h= wtracing/coresight/coresight-replicator.c index 679a36effbe8..9f27374f1310 100644 --- a/drivers/hwtracing/coresight/coresight-replicator.c +++ b/drivers/hwtracing/coresight/coresight-replicator.c @@ -63,7 +63,7 @@ static void dynamic_replicator_reset(struct replicator_dr= vdata *drvdata) /* * replicator_reset : Reset the replicator configuration to sane values. */ -static inline void replicator_reset(struct replicator_drvdata *drvdata) +static void replicator_reset(struct replicator_drvdata *drvdata) { if (drvdata->base) dynamic_replicator_reset(drvdata); diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracin= g/coresight/coresight-stm.c index b581a30a1cd9..5decc87d1fba 100644 --- a/drivers/hwtracing/coresight/coresight-stm.c +++ b/drivers/hwtracing/coresight/coresight-stm.c @@ -290,7 +290,7 @@ static const struct coresight_ops stm_cs_ops =3D { .source_ops =3D &stm_source_ops, }; =20 -static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes) +static bool stm_addr_unaligned(const void *addr, u8 write_bytes) { return ((unsigned long)addr & (write_bytes - 1)); } @@ -674,7 +674,7 @@ static int of_stm_get_stimulus_area(struct device *dev,= struct resource *res) return of_address_to_resource(np, index, res); } #else -static inline int of_stm_get_stimulus_area(struct device *dev, +static int of_stm_get_stimulus_area(struct device *dev, struct resource *res) { return -ENOENT; @@ -718,7 +718,7 @@ static int acpi_stm_get_stimulus_area(struct device *de= v, struct resource *res) return rc; } #else -static inline int acpi_stm_get_stimulus_area(struct device *dev, +static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res) { return -ENOENT; diff --git a/drivers/hwtracing/coresight/coresight-syscfg-configfs.c b/driv= ers/hwtracing/coresight/coresight-syscfg-configfs.c index 213b4159b062..2b40e556be87 100644 --- a/drivers/hwtracing/coresight/coresight-syscfg-configfs.c +++ b/drivers/hwtracing/coresight/coresight-syscfg-configfs.c @@ -10,7 +10,7 @@ #include "coresight-syscfg-configfs.h" =20 /* create a default ci_type. */ -static inline struct config_item_type *cscfg_create_ci_type(void) +static struct config_item_type *cscfg_create_ci_type(void) { struct config_item_type *ci_type; =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwt= racing/coresight/coresight-tmc-core.c index 5ac4e3c706ac..2e3354b5c5c7 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-core.c +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c @@ -164,8 +164,8 @@ static int tmc_open(struct inode *inode, struct file *f= ile) return 0; } =20 -static inline ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, - loff_t pos, size_t len, char **bufpp) +static ssize_t tmc_get_sysfs_trace(struct tmc_drvdata *drvdata, loff_t pos= , size_t len, + char **bufpp) { switch (drvdata->config_type) { case TMC_CONFIG_TYPE_ETB: @@ -359,7 +359,7 @@ static const struct attribute_group *coresight_etr_grou= ps[] =3D { NULL, }; =20 -static inline bool tmc_etr_can_use_sg(struct device *dev) +static bool tmc_etr_can_use_sg(struct device *dev) { int ret; u8 val_u8; @@ -389,7 +389,7 @@ static inline bool tmc_etr_can_use_sg(struct device *de= v) return false; } =20 -static inline bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvda= ta) +static bool tmc_etr_has_non_secure_access(struct tmc_drvdata *drvdata) { u32 auth =3D readl_relaxed(drvdata->base + TMC_AUTHSTATUS); =20 diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtr= acing/coresight/coresight-tmc-etr.c index 7ba4f79191de..0d4e3af0d4b5 100644 --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c @@ -124,7 +124,7 @@ struct etr_sg_table { * If we spill over to a new page for mapping 1 entry, we could as * well replace the link entry of the previous page with the last entry. */ -static inline unsigned long __attribute_const__ +static unsigned long __attribute_const__ tmc_etr_sg_table_entries(int nr_pages) { unsigned long nr_sgpages =3D nr_pages * ETR_SG_PAGES_PER_SYSPAGE; @@ -238,13 +238,13 @@ static int tmc_pages_alloc(struct tmc_pages *tmc_page= s, return -ENOMEM; } =20 -static inline long +static long tmc_sg_get_data_page_offset(struct tmc_sg_table *sg_table, dma_addr_t addr) { return tmc_pages_get_offset(&sg_table->data_pages, addr); } =20 -static inline void tmc_free_table_pages(struct tmc_sg_table *sg_table) +static void tmc_free_table_pages(struct tmc_sg_table *sg_table) { if (sg_table->table_vaddr) vunmap(sg_table->table_vaddr); @@ -480,7 +480,7 @@ static void tmc_etr_sg_table_dump(struct etr_sg_table *= etr_table) dev_dbg(sg_table->dev, "******* End of Table *****\n"); } #else -static inline void tmc_etr_sg_table_dump(struct etr_sg_table *etr_table) {} +static void tmc_etr_sg_table_dump(struct etr_sg_table *etr_table) {} #endif =20 /* @@ -815,10 +815,8 @@ void tmc_etr_remove_catu_ops(void) } EXPORT_SYMBOL_GPL(tmc_etr_remove_catu_ops); =20 -static inline int tmc_etr_mode_alloc_buf(int mode, - struct tmc_drvdata *drvdata, - struct etr_buf *etr_buf, int node, - void **pages) +static int tmc_etr_mode_alloc_buf(int mode, struct tmc_drvdata *drvdata, s= truct etr_buf *etr_buf, + int node, void **pages) { int rc =3D -EINVAL; =20 @@ -936,7 +934,7 @@ static ssize_t tmc_etr_buf_get_data(struct etr_buf *etr= _buf, return etr_buf->ops->get_data(etr_buf, (u64)offset, len, bufpp); } =20 -static inline s64 +static s64 tmc_etr_buf_insert_barrier_packet(struct etr_buf *etr_buf, u64 offset) { ssize_t len; diff --git a/drivers/hwtracing/coresight/coresight-trbe.c b/drivers/hwtraci= ng/coresight/coresight-trbe.c index 919804b12a67..e9a19ef52359 100644 --- a/drivers/hwtracing/coresight/coresight-trbe.c +++ b/drivers/hwtracing/coresight/coresight-trbe.c @@ -159,22 +159,22 @@ static void trbe_check_errata(struct trbe_cpudata *cp= udata) } } =20 -static inline bool trbe_has_erratum(struct trbe_cpudata *cpudata, int i) +static bool trbe_has_erratum(struct trbe_cpudata *cpudata, int i) { return (i < TRBE_ERRATA_MAX) && test_bit(i, cpudata->errata); } =20 -static inline bool trbe_may_overwrite_in_fill_mode(struct trbe_cpudata *cp= udata) +static bool trbe_may_overwrite_in_fill_mode(struct trbe_cpudata *cpudata) { return trbe_has_erratum(cpudata, TRBE_WORKAROUND_OVERWRITE_FILL_MODE); } =20 -static inline bool trbe_may_write_out_of_range(struct trbe_cpudata *cpudat= a) +static bool trbe_may_write_out_of_range(struct trbe_cpudata *cpudata) { return trbe_has_erratum(cpudata, TRBE_WORKAROUND_WRITE_OUT_OF_RANGE); } =20 -static inline bool trbe_needs_drain_after_disable(struct trbe_cpudata *cpu= data) +static bool trbe_needs_drain_after_disable(struct trbe_cpudata *cpudata) { /* * Errata affected TRBE implementation will need TSB CSYNC and @@ -184,7 +184,7 @@ static inline bool trbe_needs_drain_after_disable(struc= t trbe_cpudata *cpudata) return trbe_has_erratum(cpudata, TRBE_NEEDS_DRAIN_AFTER_DISABLE); } =20 -static inline bool trbe_needs_ctxt_sync_after_enable(struct trbe_cpudata *= cpudata) +static bool trbe_needs_ctxt_sync_after_enable(struct trbe_cpudata *cpudata) { /* * Errata affected TRBE implementation will need an additional @@ -195,7 +195,7 @@ static inline bool trbe_needs_ctxt_sync_after_enable(st= ruct trbe_cpudata *cpudat return trbe_has_erratum(cpudata, TRBE_NEEDS_CTXT_SYNC_AFTER_ENABLE); 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([145.224.65.3]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dd02e2a90sm10456047f8f.98.2025.02.11.02.40.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Feb 2025 02:40:47 -0800 (PST) From: James Clark To: lcherian@marvell.com, coresight@lists.linaro.org Cc: James Clark , Suzuki K Poulose , Mike Leach , Alexander Shishkin , Maxime Coquelin , Alexandre Torgue , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH 7/7] coresight: Remove extern from function declarations Date: Tue, 11 Feb 2025 10:39:43 +0000 Message-Id: <20250211103945.967495-8-james.clark@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250211103945.967495-1-james.clark@linaro.org> References: <20250211103945.967495-1-james.clark@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Function declarations are extern by default so remove the extra noise and inconsistency. Signed-off-by: James Clark Reviewed-by: Leo Yan --- drivers/hwtracing/coresight/coresight-priv.h | 14 ++++----- include/linux/coresight.h | 33 +++++++++----------- 2 files changed, 21 insertions(+), 26 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtraci= ng/coresight/coresight-priv.h index a83113225797..e09071a720f0 100644 --- a/drivers/hwtracing/coresight/coresight-priv.h +++ b/drivers/hwtracing/coresight/coresight-priv.h @@ -57,10 +57,8 @@ struct cs_off_attribute { u32 off; }; =20 -extern ssize_t coresight_simple_show32(struct device *_dev, - struct device_attribute *attr, char *buf); -extern ssize_t coresight_simple_show_pair(struct device *_dev, - struct device_attribute *attr, char *buf); +ssize_t coresight_simple_show32(struct device *_dev, struct device_attribu= te *attr, char *buf); +ssize_t coresight_simple_show_pair(struct device *_dev, struct device_attr= ibute *attr, char *buf); =20 #define coresight_simple_reg32(name, offset) \ (&((struct cs_off_attribute[]) { \ @@ -155,8 +153,8 @@ void coresight_remove_links(struct coresight_device *or= ig, u32 coresight_get_sink_id(struct coresight_device *csdev); =20 #if IS_ENABLED(CONFIG_CORESIGHT_SOURCE_ETM3X) -extern int etm_readl_cp14(u32 off, unsigned int *val); -extern int etm_writel_cp14(u32 off, u32 val); +int etm_readl_cp14(u32 off, unsigned int *val); +int etm_writel_cp14(u32 off, u32 val); #else static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; } static inline int etm_writel_cp14(u32 off, u32 val) { return 0; } @@ -167,8 +165,8 @@ struct cti_assoc_op { void (*remove)(struct coresight_device *csdev); }; =20 -extern void coresight_set_cti_ops(const struct cti_assoc_op *cti_op); -extern void coresight_remove_cti_ops(void); +void coresight_set_cti_ops(const struct cti_assoc_op *cti_op); +void coresight_remove_cti_ops(void); =20 /* * Macros and inline functions to handle CoreSight UCI data and driver diff --git a/include/linux/coresight.h b/include/linux/coresight.h index 11808aee9d1d..2b43698c0b25 100644 --- a/include/linux/coresight.h +++ b/include/linux/coresight.h @@ -642,26 +642,23 @@ static inline void coresight_set_mode(struct coresigh= t_device *csdev, local_set(&csdev->mode, new_mode); } =20 -extern struct coresight_device * -coresight_register(struct coresight_desc *desc); -extern void coresight_unregister(struct coresight_device *csdev); -extern int coresight_enable_sysfs(struct coresight_device *csdev); -extern void coresight_disable_sysfs(struct coresight_device *csdev); -extern int coresight_timeout(struct csdev_access *csa, u32 offset, - int position, int value); - -extern int coresight_claim_device(struct coresight_device *csdev); -extern int coresight_claim_device_unlocked(struct coresight_device *csdev); - -extern void coresight_disclaim_device(struct csdev_access *csa); -extern void coresight_disclaim_device_unlocked(struct csdev_access *csa); +struct coresight_device *coresight_register(struct coresight_desc *desc); +void coresight_unregister(struct coresight_device *csdev); +int coresight_enable_sysfs(struct coresight_device *csdev); +void coresight_disable_sysfs(struct coresight_device *csdev); +int coresight_timeout(struct csdev_access *csa, u32 offset, int position, = int value); + +int coresight_claim_device(struct coresight_device *csdev); +int coresight_claim_device_unlocked(struct coresight_device *csdev); + +void coresight_disclaim_device(struct csdev_access *csa); +void coresight_disclaim_device_unlocked(struct csdev_access *csa); int coresight_reset_claim_unlocked(struct csdev_access *csa); int coresight_reset_claim(struct csdev_access *csa); =20 -extern char *coresight_alloc_device_name(struct coresight_dev_list *devs, - struct device *dev); +char *coresight_alloc_device_name(struct coresight_dev_list *devs, struct = device *dev); =20 -extern bool coresight_loses_context_with_cpu(struct device *dev); +bool coresight_loses_context_with_cpu(struct device *dev); =20 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset); u32 coresight_read32(struct coresight_device *csdev, u32 offset); @@ -674,8 +671,8 @@ void coresight_relaxed_write64(struct coresight_device = *csdev, u64 val, u32 offset); void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset= ); =20 -extern int coresight_get_cpu(struct device *dev); -extern int coresight_get_static_trace_id(struct device *dev, u32 *id); +int coresight_get_cpu(struct device *dev); +int coresight_get_static_trace_id(struct device *dev, u32 *id); =20 struct coresight_platform_data *coresight_get_platform_data(struct device = *dev); struct coresight_connection * --=20 2.34.1