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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 06:20:27.2661 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b263c5f9-b6c0-46a3-7530-08dd4a642d50 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023CB.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7684 Content-Type: text/plain; charset="utf-8" The Tegra UTC (UART Trace Controller) allows multiple clients within the Tegra SoC to share a physical UART interface. It supports up to 16 clients. Each client operates as an independent UART endpoint with a dedicated interrupt and 128-character TX/RX FIFOs. Add device tree binding documentation for the Tegra UTC client. Signed-off-by: Kartik Rajput --- v1 -> v2: * Removed current-speed as it might not be accurate as the Tegra UTC multiplex data from various clients. * Use 'tx-threshold' and 'rx-threshold' properties defined in serial.yaml instead of 'nvidia,utc-fifo-threshold'. * Add serial.yaml reference. * Define minimum and maximum values for threshold. * Rephrase the documentation to clarify that we are documenting the Tegra UTC clients and not the controller itself. --- .../bindings/serial/nvidia,tegra264-utc.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/nvidia,tegra26= 4-utc.yaml diff --git a/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.y= aml b/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml new file mode 100644 index 000000000000..572cc574da64 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/nvidia,tegra264-utc.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/nvidia,tegra264-utc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra UTC (UART Trace Controller) client + +maintainers: + - Kartik Rajput + - Thierry Reding + - Jonathan Hunter + +description: + Represents a client interface of the Tegra UTC (UART Trace Controller). = The + Tegra UTC allows multiple clients within the Tegra SoC to share a physic= al + UART interface. It supports up to 16 clients. Each client operates as an + independent UART endpoint with a dedicated interrupt and 128-character T= X/RX + FIFOs. + + The Tegra UTC clients use 8-N-1 configuration and operates on a baudrate + configured by the bootloader at the controller level. + +allOf: + - $ref: serial.yaml# + +properties: + compatible: + const: nvidia,tegra264-utc + + reg: + items: + - description: TX region. + - description: RX region. + + reg-names: + items: + - const: tx + - const: rx + + interrupts: + maxItems: 1 + + tx-threshold: + minimum: 1 + maximum: 128 + + rx-threshold: + minimum: 1 + maximum: 128 + +required: + - compatible + - reg + - reg-names + - interrupts + - tx-threshold + - rx-threshold + +additionalProperties: false + +examples: + - | + #include + + tegra_utc: serial@c4e0000 { + compatible =3D "nvidia,tegra264-utc"; + reg =3D <0xc4e0000 0x8000>, <0xc4e8000 0x8000>; + reg-names =3D "tx", "rx"; + interrupts =3D ; + tx-threshold =3D <4>; + rx-threshold =3D <4>; + }; --=20 2.43.0 From nobody Wed Dec 17 03:19:48 2025 Received: from NAM11-DM6-obe.outbound.protection.outlook.com (mail-dm6nam11on2081.outbound.protection.outlook.com [40.107.223.81]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8C4CD1EB9ED; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Feb 2025 06:20:32.4695 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 41732e18-9c46-4c00-2746-08dd4a64305c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000023D2.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4492 Content-Type: text/plain; charset="utf-8" The Tegra264 SoC supports the UTC (UART Trace Controller), which allows multiple firmware clients (up to 16) to share a single physical UART. Each client is provided with its own interrupt and has access to a 128-character wide FIFO for both transmit (TX) and receive (RX) operations. Add tegra-utc driver to support Tegra UART Trace Controller (UTC) client. Signed-off-by: Kartik Rajput --- v1 -> v2: * Use dev_err_probe() in tegra_utc_probe(). * Use uart_read_port_properties() instead of manually parsing the port line. * Remove duplicate error prints if platform_get_irq() fails. * In tegra_utc_of_match, remove `,` after terminator line. * Remove current-speed, as it is not always accurate. --- drivers/tty/serial/Kconfig | 23 ++ drivers/tty/serial/Makefile | 1 + drivers/tty/serial/tegra-utc.c | 622 +++++++++++++++++++++++++++++++++ 3 files changed, 646 insertions(+) create mode 100644 drivers/tty/serial/tegra-utc.c diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 976dae3bb1bb..edc56a3c0ace 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -306,6 +306,29 @@ config SERIAL_TEGRA_TCU_CONSOLE =20 If unsure, say Y. =20 +config SERIAL_TEGRA_UTC + tristate "NVIDIA Tegra UART Trace Controller" + depends on ARCH_TEGRA || COMPILE_TEST + select SERIAL_CORE + help + Support for Tegra UTC (UART Trace controller) client serial port. + + UTC is a HW based serial port that allows multiplexing multiple data + streams of up to 16 UTC clients into a single hardware serial port. + +config SERIAL_TEGRA_UTC_CONSOLE + bool "Support for console on a Tegra UTC serial port" + depends on SERIAL_TEGRA_UTC + select SERIAL_CORE_CONSOLE + default SERIAL_TEGRA_UTC + help + If you say Y here, it will be possible to use a Tegra UTC client as + the system console (the system console is the device which receives + all kernel messages and warnings and which allows logins in single + user mode). + + If unsure, say Y. + config SERIAL_MAX3100 tristate "MAX3100/3110/3111/3222 support" depends on SPI diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile index 6ff74f0a9530..7190914ba707 100644 --- a/drivers/tty/serial/Makefile +++ b/drivers/tty/serial/Makefile @@ -86,6 +86,7 @@ obj-$(CONFIG_SERIAL_STM32) +=3D stm32-usart.o obj-$(CONFIG_SERIAL_SUNPLUS) +=3D sunplus-uart.o obj-$(CONFIG_SERIAL_TEGRA) +=3D serial-tegra.o obj-$(CONFIG_SERIAL_TEGRA_TCU) +=3D tegra-tcu.o +obj-$(CONFIG_SERIAL_TEGRA_UTC) +=3D tegra-utc.o obj-$(CONFIG_SERIAL_TIMBERDALE) +=3D timbuart.o obj-$(CONFIG_SERIAL_TXX9) +=3D serial_txx9.o obj-$(CONFIG_SERIAL_UARTLITE) +=3D uartlite.o diff --git a/drivers/tty/serial/tegra-utc.c b/drivers/tty/serial/tegra-utc.c new file mode 100644 index 000000000000..75d39cb8394a --- /dev/null +++ b/drivers/tty/serial/tegra-utc.c @@ -0,0 +1,622 @@ +// SPDX-License-Identifier: GPL-2.0-only +// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIA= TES. All rights reserved. +/* + * NVIDIA Tegra UTC (UART Trace Controller) driver. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TEGRA_UTC_ENABLE 0x0 +#define TEGRA_UTC_ENABLE_CLIENT_ENABLE BIT(0) + +#define TEGRA_UTC_FIFO_THRESHOLD 0x8 + +#define TEGRA_UTC_COMMAND 0xc +#define TEGRA_UTC_COMMAND_FLUSH BIT(1) +#define TEGRA_UTC_COMMAND_RESET BIT(0) + +#define TEGRA_UTC_DATA 0x20 + +#define TEGRA_UTC_FIFO_STATUS 0x100 +#define TEGRA_UTC_FIFO_TIMEOUT BIT(4) +#define TEGRA_UTC_FIFO_OVERFLOW BIT(3) +#define TEGRA_UTC_FIFO_REQ BIT(2) +#define TEGRA_UTC_FIFO_FULL BIT(1) +#define TEGRA_UTC_FIFO_EMPTY BIT(0) + +#define TEGRA_UTC_FIFO_OCCUPANCY 0x104 + +#define TEGRA_UTC_INTR_STATUS 0x108 +#define TEGRA_UTC_INTR_SET 0x10c +#define TEGRA_UTC_INTR_MASK 0x110 +#define TEGRA_UTC_INTR_CLEAR 0x114 +#define TEGRA_UTC_INTR_TIMEOUT BIT(4) +#define TEGRA_UTC_INTR_OVERFLOW BIT(3) +#define TEGRA_UTC_INTR_REQ BIT(2) +#define TEGRA_UTC_INTR_FULL BIT(1) +#define TEGRA_UTC_INTR_EMPTY BIT(0) + +#define UART_NR 16 + +struct tegra_utc_soc { + unsigned int fifosize; +}; + +struct tegra_utc_port { + const struct tegra_utc_soc *soc; +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_UTC_CONSOLE) + struct console console; +#endif + struct uart_port port; + + void __iomem *rx_base; + void __iomem *tx_base; + + u32 tx_irqmask; + u32 rx_irqmask; + + u32 tx_threshold; + u32 rx_threshold; + int irq; +}; + +static u32 tegra_utc_rx_readl(struct tegra_utc_port *tup, unsigned int off= set) +{ + void __iomem *addr =3D tup->rx_base + offset; + + return readl_relaxed(addr); +} + +static void tegra_utc_rx_writel(struct tegra_utc_port *tup, u32 val, unsig= ned int offset) +{ + void __iomem *addr =3D tup->rx_base + offset; + + writel_relaxed(val, addr); +} + +static u32 tegra_utc_tx_readl(struct tegra_utc_port *tup, unsigned int off= set) +{ + void __iomem *addr =3D tup->tx_base + offset; + + return readl_relaxed(addr); +} + +static void tegra_utc_tx_writel(struct tegra_utc_port *tup, u32 val, unsig= ned int offset) +{ + void __iomem *addr =3D tup->tx_base + offset; + + writel_relaxed(val, addr); +} + +static void tegra_utc_enable_tx_irq(struct tegra_utc_port *tup) +{ + tup->tx_irqmask =3D TEGRA_UTC_INTR_REQ; + + tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_MASK); + tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_SET); +} + +static void tegra_utc_disable_tx_irq(struct tegra_utc_port *tup) +{ + tup->tx_irqmask =3D 0x0; + + tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_MASK); + tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_SET); +} + +static void tegra_utc_stop_tx(struct uart_port *port) +{ + struct tegra_utc_port *tup =3D container_of(port, struct tegra_utc_port, = port); + + tegra_utc_disable_tx_irq(tup); +} + +static void tegra_utc_init_tx(struct tegra_utc_port *tup) +{ + /* Disable TX. */ + tegra_utc_tx_writel(tup, 0x0, TEGRA_UTC_ENABLE); + + /* Update the FIFO Threshold. */ + tegra_utc_tx_writel(tup, tup->tx_threshold, TEGRA_UTC_FIFO_THRESHOLD); + + /* Clear and mask all the interrupts. */ + tegra_utc_tx_writel(tup, TEGRA_UTC_INTR_REQ | TEGRA_UTC_INTR_FULL | TEGRA= _UTC_INTR_EMPTY, + TEGRA_UTC_INTR_CLEAR); + tegra_utc_disable_tx_irq(tup); + + /* Enable TX. */ + tegra_utc_tx_writel(tup, TEGRA_UTC_ENABLE_CLIENT_ENABLE, TEGRA_UTC_ENABLE= ); +} + +static void tegra_utc_init_rx(struct tegra_utc_port *tup) +{ + tup->rx_irqmask =3D TEGRA_UTC_INTR_REQ | TEGRA_UTC_INTR_TIMEOUT; + + tegra_utc_rx_writel(tup, TEGRA_UTC_COMMAND_RESET, TEGRA_UTC_COMMAND); + tegra_utc_rx_writel(tup, tup->rx_threshold, TEGRA_UTC_FIFO_THRESHOLD); + + /* Clear all the pending interrupts. */ + tegra_utc_rx_writel(tup, TEGRA_UTC_INTR_TIMEOUT | TEGRA_UTC_INTR_OVERFLOW= | + TEGRA_UTC_INTR_REQ | TEGRA_UTC_INTR_FULL | + TEGRA_UTC_INTR_EMPTY, TEGRA_UTC_INTR_CLEAR); + tegra_utc_rx_writel(tup, tup->rx_irqmask, TEGRA_UTC_INTR_MASK); + tegra_utc_rx_writel(tup, tup->rx_irqmask, TEGRA_UTC_INTR_SET); + + /* Enable RX. */ + tegra_utc_rx_writel(tup, TEGRA_UTC_ENABLE_CLIENT_ENABLE, TEGRA_UTC_ENABLE= ); +} + +static bool tegra_utc_tx_char(struct tegra_utc_port *tup, u8 c) +{ + if (tegra_utc_tx_readl(tup, TEGRA_UTC_FIFO_STATUS) & TEGRA_UTC_FIFO_FULL) + return false; + + tegra_utc_tx_writel(tup, c, TEGRA_UTC_DATA); + + return true; +} + +static bool tegra_utc_tx_chars(struct tegra_utc_port *tup) +{ + struct tty_port *tport =3D &tup->port.state->port; + u8 c; + + if (tup->port.x_char) { + if (!tegra_utc_tx_char(tup, tup->port.x_char)) + return true; + + tup->port.x_char =3D 0; + } + + if (kfifo_is_empty(&tport->xmit_fifo) || uart_tx_stopped(&tup->port)) { + tegra_utc_stop_tx(&tup->port); + return false; + } + + while (kfifo_peek(&tport->xmit_fifo, &c)) { + if (!tegra_utc_tx_char(tup, c)) + break; + + kfifo_skip(&tport->xmit_fifo); + } + + if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS) + uart_write_wakeup(&tup->port); + + if (kfifo_is_empty(&tport->xmit_fifo)) { + tegra_utc_stop_tx(&tup->port); + return false; + } + + return true; +} + +static void tegra_utc_rx_chars(struct tegra_utc_port *tup) +{ + struct tty_port *port =3D &tup->port.state->port; + unsigned int max_chars =3D 256; + unsigned int flag; + u32 status; + int sysrq; + u32 ch; + + while (--max_chars) { + status =3D tegra_utc_rx_readl(tup, TEGRA_UTC_FIFO_STATUS); + if (status & TEGRA_UTC_FIFO_EMPTY) + break; + + ch =3D tegra_utc_rx_readl(tup, TEGRA_UTC_DATA); + flag =3D TTY_NORMAL; + tup->port.icount.rx++; + + if (status & TEGRA_UTC_FIFO_OVERFLOW) + tup->port.icount.overrun++; + + uart_port_unlock(&tup->port); + sysrq =3D uart_handle_sysrq_char(&tup->port, ch & 0xff); + uart_port_lock(&tup->port); + + if (!sysrq) + tty_insert_flip_char(port, ch, flag); + } + + tty_flip_buffer_push(port); +} + +static irqreturn_t tegra_utc_isr(int irq, void *dev_id) +{ + struct tegra_utc_port *tup =3D dev_id; + unsigned long flags; + u32 status; + + uart_port_lock_irqsave(&tup->port, &flags); + + /* Process RX_REQ and RX_TIMEOUT interrupts. */ + do { + status =3D tegra_utc_rx_readl(tup, TEGRA_UTC_INTR_STATUS) & tup->rx_irqm= ask; + if (status) { + tegra_utc_rx_writel(tup, tup->rx_irqmask, TEGRA_UTC_INTR_CLEAR); + tegra_utc_rx_chars(tup); + } + } while (status); + + /* Process TX_REQ interrupt. */ + do { + status =3D tegra_utc_tx_readl(tup, TEGRA_UTC_INTR_STATUS) & tup->tx_irqm= ask; + if (status) { + tegra_utc_tx_writel(tup, tup->tx_irqmask, TEGRA_UTC_INTR_CLEAR); + tegra_utc_tx_chars(tup); + } + } while (status); + + uart_port_unlock_irqrestore(&tup->port, flags); + + return IRQ_HANDLED; +} + +static unsigned int tegra_utc_tx_empty(struct uart_port *port) +{ + struct tegra_utc_port *tup =3D container_of(port, struct tegra_utc_port, = port); + + return tegra_utc_tx_readl(tup, TEGRA_UTC_FIFO_OCCUPANCY) ? 0 : TIOCSER_TE= MT; +} + +static void tegra_utc_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ +} + +static unsigned int tegra_utc_get_mctrl(struct uart_port *port) +{ + return 0; +} + +static void tegra_utc_start_tx(struct uart_port *port) +{ + struct tegra_utc_port *tup =3D container_of(port, struct tegra_utc_port, = port); + + if (tegra_utc_tx_chars(tup)) + tegra_utc_enable_tx_irq(tup); +} + +static void tegra_utc_stop_rx(struct uart_port *port) +{ + struct tegra_utc_port *tup =3D container_of(port, struct tegra_utc_port, = port); + + tup->rx_irqmask =3D 0x0; + tegra_utc_rx_writel(tup, tup->rx_irqmask, TEGRA_UTC_INTR_MASK); + tegra_utc_rx_writel(tup, tup->rx_irqmask, TEGRA_UTC_INTR_SET); +} + +static void tegra_utc_hw_init(struct tegra_utc_port *tup) +{ + tegra_utc_init_tx(tup); + tegra_utc_init_rx(tup); +} + +static int tegra_utc_startup(struct uart_port *port) +{ + struct tegra_utc_port *tup =3D container_of(port, struct tegra_utc_port, = port); + int ret; + + tegra_utc_hw_init(tup); + + ret =3D request_irq(tup->irq, tegra_utc_isr, 0, dev_name(port->dev), tup); + if (ret < 0) { + dev_err(port->dev, "failed to register interrupt handler\n"); + return ret; + } + + return 0; +} + +static void tegra_utc_shutdown(struct uart_port *port) +{ + struct tegra_utc_port *tup =3D container_of(port, struct tegra_utc_port, = port); + + tegra_utc_rx_writel(tup, 0x0, TEGRA_UTC_ENABLE); + free_irq(tup->irq, tup); +} + +static void tegra_utc_set_termios(struct uart_port *port, struct ktermios = *termios, + const struct ktermios *old) +{ + /* The Tegra UTC clients supports only 8-N-1 configuration without HW flo= w control */ + termios->c_cflag &=3D ~(CSIZE | CSTOPB | PARENB | PARODD); + termios->c_cflag &=3D ~(CMSPAR | CRTSCTS); + termios->c_cflag |=3D CS8 | CLOCAL; +} + +#ifdef CONFIG_CONSOLE_POLL + +static int tegra_utc_poll_init(struct uart_port *port) +{ + struct tegra_utc_port *tup =3D container_of(port, struct tegra_utc_port, = port); + + tegra_utc_hw_init(tup); + return 0; +} + +static int tegra_utc_get_poll_char(struct uart_port *port) +{ + struct tegra_utc_port *tup =3D container_of(port, struct tegra_utc_port, = port); + + while (tegra_utc_rx_readl(tup, TEGRA_UTC_FIFO_STATUS) & TEGRA_UTC_FIFO_EM= PTY) + cpu_relax(); + + return tegra_utc_rx_readl(tup, TEGRA_UTC_DATA); +} + +static void tegra_utc_put_poll_char(struct uart_port *port, unsigned char = ch) +{ + struct tegra_utc_port *tup =3D container_of(port, struct tegra_utc_port, = port); + + while (tegra_utc_tx_readl(tup, TEGRA_UTC_FIFO_STATUS) & TEGRA_UTC_FIFO_FU= LL) + cpu_relax(); + + tegra_utc_tx_writel(tup, ch, TEGRA_UTC_DATA); +} + +#endif + +static const struct uart_ops tegra_utc_uart_ops =3D { + .tx_empty =3D tegra_utc_tx_empty, + .set_mctrl =3D tegra_utc_set_mctrl, + .get_mctrl =3D tegra_utc_get_mctrl, + .stop_tx =3D tegra_utc_stop_tx, + .start_tx =3D tegra_utc_start_tx, + .stop_rx =3D tegra_utc_stop_rx, + .startup =3D tegra_utc_startup, + .shutdown =3D tegra_utc_shutdown, + .set_termios =3D tegra_utc_set_termios, +#ifdef CONFIG_CONSOLE_POLL + .poll_init =3D tegra_utc_poll_init, + .poll_get_char =3D tegra_utc_get_poll_char, + .poll_put_char =3D tegra_utc_put_poll_char, +#endif +}; + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_UTC_CONSOLE) +#define TEGRA_UTC_DEFAULT_FIFO_THRESHOLD 0x4 +#define TEGRA_UTC_EARLYCON_MAX_BURST_SIZE 128 + +static void tegra_utc_putc(struct uart_port *port, unsigned char c) +{ + writel(c, port->membase + TEGRA_UTC_DATA); +} + +static void tegra_utc_early_write(struct console *con, const char *s, unsi= gned int n) +{ + struct earlycon_device *dev =3D con->data; + + while (n) { + u32 burst_size =3D TEGRA_UTC_EARLYCON_MAX_BURST_SIZE; + + burst_size -=3D readl(dev->port.membase + TEGRA_UTC_FIFO_OCCUPANCY); + if (n < burst_size) + burst_size =3D n; + + uart_console_write(&dev->port, s, burst_size, tegra_utc_putc); + + n -=3D burst_size; + s +=3D burst_size; + } +} + +static int __init tegra_utc_early_console_setup(struct earlycon_device *de= vice, const char *opt) +{ + if (!device->port.membase) + return -ENODEV; + + /* Configure TX */ + writel(TEGRA_UTC_COMMAND_FLUSH | TEGRA_UTC_COMMAND_RESET, + device->port.membase + TEGRA_UTC_COMMAND); + writel(TEGRA_UTC_DEFAULT_FIFO_THRESHOLD, device->port.membase + TEGRA_UTC= _FIFO_THRESHOLD); + + /* Clear and mask all the interrupts. */ + writel(TEGRA_UTC_INTR_REQ | TEGRA_UTC_INTR_FULL | TEGRA_UTC_INTR_EMPTY, + device->port.membase + TEGRA_UTC_INTR_CLEAR); + + writel(0x0, device->port.membase + TEGRA_UTC_INTR_MASK); + writel(0x0, device->port.membase + TEGRA_UTC_INTR_SET); + + /* Enable TX. */ + writel(TEGRA_UTC_ENABLE_CLIENT_ENABLE, device->port.membase + TEGRA_UTC_E= NABLE); + + device->con->write =3D tegra_utc_early_write; + + return 0; +} +OF_EARLYCON_DECLARE(tegra_utc, "nvidia,tegra264-utc", tegra_utc_early_cons= ole_setup); + +static void tegra_utc_console_putchar(struct uart_port *port, unsigned cha= r ch) +{ + struct tegra_utc_port *tup =3D container_of(port, struct tegra_utc_port, = port); + + tegra_utc_tx_writel(tup, ch, TEGRA_UTC_DATA); +} + +static void tegra_utc_console_write(struct console *cons, const char *s, u= nsigned int count) +{ + struct tegra_utc_port *tup =3D container_of(cons, struct tegra_utc_port, = console); + unsigned long flags; + int locked =3D 1; + + if (tup->port.sysrq || oops_in_progress) + locked =3D uart_port_trylock_irqsave(&tup->port, &flags); + else + uart_port_lock_irqsave(&tup->port, &flags); + + while (count) { + u32 burst_size =3D tup->soc->fifosize; + + burst_size -=3D tegra_utc_tx_readl(tup, TEGRA_UTC_FIFO_OCCUPANCY); + if (count < burst_size) + burst_size =3D count; + + uart_console_write(&tup->port, s, burst_size, tegra_utc_console_putchar); + + count -=3D burst_size; + s +=3D burst_size; + }; + + if (locked) + uart_port_unlock_irqrestore(&tup->port, flags); +} + +static int tegra_utc_console_setup(struct console *cons, char *options) +{ + struct tegra_utc_port *tup =3D container_of(cons, struct tegra_utc_port, = console); + + tegra_utc_init_tx(tup); + + return 0; +} +#endif + +static struct uart_driver tegra_utc_driver =3D { + .driver_name =3D "tegra-utc", + .dev_name =3D "ttyUTC", + .nr =3D UART_NR +}; + +static void tegra_utc_setup_port(struct device *dev, struct tegra_utc_port= *tup) +{ + tup->port.dev =3D dev; + tup->port.fifosize =3D tup->soc->fifosize; + tup->port.flags =3D UPF_BOOT_AUTOCONF; + tup->port.iotype =3D UPIO_MEM; + tup->port.ops =3D &tegra_utc_uart_ops; + tup->port.type =3D PORT_TEGRA_TCU; + tup->port.private_data =3D tup; + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_UTC_CONSOLE) + strscpy(tup->console.name, "ttyUTC", sizeof(tup->console.name)); + tup->console.write =3D tegra_utc_console_write; + tup->console.device =3D uart_console_device; + tup->console.setup =3D tegra_utc_console_setup; + tup->console.flags =3D CON_PRINTBUFFER | CON_CONSDEV | CON_ANYTIME; + tup->console.data =3D &tegra_utc_driver; +#endif + + uart_read_port_properties(&tup->port); +} + +static int tegra_utc_register_port(struct tegra_utc_port *tup) +{ + int ret; + + ret =3D uart_add_one_port(&tegra_utc_driver, &tup->port); + if (ret) + return ret; + +#if IS_ENABLED(CONFIG_SERIAL_TEGRA_UTC_CONSOLE) + register_console(&tup->console); +#endif + + return 0; +} + +static int tegra_utc_probe(struct platform_device *pdev) +{ + struct device_node *np =3D pdev->dev.of_node; + struct device *dev =3D &pdev->dev; + struct tegra_utc_port *tup; + int ret; + + tup =3D devm_kzalloc(&pdev->dev, sizeof(struct tegra_utc_port), GFP_KERNE= L); + if (!tup) + return -ENOMEM; + + ret =3D of_property_read_u32(np, "tx-threshold", &tup->tx_threshold); + if (ret) + return dev_err_probe(dev, ret, "missing tx-threshold device-tree propert= y\n"); + + ret =3D of_property_read_u32(np, "rx-threshold", &tup->rx_threshold); + if (ret) + return dev_err_probe(dev, ret, "missing rx-threshold device-tree propert= y\n"); + + tup->irq =3D platform_get_irq(pdev, 0); + if (tup->irq < 0) + return tup->irq; + + tup->soc =3D of_device_get_match_data(&pdev->dev); + + tup->tx_base =3D devm_platform_ioremap_resource_byname(pdev, "tx"); + if (IS_ERR(tup->tx_base)) + return PTR_ERR(tup->tx_base); + + tup->rx_base =3D devm_platform_ioremap_resource_byname(pdev, "rx"); + if (IS_ERR(tup->rx_base)) + return PTR_ERR(tup->rx_base); + + tegra_utc_setup_port(&pdev->dev, tup); + platform_set_drvdata(pdev, tup); + + return tegra_utc_register_port(tup); +} + +static void tegra_utc_remove(struct platform_device *pdev) +{ + struct tegra_utc_port *tup =3D platform_get_drvdata(pdev); + + uart_remove_one_port(&tegra_utc_driver, &tup->port); +} + +static const struct tegra_utc_soc tegra264_utc_soc =3D { + .fifosize =3D 128, +}; + +static const struct of_device_id tegra_utc_of_match[] =3D { + { .compatible =3D "nvidia,tegra264-utc", .data =3D &tegra264_utc_soc }, + {} +}; +MODULE_DEVICE_TABLE(of, tegra_utc_of_match); + +static struct platform_driver tegra_utc_platform_driver =3D { + .probe =3D tegra_utc_probe, + .remove =3D tegra_utc_remove, + .driver =3D { + .name =3D "tegra-utc", + .of_match_table =3D tegra_utc_of_match, + }, +}; + +static int __init tegra_utc_init(void) +{ + int ret; + + ret =3D uart_register_driver(&tegra_utc_driver); + if (ret) + return ret; + + ret =3D platform_driver_register(&tegra_utc_platform_driver); + if (ret) { + uart_unregister_driver(&tegra_utc_driver); + return ret; + } + + return 0; +} +module_init(tegra_utc_init); + +static void __exit tegra_utc_exit(void) +{ + platform_driver_unregister(&tegra_utc_platform_driver); + uart_unregister_driver(&tegra_utc_driver); +} +module_exit(tegra_utc_exit); + +MODULE_AUTHOR("Kartik Rajput "); +MODULE_DESCRIPTION("Tegra UART Trace Controller"); +MODULE_LICENSE("GPL"); --=20 2.43.0