From nobody Thu Dec 18 20:52:29 2025 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3536E1E98E0 for ; Tue, 11 Feb 2025 02:53:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739242424; cv=none; b=M3YhjnLAI0IVNMeMUiR8uca7aFwnVzYBy7jJyW+fGbCfGTPz8sgNU30AUFpuWmnpA/xVODfIoEvDi57GipYvtPktyIZJYlZaEi6o+VFg1cgQfHrM0CFhAlwjVXXlPGHIemWcicO3Mas8iqcdy15u09V+5jRGFwZgtIPZHi/cweg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739242424; c=relaxed/simple; bh=ywXnA3t3ELHvYfsaC0ppqh8nJdyRoHp1CaQzv4tzNHk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sW5ZLuMo7zMElZyptfoy8B0t5RCcyia2FGmuRVQ/fIBXwmMw2QlMeGDvvI/J7VQ+PpTLXX6bFlgXJU7NCuvNH1frA8QOUqctmJsfOFizGoTjNzrtGJ7KQXOUjElJLOTiUc3QVQEM2jK5CyPBLlOlnLKoOqeTudva9hW294N1zbU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=d7wAAjWd; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="d7wAAjWd" X-UUID: 637f24ece82311efbd192953cf12861f-20250211 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=Xf3YPNC1heVOAJxZqyxWo/MOXXbE2oMpczXgzqz6nhk=; b=d7wAAjWdjJ9T1n7LIh48Vf9mpC3CiCvtI3+85pn1InA8XIkwPrD/vdac9+m1K9MZ4lK0SCrUKzJMhPR9Tx4QZx/jiTwfq5oxmVWgKWN7B4SqZGAZ2OW5xue4g8jaX8m4m8MPkabwccZpG/SWnrDEgghYt0lP8PkDYw/sKGQza8w=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.46,REQID:6c4633f8-609c-475b-a00d-c771c500bbbc,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:60aa074,CLOUDID:2ed86b92-d651-4ec6-81e1-a3deb10c9ff8,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 637f24ece82311efbd192953cf12861f-20250211 Received: from mtkmbs14n2.mediatek.inc [(172.21.101.76)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 972286228; Tue, 11 Feb 2025 10:53:36 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Tue, 11 Feb 2025 10:53:34 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Tue, 11 Feb 2025 10:53:34 +0800 From: Sunny Shen To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chun-Kuang Hu , AngeloGioacchino Del Regno CC: Matthias Brugger , Philipp Zabel , Fei Shao , Pin-yen Lin , "Jason-JH . Lin" , "Nancy Lin" , Singo Chang , "Paul Chen --cc=devicetree @ vger . kernel . org" , , , , , , Sunny Shen Subject: [PATCH 4/5] drm/mediatek: Add MDP-RSZ component support for MT8196 Date: Tue, 11 Feb 2025 10:52:53 +0800 Message-ID: <20250211025317.399534-5-sunny.shen@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250211025317.399534-1-sunny.shen@mediatek.com> References: <20250211025317.399534-1-sunny.shen@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add MDP-RSZ component support for MT8196. Signed-off-by: Sunny Shen --- drivers/gpu/drm/mediatek/mtk_ddp_comp.c | 24 ++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_ddp_comp.h | 1 + drivers/gpu/drm/mediatek/mtk_drm_drv.c | 2 ++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.c index 7f09a8977965..65878d3fe8a9 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.c +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.c @@ -46,6 +46,10 @@ #define DSC_BYPASS BIT(4) #define DSC_UFOE_SEL BIT(16) =20 +#define DISP_REG_MDP_RSZ_EN 0x0000 +#define DISP_REG_MDP_RSZ_INPUT_SIZE 0x0010 +#define DISP_REG_MDP_RSZ_OUTPUT_SIZE 0x0014 + #define DISP_REG_OD_EN 0x0000 #define DISP_REG_OD_CFG 0x0020 #define OD_RELAYMODE BIT(0) @@ -235,6 +239,18 @@ static void mtk_od_start(struct device *dev) writel(1, priv->regs + DISP_REG_OD_EN); } =20 +static void mtk_mdp_rsz_config(struct device *dev, unsigned int w, + unsigned int h, unsigned int vrefresh, + unsigned int bpc, struct cmdq_pkt *cmdq_pkt) +{ + struct mtk_ddp_comp_dev *priv =3D dev_get_drvdata(dev); + + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MDP_RSZ_INPUT_SIZE); + mtk_ddp_write(cmdq_pkt, 0, &priv->cmdq_reg, priv->regs, + DISP_REG_MDP_RSZ_OUTPUT_SIZE); +} + static void mtk_postmask_config(struct device *dev, unsigned int w, unsigned int h, unsigned int vrefresh, unsigned int bpc, struct cmdq_pkt *cmdq_pkt) @@ -391,6 +407,12 @@ static const struct mtk_ddp_comp_funcs ddp_ovlsys_adap= tor =3D { .get_num_formats =3D mtk_ovlsys_adaptor_get_num_formats, }; =20 +static const struct mtk_ddp_comp_funcs ddp_mdp_rsz =3D { + .clk_enable =3D mtk_ddp_clk_enable, + .clk_disable =3D mtk_ddp_clk_disable, + .config =3D mtk_mdp_rsz_config, +}; + static const struct mtk_ddp_comp_funcs ddp_postmask =3D { .clk_enable =3D mtk_ddp_clk_enable, .clk_disable =3D mtk_ddp_clk_disable, @@ -454,6 +476,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COM= P_TYPE_MAX] =3D { [MTK_DISP_DITHER] =3D "dither", [MTK_DISP_DSC] =3D "dsc", [MTK_DISP_GAMMA] =3D "gamma", + [MTK_DISP_MDP_RSZ] =3D "mdp-rsz", [MTK_DISP_MERGE] =3D "merge", [MTK_DISP_MUTEX] =3D "mutex", [MTK_DISP_OD] =3D "od", @@ -515,6 +538,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[= DDP_COMPONENT_DRM_ID_MAX] [DDP_COMPONENT_DSI2] =3D { MTK_DSI, 2, &ddp_dsi }, [DDP_COMPONENT_DSI3] =3D { MTK_DSI, 3, &ddp_dsi }, [DDP_COMPONENT_GAMMA] =3D { MTK_DISP_GAMMA, 0, &ddp_gamma }, + [DDP_COMPONENT_MDP_RSZ0] =3D { MTK_DISP_MDP_RSZ, 0, &ddp_mdp_rsz}, [DDP_COMPONENT_MERGE0] =3D { MTK_DISP_MERGE, 0, &ddp_merge }, [DDP_COMPONENT_MERGE1] =3D { MTK_DISP_MERGE, 1, &ddp_merge }, [DDP_COMPONENT_MERGE2] =3D { MTK_DISP_MERGE, 2, &ddp_merge }, diff --git a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h b/drivers/gpu/drm/medi= atek/mtk_ddp_comp.h index badb42bd4f7c..87f573fcc903 100644 --- a/drivers/gpu/drm/mediatek/mtk_ddp_comp.h +++ b/drivers/gpu/drm/mediatek/mtk_ddp_comp.h @@ -36,6 +36,7 @@ enum mtk_ddp_comp_type { MTK_DISP_OVLSYS_ADAPTOR, MTK_DISP_OVL_2L, MTK_DISP_OVL_ADAPTOR, + MTK_DISP_MDP_RSZ, MTK_DISP_POSTMASK, MTK_DISP_PWM, MTK_DISP_RDMA, diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/media= tek/mtk_drm_drv.c index 50f5f81a7da1..b810a197f58b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c @@ -885,6 +885,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = =3D { .data =3D (void *)MTK_DISP_GAMMA, }, { .compatible =3D "mediatek,mt8195-disp-gamma", .data =3D (void *)MTK_DISP_GAMMA, }, + { .compatible =3D "mediatek,mt8196-disp-mdp-rsz", + .data =3D (void *)MTK_DISP_MDP_RSZ }, { .compatible =3D "mediatek,mt8195-disp-merge", .data =3D (void *)MTK_DISP_MERGE }, { .compatible =3D "mediatek,mt2701-disp-mutex", --=20 2.34.1