From nobody Sun Dec 14 06:18:06 2025 Received: from smtp-42af.mail.infomaniak.ch (smtp-42af.mail.infomaniak.ch [84.16.66.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1FC8624C671 for ; Tue, 11 Feb 2025 14:03:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.66.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739282600; cv=none; b=VObsldXyNoKqnRBDIJAdZjeiiQK3uu2R4g50VfRcWmuLwdxV0h82KPKO1s8hOsCkbtTvIgn87n04wUMrS/6Yf/Y0yS33sH6IkBTMgbkpjRiTXbrO0PhjQgteOo+oe56OGMIfh/tXbyAZJb4ip8x5I77idBhIgUF0/m74C4Yn6G8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739282600; c=relaxed/simple; bh=cj93YJcehxCrIk/VMANrSZnFRFIooTlrM0Ptrbg8l6Y=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fqCsYh6n0WU/VuysZzdpbzjDLKrsRrQaHkh7mLVa+Rw2WHv5RSjO+Hn1K95ZBbnrcC2wubNKscgRTNZIWPuX0Dd2oCHrEku908D93o3RI3/W9n0emhcqfvly8tls2lOIQ5+EhUeGrgkbiVl5Uvk0JuLl04JmMnnG7sQ3W1eMiro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=84.16.66.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0001.mail.infomaniak.ch (unknown [IPv6:2001:1600:7:10:40ca:feff:fe05:1]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YsjpD0Z3VzD0X; Tue, 11 Feb 2025 15:03:16 +0100 (CET) Received: from unknown by smtp-4-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4YsjpB6m75zSln; Tue, 11 Feb 2025 15:03:14 +0100 (CET) From: Quentin Schulz Date: Tue, 11 Feb 2025 15:02:50 +0100 Subject: [PATCH v6 1/4] arm64: dts: rockchip: add overlay test for WolfVision PF5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250211-pre-ict-jaguar-v6-1-4484b0f88cfc@cherry.de> References: <20250211-pre-ict-jaguar-v6-0-4484b0f88cfc@cherry.de> In-Reply-To: <20250211-pre-ict-jaguar-v6-0-4484b0f88cfc@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jagan Teki , Niklas Cassel , Michael Riesch Cc: Jonas Karlman , Dragan Simic , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The WolfVision PF5 can have a PF5 Visualizer display and PF5 IO Expander board connected to it. Therefore, let's generate an overlay test so the application of the two overlays are validated against the base DTB. Suggested-by: Michael Riesch Reviewed-by: Michael Riesch Reviewed-by: Dragan Simic Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/Makefile | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index def1222c1907eb16b23cff6d540174a4e897abc9..55fe706612d3ec07c2d9df9e4cd= 1e4cc54cc1c44 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -170,3 +170,25 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-orangepi-5.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-orangepi-5b.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588s-rock-5c.dtb + +# Overlay application tests +# +# A .dtbo must have its own +# +# dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D .dtbo +# +# entry, and at least one overlay application test reflecting a possible +# hardware combination in real life: +# +# dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D .dtb +# -dtbs :=3D .dtb .dtbo [.dtbo ...] +# +# This will make the .dtb have symbols (like when DTC_FLAGS has -@ p= assed) +# and generate a new DTB (.dtb) which is the +# result of the application of .dtbo and other listed overlays = on top +# of .dtb. + +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5-vz-2-uhd.dtb +rk3568-wolfvision-pf5-vz-2-uhd-dtbs :=3D rk3568-wolfvision-pf5.dtb \ + rk3568-wolfvision-pf5-display-vz.dtbo \ + rk3568-wolfvision-pf5-io-expander.dtbo --=20 2.48.1 From nobody Sun Dec 14 06:18:06 2025 Received: from smtp-1909.mail.infomaniak.ch (smtp-1909.mail.infomaniak.ch [185.125.25.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54CDA24C67A for ; Tue, 11 Feb 2025 14:03:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.125.25.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739282601; cv=none; b=QQkrLiG0eiu5HhatO3PEBrUos1M1PTA2REonfI6pnEIWahYsplipmCy0ABG4mhbgXhKW7Ox+nwvCp9tELYNxUty9LfOjA2UxVcYEwtN5YA0svN9kOBV1AxzSe1GzzByCiTj0P+Ftf9OlevdzvxSeLziQ3nyZSgVk5YJRYejdV6w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739282601; c=relaxed/simple; bh=BlYp5T7rHQ9tm+2AZREmSqkNH7doQoIqX4UDI5fOvV8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JwqEAYKOfRA60KSHmsvL7ogNUugcAyIe+ijGY1d1DwM2hJXZwR8H4UBMmyofqvdaLFOMpIPliXDNTnW+mvBDmdgAf1uuhldNrg4mzncj4veucvT3x0iHQBdaPGpxZ6dtRGgY+GBBGJxduoR8pY5EQysTXOyps20mMNV6epG27fQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=185.125.25.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0001.mail.infomaniak.ch (unknown [IPv6:2001:1600:7:10:40ca:feff:fe05:1]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YsjpF3Gf0z9W7; Tue, 11 Feb 2025 15:03:17 +0100 (CET) Received: from unknown by smtp-4-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4YsjpD1NkhzTvn; Tue, 11 Feb 2025 15:03:16 +0100 (CET) From: Quentin Schulz Date: Tue, 11 Feb 2025 15:02:51 +0100 Subject: [PATCH v6 2/4] arm64: dts: rockchip: add overlay test for Edgeble NCM6A/NCM6B Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250211-pre-ict-jaguar-v6-2-4484b0f88cfc@cherry.de> References: <20250211-pre-ict-jaguar-v6-0-4484b0f88cfc@cherry.de> In-Reply-To: <20250211-pre-ict-jaguar-v6-0-4484b0f88cfc@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jagan Teki , Niklas Cassel , Michael Riesch Cc: Jonas Karlman , Dragan Simic , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The Edgeble NCM6A/NCM6B can have WiFi modules connected and this is handled via an overlay (commit 951d6aaa37fe ("arm64: dts: rockchip: Add Edgeble NCM6A WiFi6 Overlay")). Despite the name of the overlay, it applies to both NCM6A and NCM6B[1]. In order to make sure the overlay is still valid in the future, let's add a validation test by applying the overlay on top of the main bases at build time. [1] https://lore.kernel.org/linux-rockchip/CA+VMnFyom=3D2BmJ_nt-At6hTQP0v+A= uaw-DkCVbT9mjndMmLKtQ@mail.gmail.com/ Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dragan Simic Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 55fe706612d3ec07c2d9df9e4cd1e4cc54cc1c44..1406d9df57f8ce589217730f836= b4e222b1e0d26 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -192,3 +192,11 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3568-wolfvision-pf5= -vz-2-uhd.dtb rk3568-wolfvision-pf5-vz-2-uhd-dtbs :=3D rk3568-wolfvision-pf5.dtb \ rk3568-wolfvision-pf5-display-vz.dtbo \ rk3568-wolfvision-pf5-io-expander.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6a-wifi.dtb +rk3588-edgeble-neu6a-wifi-dtbs :=3D rk3588-edgeble-neu6a-io.dtb \ + rk3588-edgeble-neu6a-wifi.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6b-wifi.dtb +rk3588-edgeble-neu6b-wifi-dtbs :=3D rk3588-edgeble-neu6b-io.dtb \ + rk3588-edgeble-neu6a-wifi.dtbo --=20 2.48.1 From nobody Sun Dec 14 06:18:06 2025 Received: from smtp-42af.mail.infomaniak.ch (smtp-42af.mail.infomaniak.ch [84.16.66.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A34F24C66D for ; Tue, 11 Feb 2025 14:03:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.66.175 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739282602; cv=none; b=ErAGWWw2lXXpV/QhLTXyvuy1xXEGMfcDVZQlCVsyTjfm8MTcEoPd07rQ8sTLKcew4xUzeiSdAwTVCF0vvkfWsRcQ78g0NGcrbdr6fyIIuLGH+nXGFvajJNRMbqUekpfCs9+hJ+1iLE5bsWdyeVquEDLq39SS/TbLSutd1zpa950= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739282602; c=relaxed/simple; bh=38SzZjtaSSJ8VTC/qk48nzlF2mAAeFz1rRcmoBtR5AE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZhB0ZKTgV1wbU/ldGuzst4xTCzaf6DtjhTMuVkOwmTlZpYI2XUiUfvijMOjktcL6bvFuIZjde2ax/bhoNmMXwbDyzv3fbslH+3C/7Xr7hQ+aawtsou/RoyLkK20AbtvUP8boq1Te4nHhYFSkSCUxUxC3zUHpPWB8cdzyg4j9Mng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=84.16.66.175 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0001.mail.infomaniak.ch (smtp-4-0001.mail.infomaniak.ch [10.7.10.108]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YsjpG45V0zChv; Tue, 11 Feb 2025 15:03:18 +0100 (CET) Received: from unknown by smtp-4-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4YsjpF3VQ1zTLG; Tue, 11 Feb 2025 15:03:17 +0100 (CET) From: Quentin Schulz Date: Tue, 11 Feb 2025 15:02:52 +0100 Subject: [PATCH v6 3/4] arm64: dts: rockchip: add overlay tests for Rock 5B PCIe overlays Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250211-pre-ict-jaguar-v6-3-4484b0f88cfc@cherry.de> References: <20250211-pre-ict-jaguar-v6-0-4484b0f88cfc@cherry.de> In-Reply-To: <20250211-pre-ict-jaguar-v6-0-4484b0f88cfc@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jagan Teki , Niklas Cassel , Michael Riesch Cc: Jonas Karlman , Dragan Simic , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz According to commit 40658534756f ("arm64: dts: rockchip: Add rock5b overlays for PCIe endpoint mode"), Rock 5B can operate in PCIe endpoint mode. For that to work, the rk3588-rock-5b-pcie-ep.dtbo overlay needs to be applied on Rock 5B base Device Tree. If that Rock 5B is connected to another Rock 5B, the latter needs to apply the rk3588-rock-5b-pcie-srns.dtbo overlay. In order to make sure the overlays are still valid in the future, let's add a validation test by applying the overlays on top of the main base at build time. Reviewed-by: Krzysztof Kozlowski Reviewed-by: Niklas Cassel Reviewed-by: Dragan Simic Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 1406d9df57f8ce589217730f836b4e222b1e0d26..2cec67c00114b16ca55c12fa8f7= 57a015c4602ad 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -200,3 +200,11 @@ rk3588-edgeble-neu6a-wifi-dtbs :=3D rk3588-edgeble-neu= 6a-io.dtb \ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6b-wifi.dtb rk3588-edgeble-neu6b-wifi-dtbs :=3D rk3588-edgeble-neu6b-io.dtb \ rk3588-edgeble-neu6a-wifi.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b-pcie-ep.dtb +rk3588-rock-5b-pcie-ep-dtbs :=3D rk3588-rock-5b.dtb \ + rk3588-rock-5b-pcie-ep.dtbo + +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b-pcie-srns.dtb +rk3588-rock-5b-pcie-srns-dtbs :=3D rk3588-rock-5b.dtb \ + rk3588-rock-5b-pcie-srns.dtbo --=20 2.48.1 From nobody Sun Dec 14 06:18:06 2025 Received: from smtp-8fab.mail.infomaniak.ch (smtp-8fab.mail.infomaniak.ch [83.166.143.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7F8C253347 for ; Tue, 11 Feb 2025 14:03:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=83.166.143.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739282610; cv=none; b=d9E+RiNY+udOYtm/m+41POShVUFBAlbjW0uWdk2EJxyB8zOr1Dt5POaHgYfoyZyQmUUHuXbJ15SpmLzgz4X54Gd6jZyq45RR0BHHdcJJnAcLQYvKpD2NT15CP9Qp578ZWwInBfzS4pFRIqGfs9nqTEaIpgzdWaX2UI9n183aVgE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739282610; c=relaxed/simple; bh=HYRvqKAoGKmiER+ZQHRN5JJ+XylNhpE6RiGjytFynUE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mONt87wB87dC6+VPs6+Q1ihsZs0N9BKTBZJbFrEgzCllJJOPHN/ZK42ooKhQ8VwgtSui6fCyLgCmn368D3LfKf03HzrRYDIFE535ej92npkfXHsyVn06LX3YVSFhJE69ASuQu+cagpNle9sZfYg6BpLZVmYXRJGDftMsefFnTTw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=83.166.143.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-4-0001.mail.infomaniak.ch (smtp-4-0001.mail.infomaniak.ch [10.7.10.108]) by smtp-4-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4YsjpH5KFFz1C9p; Tue, 11 Feb 2025 15:03:19 +0100 (CET) Received: from unknown by smtp-4-0001.mail.infomaniak.ch (Postfix) with ESMTPA id 4YsjpG4hsFzT0m; Tue, 11 Feb 2025 15:03:18 +0100 (CET) From: Quentin Schulz Date: Tue, 11 Feb 2025 15:02:53 +0100 Subject: [PATCH v6 4/4] arm64: dts: rockchip: minimal support for Pre-ICT tester adapter for RK3588 Jaguar Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250211-pre-ict-jaguar-v6-4-4484b0f88cfc@cherry.de> References: <20250211-pre-ict-jaguar-v6-0-4484b0f88cfc@cherry.de> In-Reply-To: <20250211-pre-ict-jaguar-v6-0-4484b0f88cfc@cherry.de> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Jagan Teki , Niklas Cassel , Michael Riesch Cc: Jonas Karlman , Dragan Simic , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The Pre-ICT tester adapter connects to RK3588 Jaguar SBC through its proprietary Mezzanine connector. It exposes a PCIe Gen2 1x M.2 connector and two proprietary camera connectors. Support for the latter will come once the rest of the camera stack is supported. Additionally, the adapter loops some GPIOs together as well as route some GPIOs to power rails. This adapter is used for manufacturing RK3588 Jaguar to be able to test the Mezzanine connector is properly soldered. Acked-by: Krzysztof Kozlowski Reviewed-by: Dragan Simic # Makefile Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/Makefile | 5 + .../dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso | 171 +++++++++++++++++= ++++ 2 files changed, 176 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/ro= ckchip/Makefile index 2cec67c00114b16ca55c12fa8f757a015c4602ad..ddc1898618da3e9c797b54a5ba4= 5760c3e8fbc06 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -145,6 +145,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-firefly-itx-358= 8j.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-friendlyelec-cm3588-nas.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-h96-max-v58.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-jaguar.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-jaguar-pre-ict-tester.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-nanopc-t6-lts.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-ok3588-c.dtb @@ -201,6 +202,10 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-edgeble-neu6b-= wifi.dtb rk3588-edgeble-neu6b-wifi-dtbs :=3D rk3588-edgeble-neu6b-io.dtb \ rk3588-edgeble-neu6a-wifi.dtbo =20 +dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-jaguar-pre-ict-tester.dtb +rk3588-jaguar-pre-ict-tester-dtbs :=3D rk3588-jaguar.dtb \ + rk3588-jaguar-pre-ict-tester.dtbo + dtb-$(CONFIG_ARCH_ROCKCHIP) +=3D rk3588-rock-5b-pcie-ep.dtb rk3588-rock-5b-pcie-ep-dtbs :=3D rk3588-rock-5b.dtb \ rk3588-rock-5b-pcie-ep.dtbo diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso= b/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso new file mode 100644 index 0000000000000000000000000000000000000000..9d44dfe2f30d793accb994a230c= 58038f0c3daad --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar-pre-ict-tester.dtso @@ -0,0 +1,171 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2024 Cherry Embedded Solutions GmbH + * + * Device Tree Overlay for the Pre-ICT tester adapter for the Mezzanine + * connector on RK3588 Jaguar. + * + * This adapter has a PCIe Gen2 x1 M.2 M-Key connector and two proprietary + * camera connectors (each their own I2C bus, clock, reset and PWM lines a= s well + * as 2-lane CSI). + * + * This adapter routes some GPIOs to power rails and loops together some o= ther + * GPIOs. + * + * This adapter is used during manufacturing for validating proper solderi= ng of + * the mezzanine connector. + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&{/} { + pre_ict_tester_vcc_1v2: regulator-pre-ict-tester-vcc-1v2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pre_ict_tester_vcc_1v2"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + vin-supply =3D <&vcc_3v3_s3>; + }; + + pre_ict_tester_vcc_2v8: regulator-pre-ict-tester-vcc-2v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "pre_ict_tester_vcc_2v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + vin-supply =3D <&vcc_3v3_s3>; + }; +}; + +&combphy0_ps { + status =3D "okay"; +}; + +&gpio3 { + pinctrl-0 =3D <&pre_ict_pwr2gpio>; + pinctrl-names =3D "default"; +}; + +&pcie2x1l2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie2x1l2_perstn_m0>; + reset-gpios =3D <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>; /* PCIE20X1_2_PERSTN_M0= */ + vpcie3v3-supply =3D <&vcc_3v3_s3>; + status =3D "okay"; +}; + +&pinctrl { + pcie2x1l2 { + pcie2x1l2_perstn_m0: pcie2x1l2-perstn-m0 { + rockchip,pins =3D <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pre-ict-tester { + pre_ict_pwr2gpio: pre-ict-pwr2gpio-pins { + rockchip,pins =3D + /* + * GPIO3_A3 requires two power rails to be properly + * routed to the mezzanine connector to report a proper + * value: VCC_1V8_S0_1 and VCC_IN_2. It may report an + * incorrect value if VCC_1V8_S0_1 isn't properly routed, + * but GPIO3_C6 would catch this HW soldering issue. + * If VCC_IN_2 is properly routed, GPIO3_A3 should be + * LOW. The signal shall not read HIGH in the event + * GPIO3_A3 isn't properly routed due to soldering + * issue. Therefore, let's enforce a pull-up (which is + * the SoC default for this pin). + */ + <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>, + /* + * GPIO3_A4 is directly routed to VCC_1V8_S0_2 power + * rail. It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_B2 requires two power rails to be properly + * routed to the mezzanine connector to report a proper + * value: VCC_1V8_S0_1 and VCC_IN_1. It may report an + * incorrect value if VCC_1V8_S0_1 isn't properly routed, + * but GPIO3_C6 would catch this HW soldering issue. + * If VCC_IN_1 is properly routed, GPIO3_B2 should be + * LOW. This is an issue if GPIO3_B2 isn't properly + * routed due to soldering issue, because GPIO3_B2 + * default bias is pull-down therefore being LOW. So + * the worst case scenario and the pass scenario expect + * the same value. Make GPIO3_B2 a pull-up so that a + * soldering issue on GPIO3_B2 reports HIGH but proper + * soldering reports LOW. + */ + <3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>, + /* + * GPIO3_C6 is directly routed to VCC_1V8_S0_1 power + * rail. It should be HIGH if all is properly soldered. + * This is an issue if GPIO3_C6 or VCC_1V8_S0_1 isn't + * properly routed due to soldering issue, because + * GPIO3_C6 default bias is pull-up therefore being HIGH + * in all cases: + * - GPIO3_C6 is floating (so HIGH) if GPIO3_C6 is not + * routed properly, + * - GPIO3_C6 is floating (so HIGH) if VCC_1V8_S0_1 is + * not routed properly, + * - GPIO3_C6 is HIGH if everything is proper, + * Make GPIO3_C6 a pull-down so that a soldering issue + * on GPIO3_C6 or VCC_1V8_S0_1 reports LOW but proper + * soldering reports HIGH. + */ + <3 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D2 is routed to VCC_5V0_1 power rail through a + * voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD2 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D3 is routed to VCC_5V0_2 power rail through a + * voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD3 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D4 is routed to VCC_3V3_S3_1 power rail through + * a voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_down>, + /* + * GPIO3_D5 is routed to VCC_3V3_S3_2 power rail through + * a voltage divider on the adapter. + * It should be HIGH if all is properly soldered. + * To guarantee that, a pull-down is enforced (which is + * the SoC default for this pin) so that LOW is read if + * the loop doesn't exist on HW (soldering issue on + * either signals). + */ + <3 RK_PD5 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; --=20 2.48.1