From nobody Sun Feb 8 12:38:00 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B728B250BE6; Mon, 10 Feb 2025 22:15:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225750; cv=none; b=mvtfnBQ8MNK3SmiZ7gyN4Q8rm3V48TtwkLZXasGsgruHsgX/f/18kofpWyJsKSuy8lMaTin51UlmPEdpMn41X1VPi09yJFG8nioWhFqkWKf53dCphu7fka7SC++kitiNS3J8y9T++AjuYVOJAzaEKfF5DIAHgG0nkpKEI4PUP+M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225750; c=relaxed/simple; bh=XSpcflgCQNC7uM4YnXEz/9VGuEZBndpWx+5hMMuoiN8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ZqE5Sbh73DQrctBc2f576lvymPCu7RA9YePuWr2rzsqgu6S7PqueGglAGHnv49Zdb4PXOdC7HZFcIXeT4E15TZHRH5mhWyZQn38rNQ9ZNinvfIsRsQ2Lya/P2ZPwXkWEgVk/rPCPFapMFlN7T+wYh9PNVzu9+Sj/uh5wRAimSYE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=y0v4/Vcp; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="y0v4/Vcp" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 51AMFULu3488412 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Feb 2025 16:15:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1739225731; bh=aL9J74Vel71LiNS3iDg6i9WxqILS7UqUi38OSiBvDXs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=y0v4/VcptxpoyCtgLJ3obfsAww9hKw4oIq61zui/+3p/iHM8DOohKupdGubS1oM7E W0xdGAKvb53TlBWEYpZoQc2iGna06A5Qo61wwsbMENUgEjTA8ezDgxpOu6OjUY8Joc AQZUBjp1b6587DpkWSRTek7IifwIOM9U9NkqdPDc= Received: from DFLE102.ent.ti.com (dfle102.ent.ti.com [10.64.6.23]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 51AMFUDT113603 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 10 Feb 2025 16:15:30 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 10 Feb 2025 16:15:30 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 10 Feb 2025 16:15:30 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51AMFUZ3112628; Mon, 10 Feb 2025 16:15:30 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v5 01/10] arm64: dts: ti: k3-am62-wakeup: Add wakeup R5F node Date: Mon, 10 Feb 2025 16:15:21 -0600 Message-ID: <20250210221530.1234009-2-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250210221530.1234009-1-jm@ti.com> References: <20250210221530.1234009-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla AM62 SoC devices have a single core R5F processor in wakeup domain. The R5F processor in wakeup domain is used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Acked-by: Andrew Davis --- Changes since v4: - No change --- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-wakeup.dtsi index 9b8a1f85aa15c..061819a64300f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -106,6 +106,31 @@ wkup_rti0: watchdog@2b000000 { status =3D "reserved"; }; =20 + wkup_r5fss0: r5fss@78000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains =3D <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names =3D "atcm", "btcm"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <121>; + ti,sci-proc-ids =3D <0x01 0xff>; + resets =3D <&k3_reset 121 1>; + firmware-name =3D "am62-wkup-r5f0_0-fw"; + ti,atcm-enable =3D <1>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <1>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible =3D "ti,j7200-vtm"; reg =3D <0x00 0xb00000 0x00 0x400>, --=20 2.48.0 From nobody Sun Feb 8 12:38:00 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C2B46253F33; Mon, 10 Feb 2025 22:15:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225756; cv=none; b=r05JWIDZEmcKrsinx7RuE/SEkpV1nvdid4pz40ruAFOXGuWp/2tHAd7B4qXf+7/fHyT3znW+7V2GhveFnDg3/qQpPcbcyc9BR48b9zARC3vOOzln48poMBjcUubdyLWwGpwGWKLGsr+TRNuGKRZf2iwU0tNjNmtL3T/ueyZLk2k= ARC-Message-Signature: i=1; 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Mon, 10 Feb 2025 16:15:30 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51AMFUZ4112628; Mon, 10 Feb 2025 16:15:30 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v5 02/10] arm64: dts: ti: k3-am62a-mcu: Add R5F remote proc node Date: Mon, 10 Feb 2025 16:15:22 -0600 Message-ID: <20250210221530.1234009-3-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250210221530.1234009-1-jm@ti.com> References: <20250210221530.1234009-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla AM62A SoCs have a single R5F core in the MCU voltage domain. Add the R5FSS node with the child node for core0 in MCU voltage domain .dtsi file. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Acked-by: Andrew Davis --- Changes since v4: - Drop SRAM node for am62ax MCU R5fSS0 core0 --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62a-mcu.dtsi index 0469c766b769e..1178cc6a9be8c 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -175,4 +175,29 @@ mcu_mcan1: can@4e18000 { bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; status =3D "disabled"; }; + + mcu_r5fss0: r5fss@79000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains =3D <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + mcu_r5fss0_core0: r5f@79000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names =3D "atcm", "btcm"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <9>; + ti,sci-proc-ids =3D <0x03 0xff>; + resets =3D <&k3_reset 9 1>; + firmware-name =3D "am62a-mcu-r5f0_0-fw"; + ti,atcm-enable =3D <0>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <0>; + }; + }; }; --=20 2.48.0 From nobody Sun Feb 8 12:38:00 2026 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B4C124C699; Mon, 10 Feb 2025 22:15:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225748; cv=none; b=V+vTY5pVj+IXyf88xPvM0wkM7H15omtB6sMftdC81J39yz1lYrzT14vopIW8QrxnO4ljhljVcxID/ytdyThHfiMG8ejzmwbTyRmRnADM0zXBagY8zZD6Yygckr7X41kht4YefrPlQ0oq99Vi5vfhdKoAqFHTHkWu5hbYZCRIHBs= ARC-Message-Signature: i=1; a=rsa-sha256; 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Mon, 10 Feb 2025 16:15:30 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51AMFUZ5112628; Mon, 10 Feb 2025 16:15:30 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v5 03/10] arm64: dts: ti: k3-am62a-wakeup: Add R5F device node Date: Mon, 10 Feb 2025 16:15:23 -0600 Message-ID: <20250210221530.1234009-4-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250210221530.1234009-1-jm@ti.com> References: <20250210221530.1234009-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Devarsh Thakkar AM62A SoCs have a single R5F core in wakeup domain. This core is also used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Acked-by: Andrew Davis --- Changes since v4: - No change --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 25 +++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index b2c8f53517438..785b9f00033a4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -103,6 +103,31 @@ wkup_rti0: watchdog@2b000000 { status =3D "reserved"; }; =20 + wkup_r5fss0: r5fss@78000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains =3D <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names =3D "atcm", "btcm"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <121>; + ti,sci-proc-ids =3D <0x01 0xff>; + resets =3D <&k3_reset 121 1>; + firmware-name =3D "am62a-wkup-r5f0_0-fw"; + ti,atcm-enable =3D <1>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <1>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible =3D "ti,j7200-vtm"; reg =3D <0x00 0xb00000 0x00 0x400>, --=20 2.48.0 From nobody Sun Feb 8 12:38:00 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A15621D432D; Mon, 10 Feb 2025 22:15:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225748; cv=none; b=Sfl6iqWdkZ/yurPFsQ7vJSVxhsn3zDM3TxsGPM30O2o6oovYcBLcXoDWwEFO4hkdV8T9BEd9SkkH6paTus0F1yXpRGhHNDJeHv7X6ga3JT6fMKHxNcJ2zm9RnwzUwHfWFUF+vccovGVB5B5+84jESQoK7DpLjWotuAVgjMn1rKk= ARC-Message-Signature: i=1; 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Mon, 10 Feb 2025 16:15:30 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51AMFUZ6112628; Mon, 10 Feb 2025 16:15:30 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v5 04/10] arm64: dts: ti: k3-am62a-main: Add C7xv device node Date: Mon, 10 Feb 2025 16:15:24 -0600 Message-ID: <20250210221530.1234009-5-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250210221530.1234009-1-jm@ti.com> References: <20250210221530.1234009-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra AM62A SoCs have a C7xv DSP subsystem with Analytics engine capability. This subsystem is intended for deep learning purposes. Define the device node for C7xv DSP. Signed-off-by: Jai Luthra Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Acked-by: Andrew Davis --- Changes since v4: - No change --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index a1daba7b1fad5..f6ebc4eabaf14 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -1123,6 +1123,18 @@ vpu: video-codec@30210000 { power-domains =3D <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; }; =20 + c7x_0: dsp@7e000000 { + compatible =3D "ti,am62a-c7xv-dsp"; + reg =3D <0x00 0x7e000000 0x00 0x00100000>; + reg-names =3D "l2sram"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <208>; + ti,sci-proc-ids =3D <0x04 0xff>; + resets =3D <&k3_reset 208 1>; + firmware-name =3D "am62a-c71_0-fw"; + status =3D "disabled"; + }; + e5010: jpeg-encoder@fd20000 { compatible =3D "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc"; reg =3D <0x00 0xfd20000 0x00 0x100>, --=20 2.48.0 From nobody Sun Feb 8 12:38:00 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3C15224C69B; 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charset="utf-8" From: Devarsh Thakkar For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez Acked-by: Andrew Davis --- Changes since v4: - Add "status =3D okay" for mailbox nodes at the board level, disabling of mailbox nodes in voltage domain .dtsi files will come in a separate series --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 96 +++++++++++++++++++++++-- 1 file changed, 90 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index a6f0d87a50d8a..ac67c51caa211 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -49,6 +49,42 @@ linux,cma { linux,cma-default; }; =20 + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0x1e00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -60,12 +96,6 @@ secure_ddr: optee@9e800000 { alignment =3D <0x1000>; no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; =20 opp-table { @@ -737,3 +767,57 @@ dpi1_out: endpoint { }; }; }; + +&mailbox0_cluster0 { + status =3D "okay"; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; 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charset="utf-8" From: Devarsh Thakkar For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v4: - Drop SRAM node for am62px MCU R5fSS0 core0 --- arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 50 ++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index ad71d2f27f538..9609727d042d3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -48,6 +48,30 @@ reserved-memory { #size-cells =3D <2>; ranges; =20 + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000= { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0x1e00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; no-map; @@ -57,12 +81,6 @@ secure_ddr: optee@9e800000 { reg =3D <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; =20 vmain_pd: regulator-0 { @@ -638,6 +656,26 @@ mbox_mcu_r5_0: mbox-mcu-r5-0 { }; }; =20 +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + &main_uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; --=20 2.48.0 From nobody Sun Feb 8 12:38:00 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03F1C253340; Mon, 10 Feb 2025 22:15:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225753; cv=none; b=LvjCSineIIIYd/fEnVc4ICmj/hTB1LDHdkwQhVmmJe/ygMyLW2kCh7qYl7Uwg9Mqc6ixdQM5QAe8c7ejb8yrzy8tOIFdZCht6AfwYf/6NQl2h25v9yQeEmKZk4/sIfKN5EVtiT+co3OPvSa45IQEnS7AbB93Pf8hypcRjWJpijA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225753; c=relaxed/simple; bh=jjShB/C/71HFVkwO+cdgiFF/Emn+3dl1WcMVk/EQmBo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; 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Mon, 10 Feb 2025 16:15:30 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51AMFUZ9112628; Mon, 10 Feb 2025 16:15:30 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v5 07/10] arm64: dts: ti: k3-am62x-sk-common: Enable IPC with remote processors Date: Mon, 10 Feb 2025 16:15:27 -0600 Message-ID: <20250210221530.1234009-8-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250210221530.1234009-1-jm@ti.com> References: <20250210221530.1234009-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v4: - Add "status =3D okay" for mailbox nodes at the board level, disabling of mailbox nodes in voltage domain .dtsi files will come in a separate series --- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 34 ++++++++++++++++--- 1 file changed, 29 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 2f129e8cd5b9f..17791663abc65 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -68,6 +68,18 @@ mcu_m4fss_memory_region: m4f-memory@9cc00000 { no-map; }; =20 + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -80,11 +92,6 @@ secure_ddr: optee@9e800000 { no-map; }; =20 - wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9db00000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9db00000 0x00 0xc00000>; - no-map; - }; }; =20 leds { @@ -474,10 +481,17 @@ cpsw3g_phy0: ethernet-phy@0 { }; =20 &mailbox0_cluster0 { + status =3D "okay"; + mbox_m4_0: mbox-m4-0 { ti,mbox-rx =3D <0 0 0>; ti,mbox-tx =3D <1 0 0>; }; + + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <2 0 0>; + ti,mbox-tx =3D <3 0 0>; + }; }; =20 &mcu_m4fss { @@ -487,6 +501,16 @@ &mcu_m4fss { status =3D "okay"; }; =20 +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + &usbss0 { bootph-all; status =3D "okay"; --=20 2.48.0 From nobody Sun Feb 8 12:38:00 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D88FF253335; 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charset="utf-8" From: Hari Nagalla C7x DSP uses main_timer2, so mark it as reserved in linux DT. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v4: - No change --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index ac67c51caa211..11390a8742453 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -679,6 +679,11 @@ &main_uart1 { status =3D "reserved"; }; =20 +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status =3D "reserved"; +}; + &usbss0 { status =3D "okay"; ti,vbus-divider; --=20 2.48.0 From nobody Sun Feb 8 12:38:00 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9FD42505AE; Mon, 10 Feb 2025 22:15:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225754; cv=none; b=NGO+2tmW7trwYGdSid7L91b0i8R23AhklP5ftwn5aYqvVWDJUle7FHnYkPBB//qdJhlWKjFSkhRDamk9Eg2rn3TAX24RqCcqu+h7HkC7OYUbqXlrYrmWevjDvODkESysl0xTfvmrZN+FimORGhKL+u53yTno1Z6A1crmOP/PKlk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225754; c=relaxed/simple; bh=XHKHFrm9UxTUJdQBjYVXSvTXfPPnzqfzuZ8iAYsIsfo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gcwl3yzOoUjGiv8Y26M2cud2abdKV9j2c+JpzJPdPVrcH/No75KXOW6DmBNyCNyIPi2HGjc9ltLHlopVMl+QpGlPYscUHTjJeDPmsZ2IrGj29xNVU4F8k5w6xNo8cp4rv/63DgpveuYoogCQ6KWk62qi4VV+pRFV/u0as4S1hYA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=idJMETfm; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="idJMETfm" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 51AMFVtX121121 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Feb 2025 16:15:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1739225731; bh=csK+TxlNwuyVouIbzQNjNZY+df/jqdZq/HmfKuxiiTo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=idJMETfmuE/GeG6KXF69qTXQCDIK2WETGYfo3s8IPjvt2JA+yT1CraT3qewRLFxDU vdQ4difxOBttZRL0RjrDnu0qCdpRkOwf3ZIikUobqgKNiMqdGskix7PPPG8ReH+5fB bcSzug0cUypTTa/ysIuSRMgw16dPtRtZqSkVt0fk= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 51AMFVC9016609 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 10 Feb 2025 16:15:31 -0600 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 10 Feb 2025 16:15:30 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 10 Feb 2025 16:15:30 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51AMFUZB112628; Mon, 10 Feb 2025 16:15:30 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v5 09/10] arm64: dts: ti: k3-am62a7-sk: Reserve main_rti4 for C7x DSP Date: Mon, 10 Feb 2025 16:15:29 -0600 Message-ID: <20250210221530.1234009-10-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250210221530.1234009-1-jm@ti.com> References: <20250210221530.1234009-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla The main rti4 watchdog timer is used by the C7x DSP, so reserve the timer in the linux device tree. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v4: - No change --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index 11390a8742453..07f21abd03c12 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -826,3 +826,8 @@ &c7x_0 { <&c7x_0_memory_region>; status =3D "okay"; }; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status =3D "reserved"; +}; --=20 2.48.0 From nobody Sun Feb 8 12:38:00 2026 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAEA2250BE8; Mon, 10 Feb 2025 22:15:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225755; cv=none; b=MOrYPLCU0Aeihe2Hcv4WiePe163DPo+f3utYpF3ZiXnYupz9OSo87EJKFJtoPxFkE8dly9/eoerv5BFqTVYd4VuoiQ8pCqwwx68MSCO+gjeAa8fdJhNtQd/7jzvW8qeWIEaycdBAel1S+bzK5aBHjf+kwHiFk2MjJ3HkTyQxb0g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739225755; c=relaxed/simple; bh=AuaBOvXXgv3uC8cV1e0064fK5LNOp0uvZ+8Px3GBuvg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Wxz0hT+Da3viTKdTXlwXLhqHtPIeRT30ZPhoOtBce83/WVg7VgZQC1pDa4XgshuZdFOhi/o1hTlCzB17hAuEcy2x9v5aSrfrMUbD9opYXK12GKSRyktb/FxSNpUQ94C/deWhdtm1bVSTHaimqVBwFwuNeMB3YHIsUMDWe3LcVdY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Gg2PL2f5; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Gg2PL2f5" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 51AMFVoB121123 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 10 Feb 2025 16:15:31 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1739225731; bh=rtwooEUXJqbc+gp6GlVVSdw12M9QnNlfkv2N7dQ+dOw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Gg2PL2f5wODScub8A9bFewGw/TW/jHrolRFjgp4fSwcXiNdNA7eEtiLuF1VhxjYxZ xrTh/o5Il+gosn6WnpxSOuYzpvSrBn9oVGqTKB7q1CyUUhn00GZg1206XJIrJOUyLe +6L9bRYYM/OpNrJrFJzmVzVar1MwUYL5PJdvvtYA= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 51AMFVqJ016612 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 10 Feb 2025 16:15:31 -0600 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 10 Feb 2025 16:15:31 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 10 Feb 2025 16:15:30 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 51AMFUZC112628; Mon, 10 Feb 2025 16:15:30 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v5 10/10] arm64: dts: ti: k3-am64: Reserve timers used by MCU FW Date: Mon, 10 Feb 2025 16:15:30 -0600 Message-ID: <20250210221530.1234009-11-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250210221530.1234009-1-jm@ti.com> References: <20250210221530.1234009-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla AM64x device has 4 R5F cores in the main domain. TI MCU firmware uses main domain timers as tick timers in these firmwares. Hence keep them as reserved in the Linux device tree. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v4: - Reserve timers for AM64 MCU FW, patch 10/10 --- arch/arm64/boot/dts/ti/k3-am642-evm.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/ti/k3-am642-sk.dts | 17 +++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am642-evm.dts b/arch/arm64/boot/dts/= ti/k3-am642-evm.dts index f8ec40523254b..68bd6b806f8f0 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-evm.dts @@ -796,6 +796,23 @@ &mcu_m4fss { status =3D "okay"; }; =20 +/* main_timers 8-11 are used by TI MCU FW */ +&main_timer8 { + status =3D "reserved"; +}; + +&main_timer9 { + status =3D "reserved"; +}; + +&main_timer10 { + status =3D "reserved"; +}; + +&main_timer11 { + status =3D "reserved"; +}; + &serdes_ln_ctrl { idle-states =3D ; }; diff --git a/arch/arm64/boot/dts/ti/k3-am642-sk.dts b/arch/arm64/boot/dts/t= i/k3-am642-sk.dts index 33e421ec18abb..07fbdf2400d23 100644 --- a/arch/arm64/boot/dts/ti/k3-am642-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am642-sk.dts @@ -710,6 +710,23 @@ &mcu_m4fss { status =3D "okay"; }; =20 +/* main_timers 8-11 are used by TI MCU FW */ +&main_timer8 { + status =3D "reserved"; +}; + +&main_timer9 { + status =3D "reserved"; +}; + +&main_timer10 { + status =3D "reserved"; +}; + +&main_timer11 { + status =3D "reserved"; +}; + &ecap0 { status =3D "okay"; /* PWM is available on Pin 1 of header J3 */ --=20 2.48.0