From nobody Tue Dec 16 23:29:56 2025 Received: from szxga05-in.huawei.com (szxga05-in.huawei.com [45.249.212.191]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5CEF223336 for ; Mon, 10 Feb 2025 14:57:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.191 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739199433; cv=none; b=CJ27HcmjmdNMsYe0T4p7YD/dPcf1f5t73EJGHuTKT9BFMA6nUMMJuCM40tcEMcUWm9WEIfqHqwlof/QXxJxnP0TByd/fJPvw6aqWFGNMWJuunxpggMUaJ5NT65XBiuEuSZWJZI0nYzR5QhyXwFA2gJieEAFyBRxpjDNii+c45Zs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739199433; c=relaxed/simple; bh=0DCYsyzNoD5K5+cbgRtQ7sic6MBaTnILCtXO02F37vI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cT0Q5EsauTBPS+7G8vywR68y0zuImqPbwYPbZBIsxfoGrsh2KIXfOFmgIukOqBbMhS453ANOdx+kSb3NxsZJoFBOo+zFRn5Ahwx/IVT4Thv2pbEyUIEH69Wnafg7EYJeTB0C3F3Bdjxqw9v1OnuoJAT5TeD3Fkihsik8HIUoX8M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.191 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.88.163]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4Ys6yZ148Jz1ltZr; Mon, 10 Feb 2025 22:53:26 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id 7EAD518005F; Mon, 10 Feb 2025 22:57:09 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Mon, 10 Feb 2025 22:57:08 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 drm-dp 5/7] drm/hisilicon/hibmc: Get link status and dpcd caps Date: Mon, 10 Feb 2025 22:49:57 +0800 Message-ID: <20250210144959.100551-6-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250210144959.100551-1-shiyongbang@huawei.com> References: <20250210144959.100551-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: Baihan Li Prepare the hibmc_dp_get_foo() functions for debugfs using in next patch. We also add dpcd's if statement in link training process, because we have the dpcd. Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h | 3 ++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 15 ++++++++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h | 3 ++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c | 39 ++++++++++++++++---- 4 files changed, 52 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_comm.h index d613da8b544c..8eb1659c7685 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h @@ -26,6 +26,9 @@ struct hibmc_link_status { struct hibmc_link_cap { u8 link_rate; u8 lanes; + int rx_dpcd_revision; + bool is_tps3; + bool is_tps4; }; =20 struct hibmc_dp_link { diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index 8adace0befde..5e889c377117 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -227,6 +227,21 @@ int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_= display_mode *mode) return 0; } =20 +u8 hibmc_dp_get_link_rate(struct hibmc_dp *dp) +{ + return dp->dp_dev->link.cap.link_rate; +} + +u8 hibmc_dp_get_lanes(struct hibmc_dp *dp) +{ + return dp->dp_dev->link.cap.lanes; +} + +int hibmc_dp_get_dpcd(struct hibmc_dp *dp) +{ + return dp->dp_dev->link.cap.rx_dpcd_revision; +} + static const struct hibmc_dp_color_raw g_rgb_raw[] =3D { {CBAR_COLOR_BAR, 0x000, 0x000, 0x000}, {CBAR_WHITE, 0xfff, 0xfff, 0xfff}, diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.h index 621a0a1d7eb7..823544b8008b 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h @@ -54,6 +54,9 @@ struct hibmc_dp { int hibmc_dp_hw_init(struct hibmc_dp *dp); int hibmc_dp_mode_set(struct hibmc_dp *dp, struct drm_display_mode *mode); void hibmc_dp_display_en(struct hibmc_dp *dp, bool enable); +int hibmc_dp_get_dpcd(struct hibmc_dp *dp); +u8 hibmc_dp_get_link_rate(struct hibmc_dp *dp); +u8 hibmc_dp_get_lanes(struct hibmc_dp *dp); void hibmc_dp_set_cbar(struct hibmc_dp *dp, const struct hibmc_dp_cbar_cfg= *cfg); =20 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_link.c index 4a99a9b7e3c4..39345fc78c06 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c @@ -7,6 +7,7 @@ #include "dp_comm.h" #include "dp_reg.h" #include "dp_serdes.h" +#include "dp_config.h" =20 #define HIBMC_EQ_MAX_RETRY 5 =20 @@ -42,11 +43,7 @@ static int hibmc_dp_link_training_configure(struct hibmc= _dp_dev *dp) return ret >=3D 0 ? -EIO : ret; } =20 - ret =3D drm_dp_read_dpcd_caps(dp->aux, dp->dpcd); - if (ret) - drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret); - - return ret; + return 0; } =20 static int hibmc_dp_link_set_pattern(struct hibmc_dp_dev *dp, int pattern) @@ -189,15 +186,17 @@ static int hibmc_dp_link_training_cr(struct hibmc_dp_= dev *dp) bool level_changed; u32 voltage_tries; u32 cr_tries; + u32 max_cr; int ret; =20 /* * DP 1.4 spec define 10 for maxtries value, for pre DP 1.4 version set a= limit of 80 * (4 voltage levels x 4 preemphasis levels x 5 identical voltage retries) */ + max_cr =3D dp->link.cap.rx_dpcd_revision >=3D DP_DPCD_REV_14 ? 10 : 80; =20 voltage_tries =3D 1; - for (cr_tries =3D 0; cr_tries < 80; cr_tries++) { + for (cr_tries =3D 0; cr_tries < max_cr; cr_tries++) { drm_dp_link_train_clock_recovery_delay(dp->aux, dp->dpcd); =20 ret =3D drm_dp_dpcd_read_link_status(dp->aux, lane_status); @@ -234,7 +233,7 @@ static int hibmc_dp_link_training_cr(struct hibmc_dp_de= v *dp) voltage_tries =3D level_changed ? 1 : voltage_tries + 1; } =20 - drm_err(dp->dev, "dp link training clock recovery 80 times failed\n"); + drm_err(dp->dev, "dp link training clock recovery %u times failed\n", max= _cr); dp->link.status.clock_recovered =3D false; =20 return 0; @@ -244,9 +243,17 @@ static int hibmc_dp_link_training_channel_eq(struct hi= bmc_dp_dev *dp) { u8 lane_status[DP_LINK_STATUS_SIZE] =3D {0}; u8 eq_tries; + int tps; int ret; =20 - ret =3D hibmc_dp_link_set_pattern(dp, DP_TRAINING_PATTERN_2); + if (dp->link.cap.is_tps4) + tps =3D DP_TRAINING_PATTERN_4; + else if (dp->link.cap.is_tps3) + tps =3D DP_TRAINING_PATTERN_3; + else + tps =3D DP_TRAINING_PATTERN_2; + + ret =3D hibmc_dp_link_set_pattern(dp, tps); if (ret) return ret; =20 @@ -313,11 +320,27 @@ static int hibmc_dp_link_downgrade_training_eq(struct= hibmc_dp_dev *dp) return hibmc_dp_link_reduce_rate(dp); } =20 +static void hibmc_dp_update_caps(struct hibmc_dp_dev *dp) +{ + dp->link.cap.rx_dpcd_revision =3D dp->dpcd[DP_DPCD_REV]; + + dp->link.cap.is_tps3 =3D (dp->dpcd[DP_DPCD_REV] >=3D DP_DPCD_REV_13) && + (dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED); + dp->link.cap.is_tps4 =3D (dp->dpcd[DP_DPCD_REV] >=3D DP_DPCD_REV_14) && + (dp->dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED); +} + int hibmc_dp_link_training(struct hibmc_dp_dev *dp) { struct hibmc_dp_link *link =3D &dp->link; int ret; =20 + ret =3D drm_dp_read_dpcd_caps(dp->aux, dp->dpcd); + if (ret) + drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret); + + hibmc_dp_update_caps(dp); + while (true) { ret =3D hibmc_dp_link_training_cr_pre(dp); if (ret) --=20 2.33.0