From nobody Tue Dec 16 23:29:00 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 87A7320487F for ; Mon, 10 Feb 2025 14:57:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739199434; cv=none; b=ocau1WF92EaPIGePEDe6P9hiNmUmCxIr48brcoorSjoOHtEsTTazd6hIaGIMFVC62qnsZINShC7dmncG2deMkW3AsZ1FWjNKunJVX7+lmOAF3qN9KXhD0ZxLTFjU4Or07bskNJaT3TRdwwdXwW7yrNJHEZnVQ/csQSa7TjdYdoM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739199434; c=relaxed/simple; bh=YKG6Z29MpBVK//KZKgRKZ45I33/PdBTV91zo9s6fkic=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Z/vevTavOvtjX7FLh4boOB4YNwGbOdREiCvufMBpughAs4OV3zYK/FVOoKT441y92uEw1hoAImBnZIuqzXaJnyCsTiJObRFVNuV1lD3pl3U+43154oW3aTdL1rnGeTbw+9p12XCPzpEGcchbx9EJ77N3uvRW7x9O7ALTfKkFc0M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4Ys6yW4HSzz2FcV3; Mon, 10 Feb 2025 22:53:23 +0800 (CST) Received: from kwepemd500013.china.huawei.com (unknown [7.221.188.12]) by mail.maildlp.com (Postfix) with ESMTPS id 237EE1A0188; Mon, 10 Feb 2025 22:57:07 +0800 (CST) Received: from localhost.huawei.com (10.169.71.169) by kwepemd500013.china.huawei.com (7.221.188.12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.34; Mon, 10 Feb 2025 22:57:05 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , Subject: [PATCH v2 drm-dp 3/7] drm/hisilicon/hibmc: Getting connector info and edid by using aux channel Date: Mon, 10 Feb 2025 22:49:55 +0800 Message-ID: <20250210144959.100551-4-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250210144959.100551-1-shiyongbang@huawei.com> References: <20250210144959.100551-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: dggems706-chm.china.huawei.com (10.3.19.183) To kwepemd500013.china.huawei.com (7.221.188.12) Content-Type: text/plain; charset="utf-8" From: Baihan Li Registering drm_aux and using it to get connector edid with drm functions. Refactoring some structs to fit aux's register framework. We need change a lot about getting member of drm_aux, because we change it's postions from struct hibmc_dp_dev to struct hibmc_dp. Signed-off-by: Baihan Li Signed-off-by: Yongbang Shi --- ChangeLog: v1 -> v2: - deleting type conversion, suggested by Dmitry Baryshkov. - deleting hibmc_dp_connector_get_modes() and using drm_connector_helper_= get_modes(), suggested by Dmitry Baryshkov. --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c | 16 ++++++---- drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h | 7 +++-- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 2 +- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h | 2 ++ drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c | 22 +++++++------- .../gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c | 30 +++++++++++-------- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h | 5 ++++ 7 files changed, 52 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c b/drivers/gpu/drm/= hisilicon/hibmc/dp/dp_aux.c index 0a903cce1fa9..e0bb9b14d9d8 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_aux.c @@ -8,6 +8,7 @@ #include #include "dp_comm.h" #include "dp_reg.h" +#include "dp_hw.h" =20 #define HIBMC_AUX_CMD_REQ_LEN GENMASK(7, 4) #define HIBMC_AUX_CMD_ADDR GENMASK(27, 8) @@ -124,7 +125,8 @@ static int hibmc_dp_aux_parse_xfer(struct hibmc_dp_dev = *dp, struct drm_dp_aux_ms /* ret >=3D 0 ,ret is size; ret < 0, ret is err code */ static ssize_t hibmc_dp_aux_xfer(struct drm_dp_aux *aux, struct drm_dp_aux= _msg *msg) { - struct hibmc_dp_dev *dp =3D container_of(aux, struct hibmc_dp_dev, aux); + struct hibmc_dp *dp_priv =3D container_of(aux, struct hibmc_dp, aux); + struct hibmc_dp_dev *dp =3D dp_priv->dp_dev; u32 aux_cmd; int ret; u32 val; /* val will be assigned at the beginning of readl_poll_timeout f= unction */ @@ -151,14 +153,16 @@ static ssize_t hibmc_dp_aux_xfer(struct drm_dp_aux *a= ux, struct drm_dp_aux_msg * return hibmc_dp_aux_parse_xfer(dp, msg); } =20 -void hibmc_dp_aux_init(struct hibmc_dp_dev *dp) +void hibmc_dp_aux_init(struct hibmc_dp *dp) { - hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_SYNC_LEN_= SEL, 0x0); - hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_TIMER_TIM= EOUT, 0x1); - hibmc_dp_reg_write_field(dp, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_MIN_PULSE= _NUM, + hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_S= YNC_LEN_SEL, 0x0); + hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_T= IMER_TIMEOUT, 0x1); + hibmc_dp_reg_write_field(dp->dp_dev, HIBMC_DP_AUX_REQ, HIBMC_DP_CFG_AUX_M= IN_PULSE_NUM, HIBMC_DP_MIN_PULSE_NUM); =20 dp->aux.transfer =3D hibmc_dp_aux_xfer; - dp->aux.is_remote =3D 0; + dp->aux.name =3D kasprintf(GFP_KERNEL, "HIBMC DRM dp aux"); + dp->aux.drm_dev =3D dp->drm_dev; drm_dp_aux_init(&dp->aux); + dp->dp_dev->aux =3D &dp->aux; } diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_comm.h index e7746bc4b592..d613da8b544c 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h @@ -11,8 +11,11 @@ #include #include #include + #include =20 +#include "dp_hw.h" + #define HIBMC_DP_LANE_NUM_MAX 2 =20 struct hibmc_link_status { @@ -32,7 +35,7 @@ struct hibmc_dp_link { }; =20 struct hibmc_dp_dev { - struct drm_dp_aux aux; + struct drm_dp_aux *aux; struct drm_device *dev; void __iomem *base; struct mutex lock; /* protects concurrent RW in hibmc_dp_reg_write_field(= ) */ @@ -58,7 +61,7 @@ struct hibmc_dp_dev { mutex_unlock(&_dp->lock); \ } while (0) =20 -void hibmc_dp_aux_init(struct hibmc_dp_dev *dp); +void hibmc_dp_aux_init(struct hibmc_dp *dp); int hibmc_dp_link_training(struct hibmc_dp_dev *dp); =20 #endif diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index ee1ff205ff56..77f02d5151f7 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -168,7 +168,7 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) dp_dev->dev =3D drm_dev; dp_dev->base =3D dp->mmio + HIBMC_DP_OFFSET; =20 - hibmc_dp_aux_init(dp_dev); + hibmc_dp_aux_init(dp); =20 if (hibmc_dp_serdes_init(dp_dev)) return -EAGAIN; diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.h index 4dc13b3d9875..53b6d0beecea 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.h @@ -10,6 +10,7 @@ #include #include #include +#include =20 struct hibmc_dp_dev; =20 @@ -19,6 +20,7 @@ struct hibmc_dp { struct drm_encoder encoder; struct drm_connector connector; void __iomem *mmio; + struct drm_dp_aux aux; }; =20 int hibmc_dp_hw_init(struct hibmc_dp *dp); diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_link.c index 43a4b656493f..4a99a9b7e3c4 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c @@ -27,7 +27,7 @@ static int hibmc_dp_link_training_configure(struct hibmc_= dp_dev *dp) /* set rate and lane count */ buf[0] =3D dp->link.cap.link_rate; buf[1] =3D DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; - ret =3D drm_dp_dpcd_write(&dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); + ret =3D drm_dp_dpcd_write(dp->aux, DP_LINK_BW_SET, buf, sizeof(buf)); if (ret !=3D sizeof(buf)) { drm_dbg_dp(dp->dev, "dp aux write link rate and lanes failed, ret: %d\n"= , ret); return ret >=3D 0 ? -EIO : ret; @@ -36,13 +36,13 @@ static int hibmc_dp_link_training_configure(struct hibm= c_dp_dev *dp) /* set 8b/10b and downspread */ buf[0] =3D DP_SPREAD_AMP_0_5; buf[1] =3D DP_SET_ANSI_8B10B; - ret =3D drm_dp_dpcd_write(&dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf)); + ret =3D drm_dp_dpcd_write(dp->aux, DP_DOWNSPREAD_CTRL, buf, sizeof(buf)); if (ret !=3D sizeof(buf)) { drm_dbg_dp(dp->dev, "dp aux write 8b/10b and downspread failed, ret: %d\= n", ret); return ret >=3D 0 ? -EIO : ret; } =20 - ret =3D drm_dp_read_dpcd_caps(&dp->aux, dp->dpcd); + ret =3D drm_dp_read_dpcd_caps(dp->aux, dp->dpcd); if (ret) drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret); =20 @@ -85,7 +85,7 @@ static int hibmc_dp_link_set_pattern(struct hibmc_dp_dev = *dp, int pattern) =20 hibmc_dp_reg_write_field(dp, HIBMC_DP_PHYIF_CTRL0, HIBMC_DP_CFG_PAT_SEL, = val); =20 - ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_PATTERN_SET, &buf, sizeof= (buf)); + ret =3D drm_dp_dpcd_write(dp->aux, DP_TRAINING_PATTERN_SET, &buf, sizeof(= buf)); if (ret !=3D sizeof(buf)) { drm_dbg_dp(dp->dev, "dp aux write training pattern set failed\n"); return ret >=3D 0 ? -EIO : ret; @@ -115,7 +115,7 @@ static int hibmc_dp_link_training_cr_pre(struct hibmc_d= p_dev *dp) if (ret) return ret; =20 - ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, train_set, dp-= >link.cap.lanes); + ret =3D drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, train_set, dp->= link.cap.lanes); if (ret !=3D dp->link.cap.lanes) { drm_dbg_dp(dp->dev, "dp aux write training lane set failed\n"); return ret >=3D 0 ? -EIO : ret; @@ -198,9 +198,9 @@ static int hibmc_dp_link_training_cr(struct hibmc_dp_de= v *dp) =20 voltage_tries =3D 1; for (cr_tries =3D 0; cr_tries < 80; cr_tries++) { - drm_dp_link_train_clock_recovery_delay(&dp->aux, dp->dpcd); + drm_dp_link_train_clock_recovery_delay(dp->aux, dp->dpcd); =20 - ret =3D drm_dp_dpcd_read_link_status(&dp->aux, lane_status); + ret =3D drm_dp_dpcd_read_link_status(dp->aux, lane_status); if (ret !=3D DP_LINK_STATUS_SIZE) { drm_err(dp->dev, "Get lane status failed\n"); return ret; @@ -224,7 +224,7 @@ static int hibmc_dp_link_training_cr(struct hibmc_dp_de= v *dp) if (ret) return ret; =20 - ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, dp->link.trai= n_set, + ret =3D drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train= _set, dp->link.cap.lanes); if (ret !=3D dp->link.cap.lanes) { drm_dbg_dp(dp->dev, "Update link training failed\n"); @@ -251,9 +251,9 @@ static int hibmc_dp_link_training_channel_eq(struct hib= mc_dp_dev *dp) return ret; =20 for (eq_tries =3D 0; eq_tries < HIBMC_EQ_MAX_RETRY; eq_tries++) { - drm_dp_link_train_channel_eq_delay(&dp->aux, dp->dpcd); + drm_dp_link_train_channel_eq_delay(dp->aux, dp->dpcd); =20 - ret =3D drm_dp_dpcd_read_link_status(&dp->aux, lane_status); + ret =3D drm_dp_dpcd_read_link_status(dp->aux, lane_status); if (ret !=3D DP_LINK_STATUS_SIZE) { drm_err(dp->dev, "get lane status failed\n"); break; @@ -278,7 +278,7 @@ static int hibmc_dp_link_training_channel_eq(struct hib= mc_dp_dev *dp) if (ret) return ret; =20 - ret =3D drm_dp_dpcd_write(&dp->aux, DP_TRAINING_LANE0_SET, + ret =3D drm_dp_dpcd_write(dp->aux, DP_TRAINING_LANE0_SET, dp->link.train_set, dp->link.cap.lanes); if (ret !=3D dp->link.cap.lanes) { drm_dbg_dp(dp->dev, "Update link training failed\n"); diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c b/drivers/gpu/d= rm/hisilicon/hibmc/hibmc_drm_dp.c index 603d6b198a54..795c5b1a6b99 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_dp.c @@ -13,20 +13,24 @@ #include "hibmc_drm_drv.h" #include "dp/dp_hw.h" =20 -static int hibmc_dp_connector_get_modes(struct drm_connector *connector) -{ - int count; +static const struct drm_connector_helper_funcs hibmc_dp_conn_helper_funcs = =3D { + .get_modes =3D drm_connector_helper_get_modes, + .detect_ctx =3D drm_connector_helper_detect_from_ddc, +}; =20 - count =3D drm_add_modes_noedid(connector, connector->dev->mode_config.max= _width, - connector->dev->mode_config.max_height); - drm_set_preferred_mode(connector, 1024, 768); // temporary implementation +static int hibmc_dp_late_register(struct drm_connector *connector) +{ + struct hibmc_dp *dp =3D to_hibmc_dp(connector); =20 - return count; + return drm_dp_aux_register(&dp->aux); } =20 -static const struct drm_connector_helper_funcs hibmc_dp_conn_helper_funcs = =3D { - .get_modes =3D hibmc_dp_connector_get_modes, -}; +static void hibmc_dp_early_unregister(struct drm_connector *connector) +{ + struct hibmc_dp *dp =3D to_hibmc_dp(connector); + + drm_dp_aux_unregister(&dp->aux); +} =20 static const struct drm_connector_funcs hibmc_dp_conn_funcs =3D { .reset =3D drm_atomic_helper_connector_reset, @@ -34,6 +38,8 @@ static const struct drm_connector_funcs hibmc_dp_conn_fun= cs =3D { .destroy =3D drm_connector_cleanup, .atomic_duplicate_state =3D drm_atomic_helper_connector_duplicate_state, .atomic_destroy_state =3D drm_atomic_helper_connector_destroy_state, + .late_register =3D hibmc_dp_late_register, + .early_unregister =3D hibmc_dp_early_unregister, }; =20 static inline int hibmc_dp_prepare(struct hibmc_dp *dp, struct drm_display= _mode *mode) @@ -103,8 +109,8 @@ int hibmc_dp_init(struct hibmc_drm_private *priv) =20 drm_encoder_helper_add(encoder, &hibmc_dp_encoder_helper_funcs); =20 - ret =3D drm_connector_init(dev, connector, &hibmc_dp_conn_funcs, - DRM_MODE_CONNECTOR_DisplayPort); + ret =3D drm_connector_init_with_ddc(dev, connector, &hibmc_dp_conn_funcs, + DRM_MODE_CONNECTOR_DisplayPort, &dp->aux.ddc); if (ret) { drm_err(dev, "init dp connector failed: %d\n", ret); return ret; diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h b/drivers/gpu/= drm/hisilicon/hibmc/hibmc_drm_drv.h index d982f1e4b958..3ddd71aada66 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.h @@ -47,6 +47,11 @@ static inline struct hibmc_vdac *to_hibmc_vdac(struct dr= m_connector *connector) return container_of(connector, struct hibmc_vdac, connector); } =20 +static inline struct hibmc_dp *to_hibmc_dp(struct drm_connector *connector) +{ + return container_of(connector, struct hibmc_dp, connector); +} + static inline struct hibmc_drm_private *to_hibmc_drm_private(struct drm_de= vice *dev) { return container_of(dev, struct hibmc_drm_private, dev); --=20 2.33.0