From nobody Tue Dec 16 22:03:26 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C76411C9B97 for ; Mon, 10 Feb 2025 10:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739184489; cv=none; b=TkeXxBCJPW6c1Mbp3ZmhPTHp28u22NFNAGdx/Cuel2BCKnFDYqFAjlW+Lx0QPgxRahbL5sidXxo1qJ6dTdTngDn+eflVA1pcbkuz5h4nLthTFx54bJhzbDunZSuQ62P+XXamzYgKuX5Ji5habAAaClGV2X9wBSgmDEPmjFDj8KA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739184489; c=relaxed/simple; bh=2RAGCEjD/CR08jL4G3YT5aoARea4GVAx+mC/eXm1oj8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GrUYGtG8zrizeD4zPbhyqft7oBtfLO6khtgl5Yqsra1zYLS1GbD0ceYYf59/he6z0xFn2OovlNW2RISjFgAwBPmJqoyF/VY1wUbgGrtFGT9RGyF3Phc23u5g3q6NmdGlfns+rJsi5E/JA6yAZ1NSm8FlXnqB3Y9Pry3IwQbz6RE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1thRKR-0002Bn-HM; Mon, 10 Feb 2025 11:47:51 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1thRKP-000EIa-2n; Mon, 10 Feb 2025 11:47:49 +0100 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1thRKP-001f8B-2V; Mon, 10 Feb 2025 11:47:49 +0100 From: Oleksij Rempel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Woojung Huh , Andrew Lunn Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 1/3] dt-bindings: sound: convert ICS-43432 binding to YAML Date: Mon, 10 Feb 2025 11:47:46 +0100 Message-Id: <20250210104748.396399-2-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210104748.396399-1-o.rempel@pengutronix.de> References: <20250210104748.396399-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Convert the ICS-43432 MEMS microphone device tree binding from text format to YAML. Signed-off-by: Oleksij Rempel --- changes v2: - use "enum" instead "oneOf + const" --- .../devicetree/bindings/sound/ics43432.txt | 19 ------- .../bindings/sound/invensense,ics43432.yaml | 51 +++++++++++++++++++ 2 files changed, 51 insertions(+), 19 deletions(-) delete mode 100644 Documentation/devicetree/bindings/sound/ics43432.txt create mode 100644 Documentation/devicetree/bindings/sound/invensense,ics4= 3432.yaml diff --git a/Documentation/devicetree/bindings/sound/ics43432.txt b/Documen= tation/devicetree/bindings/sound/ics43432.txt deleted file mode 100644 index e6f05f2f6c4e..000000000000 --- a/Documentation/devicetree/bindings/sound/ics43432.txt +++ /dev/null @@ -1,19 +0,0 @@ -Invensense ICS-43432-compatible MEMS microphone with I2S output. - -There are no software configuration options for this device, indeed, the o= nly -host connection is the I2S interface. Apart from requirements on clock -frequency (460 kHz to 3.379 MHz according to the data sheet) there must be -64 clock cycles in each stereo output frame; 24 of the 32 available bits -contain audio data. A hardware pin determines if the device outputs data -on the left or right channel of the I2S frame. - -Required properties: - - compatible: should be one of the following. - "invensense,ics43432": For the Invensense ICS43432 - "cui,cmm-4030d-261": For the CUI CMM-4030D-261-I2S-TR - -Example: - - ics43432: ics43432 { - compatible =3D "invensense,ics43432"; - }; diff --git a/Documentation/devicetree/bindings/sound/invensense,ics43432.ya= ml b/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml new file mode 100644 index 000000000000..79ed8c8e8790 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/invensense,ics43432.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/invensense,ics43432.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Invensense ICS-43432-compatible MEMS Microphone with I2S Output + +maintainers: + - N/A + +description: | + The ICS-43432 and compatible MEMS microphones output audio over an I2S + interface and require no software configuration. The only host connection + is the I2S bus. The microphone requires an I2S clock frequency between + 460 kHz and 3.379 MHz and 64 clock cycles per stereo frame. Each frame + contains 32-bit slots per channel, with 24 bits carrying audio data. + A hardware pin determines whether the microphone outputs audio on the + left or right channel of the I2S frame. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - invensense,ics43432 + - cui,cmm-4030d-261 + + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + ics43432: ics43432 { + compatible =3D "invensense,ics43432"; + + port { + endpoint { + remote-endpoint =3D <&i2s1_endpoint>; + dai-format =3D "i2s"; + }; + }; + + }; -- 2.39.5 From nobody Tue Dec 16 22:03:26 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 253081C6F70 for ; Mon, 10 Feb 2025 10:48:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739184489; cv=none; b=YnNeUYaKV+fcH+JoTh3SOJdvIhPFMte01aOKLRZqhHN/K8qASxjQVx6y6+2iI3YdC6ODJvvrBiZFdlhQAxGt1YXbc3C19nVK7lHfFNHf21dQvDknLRu4cQKTEzWpQ0e6HFriRPLtaL8C5OZC/XcvpO3natoSVchfrq9lgM5FmGQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739184489; c=relaxed/simple; bh=IASJFIdwqKt2fJiXZLQPvbOmfF0RAP8JOTNg11ynshQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=b7O1hRkkpIle+mJlmFhu0a4447awNQBiq0bVPlRv82PFZeM/GIDkcLSO7hnHvSuLRrLEvab+jxapQWYudh+2Qb6w5imXHl7Pst+iaFkZg7RUl5eRLzP+orkLX9MAKe9I8kP49oLZV764PpCIgCQayDnwXrGpTZN30pPqx2cp47c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1thRKR-0002Bo-HM; Mon, 10 Feb 2025 11:47:51 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1thRKP-000EIb-2r; Mon, 10 Feb 2025 11:47:49 +0100 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1thRKP-001f8L-2b; Mon, 10 Feb 2025 11:47:49 +0100 From: Oleksij Rempel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Woojung Huh , Andrew Lunn Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 2/3] dt-bindings: arm: stm32: Add Plymovent AQM board Date: Mon, 10 Feb 2025 11:47:47 +0100 Message-Id: <20250210104748.396399-3-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210104748.396399-1-o.rempel@pengutronix.de> References: <20250210104748.396399-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add support for the Plymovent AQM board based on the ST STM32MP151 SoC to the STM32 devicetree bindings. Signed-off-by: Oleksij Rempel --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Docum= entation/devicetree/bindings/arm/stm32/stm32.yaml index 2cea166641c5..734c4b8ac881 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -65,6 +65,7 @@ properties: - prt,prtt1a # Protonic PRTT1A - prt,prtt1c # Protonic PRTT1C - prt,prtt1s # Protonic PRTT1S + - ply,plyaqm # Plymovent AQM board - const: st,stm32mp151 =20 - description: DH STM32MP135 DHCOR SoM based Boards --=20 2.39.5 From nobody Tue Dec 16 22:03:26 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA3721CEACB for ; Mon, 10 Feb 2025 10:48:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739184492; cv=none; b=rsKmqh3zMDOuJD5ttYal9l75T067whAktNE8sU6NybapnuXagXySMSZkriilkRJEgk6vWc/p1WjQ4dXQPuIorrWB7bBsk5CAfApPHpPeE7m9GcUVyeWiWEV6mU6tUfzZsbKwCkd0qLS6gBkKr+XteFMBDWKTnKcgapPcB04uins= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1739184492; c=relaxed/simple; bh=hoLwhhljYcOuDLc80waE7iUVbiUVLcEwxuyr146fMY0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version:Content-Type; b=qnlOL6mhHVsHAlqrB2GV9qea82OYzz54ziqa6N68w+d7PHVWcX4qNNBuMd+lpnSUS0KpHilMeqg/fgKAjQGEqfZq/ZNr8DFIVxppWX+IyU/5WL5I5S6X5geJZgLRVXAXwR/TJqWVdOliNZoS5Wdgl41cJeeFO6QPtCb0Pu9jeN4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1thRKR-0002Bp-HM; Mon, 10 Feb 2025 11:47:51 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1thRKP-000EIc-2z; Mon, 10 Feb 2025 11:47:49 +0100 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1thRKP-001f8V-2g; Mon, 10 Feb 2025 11:47:49 +0100 From: Oleksij Rempel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Woojung Huh , Andrew Lunn Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 3/3] arm: dts: stm32: Add Plymovent AQM devicetree Date: Mon, 10 Feb 2025 11:47:48 +0100 Message-Id: <20250210104748.396399-4-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250210104748.396399-1-o.rempel@pengutronix.de> References: <20250210104748.396399-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Introduce the devicetree for the Plymovent AQM board (stm32mp151c-plyaqm), based on the STM32MP151 SoC. Signed-off-by: Oleksij Rempel --- changes v2: - remove spidev --- arch/arm/boot/dts/st/Makefile | 1 + arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts | 669 ++++++++++++++++++++ 2 files changed, 670 insertions(+) create mode 100644 arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index d8f297035812..561819ef7a32 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -38,6 +38,7 @@ dtb-$(CONFIG_ARCH_STM32) +=3D \ stm32mp151a-dhcor-testbench.dtb \ stm32mp151c-mecio1r0.dtb \ stm32mp151c-mect1s.dtb \ + stm32mp151c-plyaqm.dtb \ stm32mp153c-dhcom-drc02.dtb \ stm32mp153c-dhcor-drc-compact.dtb \ stm32mp153c-lxa-tac-gen3.dtb \ diff --git a/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts b/arch/arm/boot/dt= s/st/stm32mp151c-plyaqm.dts new file mode 100644 index 000000000000..4e050c49dfc5 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp151c-plyaqm.dts @@ -0,0 +1,669 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/dts-v1/; + +#include +#include +#include +#include +#include +#include +#include + +/ { + model =3D "Plymovent AQM board"; + compatible =3D "ply,plyaqm", "st,stm32mp151"; + + aliases { + ethernet0 =3D ðernet0; + serial0 =3D &uart4; + serial1 =3D &uart7; + }; + + codec { + compatible =3D "invensense,ics43432"; + + port { + codec_endpoint: endpoint { + remote-endpoint =3D <&i2s1_endpoint>; + dai-format =3D "i2s"; + }; + }; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + leds { + compatible =3D "gpio-leds"; + + led-0 { + gpios =3D <&gpioa 3 GPIO_ACTIVE_HIGH>; /* WHITE_EN */ + color =3D ; + default-state =3D "on"; + }; + }; + + v3v3: fixed-regulator-v3v3 { + compatible =3D "regulator-fixed"; + regulator-name =3D "v3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + }; + + v5v_sw: fixed-regulator-v5sw { + compatible =3D "regulator-fixed"; + regulator-name =3D "5v-switched"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + gpio =3D <&gpioe 10 GPIO_ACTIVE_HIGH>; /* 5V_SWITCHED_EN */ + startup-delay-us =3D <100000>; + enable-active-high; + regulator-boot-on; + }; + + reserved-memory { + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + optee@cfd00000 { + reg =3D <0xcfd00000 0x300000>; + no-map; + }; + }; + + sound { + compatible =3D "audio-graph-card"; + label =3D "STM32MP15"; + dais =3D <&i2s1_port>; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&gpioe 12 GPIO_ACTIVE_LOW>; /* WLAN_REG_ON */ + }; +}; + +&adc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&adc1_in10_aqm_pins_a>; + vdda-supply =3D <&v3v3>; + vref-supply =3D <&v3v3>; + status =3D "okay"; + + adc@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + channel@10 { /* NTC */ + reg =3D <10>; + st,min-sample-time-ns =3D <10000>; /* 10=C2=B5s sampling time */ + }; + }; +}; + +&cpu0 { + clocks =3D <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks =3D <&scmi_clk CK_SCMI_CRYP1>; + resets =3D <&scmi_reset RST_SCMI_CRYP1>; + status =3D "okay"; +}; + +ðernet0 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <ðernet0_rmii_aqm_pins_a>; + pinctrl-1 =3D <ðernet0_rmii_sleep_aqm_pins_a>; + phy-mode =3D "rmii"; + max-speed =3D <100>; + phy-handle =3D <ðphy0>; + status =3D "okay"; + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + compatible =3D "snps,dwmac-mdio"; + + /* KSZ8081RNA PHY */ + ethphy0: ethernet-phy@0 { + reg =3D <0>; + interrupts-extended =3D <&gpiob 0 IRQ_TYPE_LEVEL_LOW>; + reset-gpios =3D <&gpiob 1 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <300>; + }; + }; +}; + +&gpioa { + gpio-line-names =3D + "", "", "", "", "", "", "", "", + "", "", "", "", "", "HWID_PL_N", "HWID_CP", ""; +}; + +&gpiob { + gpio-line-names =3D + "", "", "", "", "", "", "LED_LATCH", "", + "", "RELAY1_EN", "", "", "", "", "", ""; +}; + +&gpioc { + gpio-line-names =3D + "", "", "", "", "", "", "", "", + "", "", "", "", "", "HWID_Q7", "", ""; +}; + +&gpioe { + gpio-line-names =3D + "", "", "", "", "RELAY2_EN", "", "", "", + "", "", "", "", "", "", "", ""; +}; + +&gpiog { + gpio-line-names =3D + "", "", "", "", "", "", "", "SW1", + "", "", "", "", "", "", "", ""; +}; + +&gpioz { + clocks =3D <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks =3D <&scmi_clk CK_SCMI_HASH1>; + resets =3D <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c1_aqm_pins_a>; + pinctrl-1 =3D <&i2c1_sleep_aqm_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + status =3D "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + /* CYPD3177 USB PD controller 0x08 */ +}; + +&i2c4 { + clocks =3D <&scmi_clk CK_SCMI_I2C4>; + resets =3D <&scmi_reset RST_SCMI_I2C4>; +}; + +&i2c6 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2c6_aqm_pins_a>; + pinctrl-1 =3D <&i2c6_sleep_aqm_pins_a>; + i2c-scl-rising-time-ns =3D <185>; + i2c-scl-falling-time-ns =3D <20>; + clocks =3D <&scmi_clk CK_SCMI_I2C6>; + resets =3D <&scmi_reset RST_SCMI_I2C6>; + status =3D "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pm-sensor@69 { + compatible =3D "sensirion,sps30"; + reg =3D <0x69>; + }; + + co2-sensor@62 { + compatible =3D "sensirion,scd41"; + reg =3D <0x62>; + vdd-supply =3D <&v5v_sw>; + }; + + pressure-sensor@47 { + compatible =3D "bosch,bmp580"; + reg =3D <0x47>; + vdda-supply =3D <&v5v_sw>; + vddd-supply =3D <&v5v_sw>; + }; + + /* Used for ZMOD4410 in userspace */ +}; + +&i2s1 { + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <&i2s1_aqm_pins>; + pinctrl-1 =3D <&i2s1_sleep_aqm_pins>; + clocks =3D <&rcc SPI1>, <&rcc SPI1_K>, <&rcc PLL3_Q>, <&rcc PLL3_R>; + clock-names =3D "pclk", "i2sclk", "x8k", "x11k"; + #clock-cells =3D <0>; /* Set I2S2 as master clock provider */ + status =3D "okay"; + + i2s1_port: port { + i2s1_endpoint: endpoint { + format =3D "i2s"; + mclk-fs =3D <256>; + remote-endpoint =3D <&codec_endpoint>; + }; + }; +}; + +&iwdg2 { + clocks =3D <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; + status =3D "okay"; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets =3D <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names =3D "mcu_rst", "hold_boot"; +}; + +&mdma1 { + resets =3D <&scmi_reset RST_SCMI_MDMA>; +}; + +&rcc { + compatible =3D "st,stm32mp1-rcc-secure", "syscon"; + clock-names =3D "hse", "hsi", "csi", "lse", "lsi"; + clocks =3D <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks =3D <&scmi_clk CK_SCMI_RNG1>; + resets =3D <&scmi_reset RST_SCMI_RNG1>; + status =3D "okay"; +}; + +&rtc { + clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +/* SD card without Card-detect */ +&sdmmc1 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc1_b4_pins_a>; + pinctrl-1 =3D <&sdmmc1_b4_od_pins_a>; + pinctrl-2 =3D <&sdmmc1_b4_sleep_pins_a>; + broken-cd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width =3D <4>; + vmmc-supply =3D <&v3v3>; + status =3D "okay"; +}; + +/* EMMC */ +&sdmmc2 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc2_b4_aqm_pins_a>; + pinctrl-1 =3D <&sdmmc2_b4_od_aqm_pins_a>; + pinctrl-2 =3D <&sdmmc2_b4_sleep_aqm_pins_a>; + non-removable; + no-sd; + no-sdio; + no-1-8-v; + st,neg-edge; + bus-width =3D <8>; + vmmc-supply =3D <&v3v3>; + status =3D "okay"; +}; + +/* Wifi */ +&sdmmc3 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc3_b4_aqm_pins_a>; + pinctrl-1 =3D <&sdmmc3_b4_od_aqm_pins_a>; + pinctrl-2 =3D <&sdmmc3_b4_sleep_aqm_pins_a>; + non-removable; + st,neg-edge; + bus-width =3D <4>; + vmmc-supply =3D <&v3v3>; + mmc-pwrseq =3D <&wifi_pwrseq>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + wifi@1 { + reg =3D <1>; + compatible =3D "brcm,bcm4329-fmac"; + }; +}; + +&timers5 { + status =3D "okay"; + /delete-property/dmas; + /delete-property/dma-names; + + pwm { + pinctrl-0 =3D <&pwm1_aqm_pins_a>; + pinctrl-1 =3D <&pwm1_sleep_aqm_pins_a>; + pinctrl-names =3D "default", "sleep"; + status =3D "okay"; + }; +}; + +&uart4 { + pinctrl-names =3D "default", "sleep", "idle"; + pinctrl-0 =3D <&uart4_aqm_pins_a>; + pinctrl-1 =3D <&uart4_idle_aqm_pins_a>; + pinctrl-2 =3D <&uart4_sleep_aqm_pins_a>; + /delete-property/dmas; + /delete-property/dma-names; + status =3D "okay"; +}; + +&uart7 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart7_aqm_pins_a>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + compatible =3D "brcm,bcm43438-bt"; + shutdown-gpios =3D <&gpioe 11 GPIO_ACTIVE_HIGH>; /* BT_REG_ON */ + max-speed =3D <4000000>; + vbat-supply =3D <&v3v3>; + vddio-supply =3D <&v3v3>; + interrupt-parent =3D <&gpiog>; + interrupts =3D <12 IRQ_TYPE_EDGE_RISING>; /* BT_HOST_WAKE */ + interrupt-names =3D "host-wakeup"; + }; +}; + +&pinctrl { + adc1_in10_aqm_pins_a: adc1in10-0 { + pins { + pinmux =3D ; /* NTC */ + }; + }; + + ethernet0_rmii_aqm_pins_a: rmii-0 { + pins1 { + pinmux =3D , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate =3D <2>; + }; + + pins2 { + pinmux =3D , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + ethernet0_rmii_sleep_aqm_pins_a: rmii-sleep-0 { + pins1 { + pinmux =3D , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + + /* i2c1 pins redefined because they differ from stm32mp15-pinctrl.dtsi */ + i2c1_aqm_pins_a: i2c1-0 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate =3D <0>; + }; + }; + + i2c1_sleep_aqm_pins_a: i2c1-sleep-0 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + + /* i2c6 pins redefined because they differ from stm32mp15-pinctrl.dtsi */ + i2c6_aqm_pins_a: i2c6-0 { + pins { + pinmux =3D , /* I2C6_SCL */ + ; /* I2C6_SDA */ + bias-disable; + drive-open-drain; + slew-rate =3D <0>; + }; + }; + + i2c6_sleep_aqm_pins_a: i2c6-sleep-0 { + pins { + pinmux =3D , /* I2C6_SCL */ + ; /* I2C6_SDA */ + }; + }; + + i2s1_aqm_pins: i2s1-0 { + pins { + pinmux =3D , /* I2S2_SDI */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + slew-rate =3D <0>; + drive-push-pull; + bias-disable; + }; + }; + + i2s1_sleep_aqm_pins: i2s1-sleep-0 { + pins { + pinmux =3D , /* I2S2_SDI */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + }; + }; + + pwm1_aqm_pins_a: pwm1-0 { + pins { + pinmux =3D ; /* TIM5_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + pwm1_sleep_aqm_pins_a: pwm1-sleep-0 { + pins { + pinmux =3D ; + }; + }; + + /* SDMMC1 pins same as stm32mp15-pinctrl.dtsi */ + + sdmmc2_b4_sleep_aqm_pins_a: sdmmc2-b4-sleep-0 { + pins { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + , /* SDMMC2_D7 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + + sdmmc2_b4_aqm_pins_a: sdmmc2-b4-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + , /* SDMMC2_D7 */ + ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc2_b4_od_aqm_pins_a: sdmmc2-b4-od-0 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux =3D ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_b4_aqm_pins_a: sdmmc3-b4-0 { + pins1 { + pinmux =3D , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux =3D ; /* SDMMC3_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + sdmmc3_b4_od_aqm_pins_a: sdmmc3-b4-od-0 { + pins1 { + pinmux =3D , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux =3D ; /* SDMMC3_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux =3D ; /* SDMMC3_CMD */ + slew-rate =3D <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + sdmmc3_b4_sleep_aqm_pins_a: sdmmc3-b4-sleep-0 { + pins { + pinmux =3D , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; + }; + + uart4_aqm_pins_a: uart4-0 { + pins1 { + pinmux =3D ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate =3D <0>; + }; + + pins2 { + pinmux =3D ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_idle_aqm_pins_a: uart4-idle-0 { + pins1 { + pinmux =3D ; /* UART4_TX */ + }; + + pins2 { + pinmux =3D ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_aqm_pins_a: uart4-sleep-0 { + pins { + pinmux =3D , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart7_aqm_pins_a: uart7-0 { + pins1 { + pinmux =3D , /* UART7_TX */ + ; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate =3D <0>; + }; + + pins2 { + pinmux =3D , /* UART7_RX */ + ; /* UART7_CTS */ + bias-disable; + }; + }; +}; -- 2.39.5