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Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Konrad Dybcio --- This patch depends on the this dt binding pull request which got recently merged: https://github.com/devicetree-org/dt-schema/pull/146 --- --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/q= com/x1e80100.dtsi index 4936fa5b98ff..1b815d4eed5c 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3209,6 +3209,11 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys =3D <&pcie3_phy>; phy-names =3D "pciephy"; =20 + eq-presets-8gts =3D /bits/ 16 <0x5555 0x5555 0x5555 0x5555>, + /bits/ 16 <0x5555 0x5555 0x5555 0x5555>; + + eq-presets-16gts =3D /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>; + operating-points-v2 =3D <&pcie3_opp_table>; =20 status =3D "disabled"; @@ -3411,6 +3416,10 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, phys =3D <&pcie6a_phy>; phy-names =3D "pciephy"; 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As per PCIe spec 6.0.1 revision section 8.3.3.3 & 4.2.4 for data rates of 8.0 GT/s, 16.0 GT/s, 32.0 GT/s, and 64.0 GT/s, there is a way to configure lane equalization presets for each lane to enhance the PCIe link reliability. Each preset value represents a different combination of pre-shoot and de-emphasis values. For each data rate, different registers are defined: for 8.0 GT/s, registers are defined in section 7.7.3.4; for 16.0 GT/s, in section 7.7.5.9, etc. The 8.0 GT/s rate has an extra receiver preset hint, requiring 16 bits per lane, while the remaining data rates use 8 bits per lane. Based on the number of lanes and the supported data rate, this function reads the device tree property and stores in the presets structure. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/of.c | 43 +++++++++++++++++++++++++++++++++++++++++++ drivers/pci/pci.h | 27 ++++++++++++++++++++++++++- 2 files changed, 69 insertions(+), 1 deletion(-) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 7a806f5c0d20..705d5529fa95 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -851,3 +851,46 @@ u32 of_pci_get_slot_power_limit(struct device_node *no= de, return slot_power_limit_mw; } EXPORT_SYMBOL_GPL(of_pci_get_slot_power_limit); + +/** + * of_pci_get_equalization_presets - Parses the "eq-presets-ngts" property. + * + * @dev: Device containing the properties. + * @presets: Pointer to store the parsed data. + * @num_lanes: Maximum number of lanes supported. + * + * If the property is present read and store the data in the preset struct= ure + * assign default value 0xff to indicate property is not present. + * + * Return: 0 if the property is not available or successfully parsed; errn= o otherwise. + */ +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + char name[20]; + int ret; + + presets->eq_presets_8gts[0] =3D PCI_EQ_RESV; + ret =3D of_property_read_u16_array(dev->of_node, "eq-presets-8gts", + presets->eq_presets_8gts, num_lanes); + if (ret && ret !=3D -EINVAL) { + dev_err(dev, "Error reading eq-presets-8gts %d\n", ret); + return ret; + } + + for (int i =3D 0; i < EQ_PRESET_TYPE_MAX; i++) { + presets->eq_presets_Ngts[i][0] =3D PCI_EQ_RESV; + snprintf(name, sizeof(name), "eq-presets-%dgts", 8 << (i + 1)); + ret =3D of_property_read_u8_array(dev->of_node, name, + presets->eq_presets_Ngts[i], + num_lanes); + if (ret && ret !=3D -EINVAL) { + dev_err(dev, "Error reading %s %d\n", name, ret); + return ret; + } + } + + return 0; +} +EXPORT_SYMBOL_GPL(of_pci_get_equalization_presets); diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 01e51db8d285..e87c2ffd1e85 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -9,6 +9,8 @@ struct pcie_tlp_log; /* Number of possible devfns: 0.0 to 1f.7 inclusive */ #define MAX_NR_DEVFNS 256 =20 +#define MAX_NR_LANES 16 + #define PCI_FIND_CAP_TTL 48 =20 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ @@ -808,6 +810,20 @@ static inline u64 pci_rebar_size_to_bytes(int size) =20 struct device_node; =20 +#define PCI_EQ_RESV 0xff + +enum equalization_preset_type { + EQ_PRESET_TYPE_16GTS, + EQ_PRESET_TYPE_32GTS, + EQ_PRESET_TYPE_64GTS, + EQ_PRESET_TYPE_MAX +}; + +struct pci_eq_presets { + u16 eq_presets_8gts[MAX_NR_LANES]; + u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX][MAX_NR_LANES]; +}; + #ifdef CONFIG_OF int of_get_pci_domain_nr(struct device_node *node); int of_pci_get_max_link_speed(struct device_node *node); @@ -822,7 +838,9 @@ void pci_release_bus_of_node(struct pci_bus *bus); =20 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *br= idge); bool of_pci_supply_present(struct device_node *np); - +int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes); #else static inline int of_get_pci_domain_nr(struct device_node *node) @@ -867,6 +885,13 @@ static inline bool of_pci_supply_present(struct device= _node *np) { return false; } + +static inline int of_pci_get_equalization_presets(struct device *dev, + struct pci_eq_presets *presets, + int num_lanes) +{ + return 0; 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Sun, 09 Feb 2025 23:30:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IGC4mFsdhr14elczMdgif0tIJ9T32NQVRA86UAwGYhm7aRYQ7hdqOUHt+ZP3HEWgDqCFnMgDg== X-Received: by 2002:a17:90b:2ec5:b0:2fa:2252:f438 with SMTP id 98e67ed59e1d1-2fa2450cf33mr18714812a91.30.1739172632097; Sun, 09 Feb 2025 23:30:32 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-2fa09a6fe28sm7918507a91.26.2025.02.09.23.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Feb 2025 23:30:31 -0800 (PST) From: Krishna Chaitanya Chundru Date: Mon, 10 Feb 2025 13:00:02 +0530 Subject: [PATCH v6 3/4] PCI: dwc: Improve handling of PCIe lane configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250210-preset_v6-v6-3-cbd837d0028d@oss.qualcomm.com> References: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> In-Reply-To: <20250210-preset_v6-v6-0-cbd837d0028d@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_mrana@quicinc.com, quic_vbadigan@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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Update number of lanes only when it is not equal to hardware capability. And also if the num-lanes property is not present in the devicetree update the num_lanes with the maximum hardware supports. Introduce dw_pcie_link_get_max_link_width() to get the maximum lane width the hardware supports. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.c | 11 ++++++++++- drivers/pci/controller/dwc/pcie-designware.h | 1 + 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index ffaded8f2df7..dd56cc02f4ef 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -504,6 +504,9 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 dw_pcie_iatu_detect(pci); =20 + if (pci->num_lanes < 1) + pci->num_lanes =3D dw_pcie_link_get_max_link_width(pci); + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 145e7f579072..967c62cf3db0 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -737,12 +737,21 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie= *pci) =20 } =20 +int dw_pcie_link_get_max_link_width(struct dw_pcie *pci) +{ + u8 cap =3D dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 lnkcap =3D dw_pcie_readl_dbi(pci, cap + PCI_EXP_LNKCAP); + + return FIELD_GET(PCI_EXP_LNKCAP_MLW, lnkcap); +} + static void dw_pcie_link_set_max_link_width(struct dw_pcie *pci, u32 num_l= anes) { + int max_lanes =3D dw_pcie_link_get_max_link_width(pci); u32 lnkcap, lwsc, plc; u8 cap; =20 - if (!num_lanes) + if (!num_lanes || max_lanes =3D=3D num_lanes) return; =20 /* Set the number of lanes */ diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 501d9ddfea16..61d1fb6b437b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -488,6 +488,7 @@ void dw_pcie_write_dbi2(struct dw_pcie *pci, u32 reg, s= ize_t size, u32 val); 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Based upon the number of lanes and the data rate supported, write the preset data read from the device tree in to the lane equalization control registers. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 53 +++++++++++++++++++= ++++ drivers/pci/controller/dwc/pcie-designware.h | 3 ++ include/uapi/linux/pci_regs.h | 3 ++ 3 files changed, 59 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index dd56cc02f4ef..7d5f16f77e2f 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -507,6 +507,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pci->num_lanes < 1) pci->num_lanes =3D dw_pcie_link_get_max_link_width(pci); =20 + ret =3D of_pci_get_equalization_presets(dev, &pp->presets, pci->num_lanes= ); + if (ret) + goto err_free_msi; + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -808,6 +812,54 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) return 0; } =20 +static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_sp= eed speed) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + u8 lane_eq_offset, lane_reg_size, cap_id; + u8 *presets; + u32 cap; + int i; + + if (speed =3D=3D PCIE_SPEED_8_0GT) { + presets =3D (u8 *)pp->presets.eq_presets_8gts; + lane_eq_offset =3D PCI_SECPCI_LE_CTRL; + cap_id =3D PCI_EXT_CAP_ID_SECPCI; + /* For data rate of 8 GT/S each lane equalization control is 16bits wide= */ + lane_reg_size =3D 0x2; + } else if (speed =3D=3D PCIE_SPEED_16_0GT) { + presets =3D pp->presets.eq_presets_Ngts[EQ_PRESET_TYPE_16GTS]; + lane_eq_offset =3D PCI_PL_16GT_LE_CTRL; + cap_id =3D PCI_EXT_CAP_ID_PL_16GT; + lane_reg_size =3D 0x1; + } + + if (presets[0] =3D=3D PCI_EQ_RESV) + return; + + cap =3D dw_pcie_find_ext_capability(pci, cap_id); + if (!cap) + return; + + /* + * Write preset values to the registers byte-by-byte for the given + * number of lanes and register size. + */ + for (i =3D 0; i < pci->num_lanes * lane_reg_size; i++) + dw_pcie_writeb_dbi(pci, cap + lane_eq_offset + i, presets[i]); +} + +static void dw_pcie_config_presets(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + enum pci_bus_speed speed =3D pcie_link_speed[pci->max_link_speed]; + + if (speed >=3D PCIE_SPEED_8_0GT) + dw_pcie_program_presets(pp, PCIE_SPEED_8_0GT); + + if (speed >=3D PCIE_SPEED_16_0GT) + dw_pcie_program_presets(pp, PCIE_SPEED_16_0GT); +} + int dw_pcie_setup_rc(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -861,6 +913,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) PCI_COMMAND_MASTER | PCI_COMMAND_SERR; dw_pcie_writel_dbi(pci, PCI_COMMAND, val); =20 + dw_pcie_config_presets(pp); /* * If the platform provides its own child bus config accesses, it means * the platform uses its own address translation component rather than diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 61d1fb6b437b..30ae8d3f4282 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -25,6 +25,8 @@ #include #include =20 +#include "../../pci.h" + /* DWC PCIe IP-core versions (native support since v4.70a) */ #define DW_PCIE_VER_365A 0x3336352a #define DW_PCIE_VER_460A 0x3436302a @@ -381,6 +383,7 @@ struct dw_pcie_rp { int msg_atu_index; struct resource *msg_res; bool use_linkup_irq; + struct pci_eq_presets presets; }; =20 struct dw_pcie_ep_ops { diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 3445c4970e4d..2cd20170adb4 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1140,6 +1140,9 @@ #define PCI_DLF_CAP 0x04 /* Capabilities Register */ #define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange= Enable */ =20 +/* Secondary PCIe Capability 8.0 GT/s */ +#define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */ + /* Physical Layer 16.0 GT/s */ #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F --=20 2.34.1