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Camera can connect different CSI port. So use dts overlay file to handle these difference connect options. Signed-off-by: Frank Li --- change from v2 to v3 - remove phy nodes change from v1 to v2 - none --- arch/arm64/boot/dts/freescale/Makefile | 12 +++ .../boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso | 90 ++++++++++++++++++= ++++ .../boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso | 90 ++++++++++++++++++= ++++ arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 51 ++++++++++++ .../boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso | 89 ++++++++++++++++++= +++ arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 36 +++++++++ 6 files changed, 368 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/f= reescale/Makefile index 839432153cc7a..d1cbc08eb3f4d 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -261,12 +261,24 @@ dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-apalis-v1.1-eval-v= 1.2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-apalis-v1.1-ixora-v1.1.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-apalis-v1.1-ixora-v1.2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qm-mek.dtb + +imx8qm-mek-ov5640-csi0-dtbs :=3D imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtbo +dtb-${CONFIG_ARCH_MXC} +=3D imx8qm-mek-ov5640-csi0.dtb +imx8qm-mek-ov5640-csi1-dtbs :=3D imx8qm-mek.dtb imx8qm-mek-ov5640-csi1.dtbo +dtb-${CONFIG_ARCH_MXC} +=3D imx8qm-mek-ov5640-csi1.dtb +imx8qm-mek-ov5640-dual-dtbs :=3D imx8qm-mek.dtb imx8qm-mek-ov5640-csi0.dtb= o imx8qm-mek-ov5640-csi1.dtbo +dtb-${CONFIG_ARCH_MXC} +=3D imx8qm-mek-ov5640-dual.dtb + dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-ai_ml.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-colibri-aster.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-colibri-eval-v3.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-colibri-iris.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-mek.dtb + +imx8qxp-mek-ov5640-csi-dtbs :=3D imx8qxp-mek.dtb imx8qxp-mek-ov5640-csi.dt= bo +dtb-${CONFIG_ARCH_MXC} +=3D imx8qxp-mek-ov5640-csi.dtb + dtb-$(CONFIG_ARCH_MXC) +=3D imx8qxp-tqma8xqp-mba8xx.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) +=3D imx93-9x9-qsb.dtb diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso b/ar= ch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso new file mode 100644 index 0000000000000..cfd599db997b9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi0.dtso @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&i2c_mipi_csi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <100000>; + pinctrl-0 =3D <&pinctrl_i2c_mipi_csi0>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ov5640_mipi_0: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&xtal24m>; + clock-names =3D "xclk"; + pinctrl-0 =3D <&pinctrl_mipi_csi0>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&lsio_gpio1 27 GPIO_ACTIVE_LOW>; + AVDD-supply =3D <®_2v8>; + DVDD-supply =3D <®_1v5>; + DOVDD-supply =3D <®_1v8>; + status =3D "okay"; + + port { + ov5640_mipi_0_ep: endpoint { + bus-type =3D ; + data-lanes =3D <1 2>; + remote-endpoint =3D <&mipi_csi0_in>; + }; + }; + }; +}; + +&irqsteer_csi0 { + status =3D "okay"; +}; + +&isi { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + isi_in_2: endpoint { + remote-endpoint =3D <&mipi_csi0_out>; + }; + }; + }; +}; + +&mipi_csi_0 { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mipi_csi0_in: endpoint { + data-lanes =3D <1 2>; + remote-endpoint =3D <&ov5640_mipi_0_ep>; + }; + }; + + port@1 { + reg =3D <1>; + + mipi_csi0_out: endpoint { + remote-endpoint =3D <&isi_in_2>; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso b/ar= ch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso new file mode 100644 index 0000000000000..199a79e98d88b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek-ov5640-csi1.dtso @@ -0,0 +1,90 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2025 NXP + */ + +/dts-v1/; +/plugin/; + +#include +#include + +&i2c_mipi_csi1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <100000>; + pinctrl-0 =3D <&pinctrl_i2c_mipi_csi1>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ov5640_mipi_1: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&xtal24m>; + clock-names =3D "xclk"; + pinctrl-0 =3D <&pinctrl_mipi_csi1>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&lsio_gpio1 31 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&lsio_gpio1 30 GPIO_ACTIVE_LOW>; + AVDD-supply =3D <®_2v8>; + DVDD-supply =3D <®_1v5>; + DOVDD-supply =3D <®_1v8>; + status =3D "okay"; + + port { + ov5640_mipi_1_ep: endpoint { + bus-type =3D ; + data-lanes =3D <1 2>; + remote-endpoint =3D <&mipi_csi1_in>; + }; + }; + }; +}; + +&irqsteer_csi1 { + status =3D "okay"; +}; + +&isi { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@3 { + reg =3D <3>; + + isi_in_3: endpoint { + remote-endpoint =3D <&mipi_csi1_out>; + }; + }; + }; +}; + +&mipi_csi_1 { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mipi_csi1_in: endpoint { + data-lanes =3D <1 2>; + remote-endpoint =3D <&ov5640_mipi_1_ep>; + }; + }; + + port@1 { + reg =3D <1>; + + mipi_csi1_out: endpoint { + remote-endpoint =3D <&isi_in_3>; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot= /dts/freescale/imx8qm-mek.dts index 61ef00f4259e1..3a6e25e08c26a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -155,6 +155,27 @@ usb3_data_ss: endpoint { }; }; =20 + reg_1v5: regulator-1v5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v5"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_2v8: regulator-2v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "2v8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + reg_usdhc2_vmmc: usdhc2-vmmc { compatible =3D "regulator-fixed"; regulator-name =3D "SD1_SPWR"; @@ -727,6 +748,20 @@ IMX8QM_SCU_GPIO0_03_LSIO_GPIO0_IO31 0x0600004c >; }; =20 + pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp { + fsl,pins =3D < + IMX8QM_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + + pinctrl_i2c_mipi_csi1: i2c-mipi-csi1grp { + fsl,pins =3D < + IMX8QM_MIPI_CSI1_I2C0_SCL_MIPI_CSI1_I2C0_SCL 0xc2000020 + IMX8QM_MIPI_CSI1_I2C0_SDA_MIPI_CSI1_I2C0_SDA 0xc2000020 + >; + }; + pinctrl_i2c0: i2c0grp { fsl,pins =3D < IMX8QM_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021 @@ -905,6 +940,22 @@ IMX8QM_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c >; }; =20 + pinctrl_mipi_csi0: mipi-csi0grp { + fsl,pins =3D < + IMX8QM_MIPI_CSI0_GPIO0_00_LSIO_GPIO1_IO27 0xC0000041 + IMX8QM_MIPI_CSI0_GPIO0_01_LSIO_GPIO1_IO28 0xC0000041 + IMX8QM_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + + pinctrl_mipi_csi1: mipi-csi1grp { + fsl,pins =3D < + IMX8QM_MIPI_CSI1_GPIO0_00_LSIO_GPIO1_IO30 0xC0000041 + IMX8QM_MIPI_CSI1_GPIO0_01_LSIO_GPIO1_IO31 0xC0000041 + IMX8QM_MIPI_CSI1_MCLK_OUT_MIPI_CSI1_ACM_MCLK_OUT 0xC0000041 + >; + }; + pinctrl_pciea: pcieagrp { fsl,pins =3D < IMX8QM_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso b/ar= ch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso new file mode 100644 index 0000000000000..0546a2dc2a543 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek-ov5640-csi.dtso @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2024 NXP + */ +/dts-v1/; +/plugin/; + +#include +#include + +&i2c_mipi_csi0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + clock-frequency =3D <100000>; + pinctrl-0 =3D <&pinctrl_i2c_mipi_csi0>; + pinctrl-names =3D "default"; + status =3D "okay"; + + ov5640_mipi: camera@3c { + compatible =3D "ovti,ov5640"; + reg =3D <0x3c>; + clocks =3D <&xtal24m>; + clock-names =3D "xclk"; + pinctrl-0 =3D <&pinctrl_mipi_csi0>; + pinctrl-names =3D "default"; + powerdown-gpios =3D <&lsio_gpio3 7 GPIO_ACTIVE_HIGH>; + reset-gpios =3D <&lsio_gpio3 8 GPIO_ACTIVE_LOW>; + AVDD-supply =3D <®_2v8>; + DVDD-supply =3D <®_1v5>; + DOVDD-supply =3D <®_1v8>; + status =3D "okay"; + + port { + ov5640_mipi_ep: endpoint { + bus-type =3D ; + data-lanes =3D <1 2>; + remote-endpoint =3D <&mipi_csi0_in>; + }; + }; + }; +}; + +&irqsteer_csi0 { + status =3D "okay"; +}; + +&isi { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@2 { + reg =3D <2>; + + isi_in_2: endpoint { + remote-endpoint =3D <&mipi_csi0_out>; + }; + }; + }; +}; + +&mipi_csi_0 { + status =3D "okay"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mipi_csi0_in: endpoint { + data-lanes =3D <1 2>; + remote-endpoint =3D <&ov5640_mipi_ep>; + }; + }; + + port@1 { + reg =3D <1>; + + mipi_csi0_out: endpoint { + remote-endpoint =3D <&isi_in_2>; + }; + }; + }; +}; + diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boo= t/dts/freescale/imx8qxp-mek.dts index 89c6516c5ba90..a356c491375cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -90,6 +90,27 @@ usb3_data_ss: endpoint { }; }; =20 + reg_1v5: regulator-1v5 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v5"; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + }; + + reg_1v8: regulator-1v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "1v8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + }; + + reg_2v8: regulator-2v8 { + compatible =3D "regulator-fixed"; + regulator-name =3D "2v8"; + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + }; + reg_pcieb: regulator-pcie { compatible =3D "regulator-fixed"; regulator-max-microvolt =3D <3300000>; @@ -749,6 +770,13 @@ IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 >; }; =20 + pinctrl_i2c_mipi_csi0: i2c-mipi-csi0grp { + fsl,pins =3D < + IMX8QXP_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 + IMX8QXP_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 + >; + }; + pinctrl_ioexp_rst: ioexprstgrp { fsl,pins =3D < IMX8QXP_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 @@ -789,6 +817,14 @@ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 >; }; =20 + pinctrl_mipi_csi0: mipi-csi0grp { + fsl,pins =3D < + IMX8QXP_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 + IMX8QXP_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 + IMX8QXP_MIPI_CSI0_MCLK_OUT_MIPI_CSI0_ACM_MCLK_OUT 0xC0000041 + >; + }; + pinctrl_pcieb: pcieagrp { fsl,pins =3D < IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 --=20 2.34.1