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Sat, 08 Feb 2025 02:53:41 -0800 (PST) From: Langyan Ye To: neil.armstrong@linaro.org, quic_jesszhan@quicinc.com, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, thierry.reding@gmail.com, sam@ravnborg.org, dianders@chromium.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Langyan Ye Subject: [PATCH v5 2/3] drm/panel: panel-himax-hx83102: support for kingdisplay-kd110n11-51ie MIPI-DSI panel Date: Sat, 8 Feb 2025 18:53:25 +0800 Message-Id: <20250208105326.3850358-3-yelangyan@huaqin.corp-partner.google.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250208105326.3850358-1-yelangyan@huaqin.corp-partner.google.com> References: <20250208105326.3850358-1-yelangyan@huaqin.corp-partner.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kingdisplay-kd110n11-51ie is a 10.95" TFT panel. The MIPI controller on this panel is the same as the other panels here, so add this panel to this driver. Signed-off-by: Langyan Ye Reviewed-by: Douglas Anderson --- drivers/gpu/drm/panel/panel-himax-hx83102.c | 115 ++++++++++++++++++++ 1 file changed, 115 insertions(+) diff --git a/drivers/gpu/drm/panel/panel-himax-hx83102.c b/drivers/gpu/drm/= panel/panel-himax-hx83102.c index c3f4f5ee175d..9a818dea653f 100644 --- a/drivers/gpu/drm/panel/panel-himax-hx83102.c +++ b/drivers/gpu/drm/panel/panel-himax-hx83102.c @@ -494,6 +494,96 @@ static int ivo_t109nw41_init(struct hx83102 *ctx) return dsi_ctx.accum_err; }; =20 +static int kingdisplay_kd110n11_51ie_init(struct hx83102 *ctx) +{ + struct mipi_dsi_multi_context dsi_ctx =3D { .dsi =3D ctx->dsi }; + + msleep(50); + + hx83102_enable_extended_cmds(&dsi_ctx, true); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc4); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D9, 0xd1); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x2c, 0xb3, 0xb3= , 0x31, 0xf1, + 0x33, 0xe0, 0x54, 0x36, 0x36, 0x3a, 0x3a, 0x32, 0x8b, + 0x11, 0xe5, 0x98); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xd9); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x8b, 0x33); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x00, 0x47, 0xb0,= 0x80, 0x00, 0x2c, + 0x80, 0x3c, 0x9f, 0x22, 0x20, 0x00, 0x00, 0x98, 0x51); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x64, 0x64, 0x64, = 0x64, 0x64, 0x64, + 0x40, 0x84, 0x64, 0x84, 0x01, 0x9d, 0x01, 0x02, 0x01, 0x00, + 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETVDC, 0x1b, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_BE, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPTBA, 0xfc, 0xc4, 0x80,= 0x9c, 0x36, 0x00, + 0x0d, 0x04); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSTBA, 0x32, 0x32, 0x22,= 0x11, 0x22, 0xa0, + 0x31, 0x08, 0xf5, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xcc); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTCON, 0x80); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETRAMDMY, 0x97); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPWM, 0x00, 0x1e, 0x13, = 0x88, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x08, 0x13, 0x07= , 0x00, + 0x0f, 0x36); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPANEL, 0x02, 0x03, 0x44= ); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPCTRL, 0x07, 0x06, 0x00= , 0x02, + 0x04, 0x2c, 0xff); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x06, 0x00, 0x00,= 0x00, 0x40, 0x04, + 0x08, 0x04, 0x08, 0x37, 0x07, 0x44, 0x37, 0x2b, 0x2b, 0x03, + 0x03, 0x32, 0x10, 0x22, 0x00, 0x25, 0x32, 0x10, 0x29, 0x00, + 0x29, 0x32, 0x10, 0x08, 0x00, 0x08, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP1, 0x18, 0x18, 0x18,= 0x18, 0x18, 0x18, + 0x18, 0x18, 0x18, 0x18, 0x07, 0x06, 0x07, 0x06, 0x05, 0x04, + 0x05, 0x04, 0x03, 0x02, 0x03, 0x02, 0x01, 0x00, 0x01, 0x00, + 0x18, 0x18, 0x25, 0x24, 0x25, 0x24, 0x1f, 0x1f, 0x1f, 0x1f, + 0x1e, 0x1e, 0x1e, 0x1e, 0x20, 0x20, 0x20, 0x20); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa,= 0x8a, 0xaa, 0xa0, + 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xe0, 0x10, 0x10, = 0x0d, 0x1e, 0x9d, + 0x02, 0x52, 0x9d, 0x14, 0x14); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x01); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETPOWER, 0x01, 0x7f, 0x11= , 0xfd); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETMIPI, 0x4f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x86); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_UNKNOWN_D2, 0x64); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc5); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP0, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa,= 0x8a, 0xaa, 0xa0, + 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x05, 0x15, 0x55, 0x45, + 0x55, 0x50, 0x05, 0x15, 0x55, 0x45, 0x55, 0x50); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0x02, 0x00, 0x24, = 0x01, 0x7e, 0x0f, + 0x7c, 0x10, 0xa0, 0x00, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x02); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCLOCK, 0x03, 0x07, 0x00= , 0x10, 0x7b); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0f, 0x3f, 0xff,= 0xcf, 0xff, 0xf0, + 0x0f, 0x3f, 0xff, 0xcf, 0xff, 0xf0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETTP1, 0xfe, 0x01, 0xfe, = 0x01, 0xfe, 0x01, + 0x00, 0x00, 0x00, 0x23, 0x00, 0x23, 0x81, 0x02, 0x40, 0x00, + 0x20, 0x9d, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x01, 0x00); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x03); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETDISP, 0x66, 0x81); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0xc6); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETCYC, 0x03, 0xff, 0xf8); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETSPCCMD, 0x3f); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETGIP3, 0x0a, 0x2a, 0xaa,= 0x8a, 0xaa, 0xa0, + 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0, 0x0f, 0x2a, 0xaa, 0x8a, + 0xaa, 0xf0, 0x0f, 0x2a, 0xaa, 0x8a, 0xaa, 0xf0, 0x0a, 0x2a, + 0xaa, 0x8a, 0xaa, 0xa0, 0x0a, 0x2a, 0xaa, 0x8a, 0xaa, 0xa0); + mipi_dsi_dcs_write_seq_multi(&dsi_ctx, HX83102_SETBANK, 0x00); + hx83102_enable_extended_cmds(&dsi_ctx, false); + + return dsi_ctx.accum_err; +} + static const struct drm_display_mode starry_mode =3D { .clock =3D 162680, .hdisplay =3D 1200, @@ -582,6 +672,28 @@ static const struct hx83102_panel_desc ivo_t109nw41_de= sc =3D { .init =3D ivo_t109nw41_init, }; =20 +static const struct drm_display_mode kingdisplay_kd110n11_51ie_default_mod= e =3D { + .clock =3D 182750, + .hdisplay =3D 1200, + .hsync_start =3D 1200 + 124, + .hsync_end =3D 1200 + 124 + 80, + .htotal =3D 1200 + 124 + 80 + 80, + .vdisplay =3D 1920, + .vsync_start =3D 1920 + 88, + .vsync_end =3D 1920 + 88 + 8, + .vtotal =3D 1920 + 88 + 8 + 38, + .type =3D DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED, +}; + +static const struct hx83102_panel_desc kingdisplay_kd110n11_51ie_desc =3D { + .modes =3D &kingdisplay_kd110n11_51ie_default_mode, + .size =3D { + .width_mm =3D 147, + .height_mm =3D 235, + }, + .init =3D kingdisplay_kd110n11_51ie_init, +}; + static int hx83102_enable(struct drm_panel *panel) { msleep(130); @@ -809,6 +921,9 @@ static const struct of_device_id hx83102_of_match[] =3D= { { .compatible =3D "ivo,t109nw41", .data =3D &ivo_t109nw41_desc }, + { .compatible =3D "kingdisplay,kd110n11-51ie", + .data =3D &kingdisplay_kd110n11_51ie_desc + }, { .compatible =3D "starry,himax83102-j02", .data =3D &starry_desc }, --=20 2.34.1