From nobody Mon Feb 9 13:36:31 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 66D9F1DE2AD for ; Fri, 7 Feb 2025 18:20:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738952415; cv=none; b=htdJh/PhXLOBQKSZNm5KHHxI1sIsecZm3ikoiC+10p/ThntI/QjstXkXTyKSJRyjlasH2DdupV7keXNTEsr43gSJDqXAJQPCKCdrxZTGJVHD0EdPMHMbUtNF7QE8fr0Ehv5WDurXJ3HXyqspeo7THWhdOIWiIqs7pr7o8/Y3xtA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738952415; c=relaxed/simple; bh=xFsaaePk9tkZWAd3x775QrlPec/RFGLaqZuvfVZs1Wc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=piADxxT8E88NlOx077xT92Z2ZMfloOvlG37rtyR6mSrmVUebNZhNDA8dBnOnJagDunjPY2xJSnRRP6o4MLRQjdMm3Ssj3qOrL1C8lnRPdA+h/MEOKNkRfZgUtE5ADQTENikNIajwBOMDFjY5lLBqgdkt3AI+HwVq3L6Ou5qChHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 784701E32; Fri, 7 Feb 2025 10:20:34 -0800 (PST) Received: from merodach.members.linode.com (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 58FAD3F63F; Fri, 7 Feb 2025 10:20:08 -0800 (PST) From: James Morse To: x86@kernel.org, linux-kernel@vger.kernel.org Cc: Reinette Chatre , Thomas Gleixner , Ingo Molnar , Borislav Petkov , H Peter Anvin , Babu Moger , James Morse , shameerali.kolothum.thodi@huawei.com, D Scott Phillips OS , carl@os.amperecomputing.com, lcherian@marvell.com, bobo.shaobowang@huawei.com, tan.shaopeng@fujitsu.com, baolin.wang@linux.alibaba.com, Jamie Iles , Xin Hao , peternewman@google.com, dfustini@baylibre.com, amitsinght@marvell.com, David Hildenbrand , Rex Nie , Dave Martin , Koba Ko , Shanker Donthineni , Shaopeng Tan , Tony Luck Subject: [PATCH v6 25/42] x86/resctrl: Make prefetch_disable_bits belong to the arch code Date: Fri, 7 Feb 2025 18:18:06 +0000 Message-Id: <20250207181823.6378-26-james.morse@arm.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20250207181823.6378-1-james.morse@arm.com> References: <20250207181823.6378-1-james.morse@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" prefetch_disable_bits is set by rdtgroup_locksetup_enter() from a value provided by the architecture, but is largely read by other architecture helpers. Make resctrl_arch_get_prefetch_disable_bits() set prefetch_disable_bits so that it can be isolated to arch-code from where the other arch-code helpers can use its cached-value. Signed-off-by: James Morse Tested-by: Carl Worth # arm64 Tested-by: Shaopeng Tan Reviewed-by: Shaopeng Tan Reviewed-by: Tony Luck Reviewed-by: Reinette Chatre --- Changes since v5: * Tweaked the word 'export'. * Swapped the second paragraph for Reinette's version. --- arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cp= u/resctrl/pseudo_lock.c index d078b89380dd..13145e744556 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -84,6 +84,8 @@ static const struct class pseudo_lock_class =3D { */ u64 resctrl_arch_get_prefetch_disable_bits(void) { + prefetch_disable_bits =3D 0; + if (boot_cpu_data.x86_vendor !=3D X86_VENDOR_INTEL || boot_cpu_data.x86 !=3D 6) return 0; @@ -99,7 +101,8 @@ u64 resctrl_arch_get_prefetch_disable_bits(void) * 3 DCU IP Prefetcher Disable (R/W) * 63:4 Reserved */ - return 0xF; + prefetch_disable_bits =3D 0xF; + break; case INTEL_ATOM_GOLDMONT: case INTEL_ATOM_GOLDMONT_PLUS: /* @@ -110,10 +113,11 @@ u64 resctrl_arch_get_prefetch_disable_bits(void) * 2 DCU Hardware Prefetcher Disable (R/W) * 63:3 Reserved */ - return 0x5; + prefetch_disable_bits =3D 0x5; + break; } =20 - return 0; + return prefetch_disable_bits; } =20 /** @@ -713,8 +717,7 @@ int rdtgroup_locksetup_enter(struct rdtgroup *rdtgrp) * Not knowing the bits to disable prefetching implies that this * platform does not support Cache Pseudo-Locking. */ - prefetch_disable_bits =3D resctrl_arch_get_prefetch_disable_bits(); - if (prefetch_disable_bits =3D=3D 0) { + if (resctrl_arch_get_prefetch_disable_bits() =3D=3D 0) { rdt_last_cmd_puts("Pseudo-locking not supported\n"); return -EINVAL; } --=20 2.39.2