From nobody Mon Feb 9 13:01:20 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8A914189520 for ; Fri, 7 Feb 2025 16:19:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945189; cv=none; b=Z3Sh6JIrYH4x7ZtICe4AbL+sxhGvNNhs/dQQRoFEuHPt0UHnVxZW+i5J7GIOf2/uSfS7lnyfm9xqcExYva26XqbccY3mNTvrNNZ+YDLBREp7rvD53S+X8CUmoT9n8Ql8Cae3bZrZPkyBvuRdmXgOF9VLwwHuH7eI84hjCZqVCfs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945189; c=relaxed/simple; bh=GF0Hn09KPD012xYnrHRyG4xf0X9wQ9KlAHjX6egHn0Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=OEX5QTypT938s8lOzibxDrlBH1Q4gVdkZvy+pVu7fxwj8O8bDY4Uu50JLCEpeXi1xl9t9MaHfwA3zwjJLQ3px/VU7drPLQ6RHZfYbSfqMJdRVj824q97FqbtnRjHj5NvAcpMuB+9riFyVVzZBMv8rKDJvolcm69kktToncLOPOU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=Fc23NXLD; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="Fc23NXLD" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-435f8f29f8aso16283925e9.2 for ; Fri, 07 Feb 2025 08:19:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1738945186; x=1739549986; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IuJMR1N/b1qpsKDKcoeIqZx9TZLHFvG76FujKxOxlNs=; b=Fc23NXLDEBHIucN065QbvTqtWkcpOLHFSxTTqTfxBfCti6gsOvFFPZ5FPIUfEzis6B FiNGxoGY1GEc67rTyakbMrofh3Ed6/KQeTT8rhdPDUCzdP2mNAOYwBQ1p3D2h/6Tv/gf AhKmMGi6JIVPjGZ/NkJvwNuewo+cuvj7F+wOWfFu66Wvr+IGtN2/Qu10KrL5lqR612mD he1SGLFdVSQO+A6ZIgfYWZqFGFUOkyte+dit8uYnd5sszYwAuwTA8BI+qQb5ZRNyE/dJ movWztGzVEcDwjCKlaYKa++UbHdueBuY+7qhMxxK2xHZIInLFVFZ+brlT6xw6I0AUyGG HnmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738945186; x=1739549986; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IuJMR1N/b1qpsKDKcoeIqZx9TZLHFvG76FujKxOxlNs=; b=N5wbeR20+jCzbZR04S30L7tpk5GZzSJOWX6AxIvtrTO8XXX64UeZojbMYvoQ1aNRWX gTEw1RjSm5XPwkCxBCjMxDsv+F+/wcSL5oGKnrrWgFTYUpJK+kb+rgTBS4j9ngZQgKwB 07jwjIx/4bf1sGiRKv1YKJCd0Lo8x/TcGbMa2We9lVcp9W0EzI7H0fjA/ZDwDVQ1jEvb S2aUru8M5eKaY8OpLttdsZdYlyataMMVpEFOttld3NzYUsb/PopN2X8UKYXwpMgeB1Ez /tMyRqQ+6szh+jd4Mr3cDpnh30Fja/BFclzjZ44VwiGPnDjPm2LXK9r1h3fnLhwzU90K 2Byg== X-Forwarded-Encrypted: i=1; AJvYcCWTOX+FNjXZwsuerLzOii1qpzT3FtaMhY2fns5D23ZIlsILBYvrz2Fo21dSNGvaN5VTLTMTOlTUkoP+NL8=@vger.kernel.org X-Gm-Message-State: AOJu0Yyl4skUdXoNV1PpukiM+d3ZRTUbP4W4hkPZ7Zt6XKAlZ5AMiWi1 u6kcI95CVj/kEwCYN7a/ZnEqcgJ49cCbwOhnk7Z3rRSKQmDmCRJgaW/Vy6Ib630= X-Gm-Gg: ASbGnctkg6P1u3wCx8XSDqICG9HJV4PUmdOGP/XmxXcg9huyywKVD2oppQ2h/4p+/rw BTCOVfFjxASXQ0rNglP55pAmrRkqkqO3JMAJllHWozhiN+6k5a/i6ujTa5nMxa3ogVTQYSQRQmm k334rKJeome0JP9ulziQtVTtjnNcwu5rCan2eXSrFzjCm8OptJAlvNQpEAgpifmhJSrRyIa1MnF bZBTE12+sECZeUCpo67pdL7Rug2apL0Usv+aQEbPKutFyTeT5gde+3NWr6I4GzVTFKmHrWUxFsm 9uw0soVt5HOD0/enazQzPgJolMLm3DXZTjZbRjCjRB420C4ZVgijKb+L1w== X-Google-Smtp-Source: AGHT+IF2QBiK/6fJgHT5gF+3avImUBiADzRKV6TlV+pcR6wlIV7GNBKNVzGepoKdRql8iUw7eoyotg== X-Received: by 2002:a05:6000:1787:b0:38d:a876:845a with SMTP id ffacd0b85a97d-38dc959fab9mr2553003f8f.47.1738945185782; Fri, 07 Feb 2025 08:19:45 -0800 (PST) Received: from localhost (089144193052.atnat0002.highway.a1.net. [89.144.193.52]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dc6c80df2sm3037899f8f.18.2025.02.07.08.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 08:19:45 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel Subject: [PATCH 1/9] riscv: Annotate unaligned access init functions Date: Fri, 7 Feb 2025 17:19:41 +0100 Message-ID: <20250207161939.46139-12-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207161939.46139-11-ajones@ventanamicro.com> References: <20250207161939.46139-11-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Several functions used in unaligned access probing are only run at init time. Annotate them appropriately. Fixes: f413aae96cda ("riscv: Set unaligned access speed at compile time") Signed-off-by: Andrew Jones Reviewed-by: Alexandre Ghiti --- arch/riscv/include/asm/cpufeature.h | 4 ++-- arch/riscv/kernel/traps_misaligned.c | 8 ++++---- arch/riscv/kernel/unaligned_access_speed.c | 14 +++++++------- 3 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 569140d6e639..19defdc2002d 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -63,7 +63,7 @@ void __init riscv_user_isa_enable(void); #define __RISCV_ISA_EXT_SUPERSET_VALIDATE(_name, _id, _sub_exts, _validate= ) \ _RISCV_ISA_EXT_DATA(_name, _id, _sub_exts, ARRAY_SIZE(_sub_exts), _valida= te) =20 -bool check_unaligned_access_emulated_all_cpus(void); +bool __init check_unaligned_access_emulated_all_cpus(void); #if defined(CONFIG_RISCV_SCALAR_MISALIGNED) void check_unaligned_access_emulated(struct work_struct *work __always_unu= sed); void unaligned_emulation_finish(void); @@ -76,7 +76,7 @@ static inline bool unaligned_ctl_available(void) } #endif =20 -bool check_vector_unaligned_access_emulated_all_cpus(void); +bool __init check_vector_unaligned_access_emulated_all_cpus(void); #if defined(CONFIG_RISCV_VECTOR_MISALIGNED) void check_vector_unaligned_access_emulated(struct work_struct *work __alw= ays_unused); DECLARE_PER_CPU(long, vector_misaligned_access); diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index 7cc108aed74e..aacbd9d7196e 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -605,7 +605,7 @@ void check_vector_unaligned_access_emulated(struct work= _struct *work __always_un kernel_vector_end(); } =20 -bool check_vector_unaligned_access_emulated_all_cpus(void) +bool __init check_vector_unaligned_access_emulated_all_cpus(void) { int cpu; =20 @@ -625,7 +625,7 @@ bool check_vector_unaligned_access_emulated_all_cpus(vo= id) return true; } #else -bool check_vector_unaligned_access_emulated_all_cpus(void) +bool __init check_vector_unaligned_access_emulated_all_cpus(void) { return false; } @@ -659,7 +659,7 @@ void check_unaligned_access_emulated(struct work_struct= *work __always_unused) } } =20 -bool check_unaligned_access_emulated_all_cpus(void) +bool __init check_unaligned_access_emulated_all_cpus(void) { int cpu; =20 @@ -684,7 +684,7 @@ bool unaligned_ctl_available(void) return unaligned_ctl; } #else -bool check_unaligned_access_emulated_all_cpus(void) +bool __init check_unaligned_access_emulated_all_cpus(void) { return false; } diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index 91f189cf1611..b7a8ff7ba6df 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -121,7 +121,7 @@ static int check_unaligned_access(void *param) return 0; } =20 -static void check_unaligned_access_nonboot_cpu(void *param) +static void __init check_unaligned_access_nonboot_cpu(void *param) { unsigned int cpu =3D smp_processor_id(); struct page **pages =3D param; @@ -175,7 +175,7 @@ static void set_unaligned_access_static_branches(void) modify_unaligned_access_branches(&fast_and_online, num_online_cpus()); } =20 -static int lock_and_set_unaligned_access_static_branch(void) +static int __init lock_and_set_unaligned_access_static_branch(void) { cpus_read_lock(); set_unaligned_access_static_branches(); @@ -218,7 +218,7 @@ static int riscv_offline_cpu(unsigned int cpu) } =20 /* Measure unaligned access speed on all CPUs present at boot in parallel.= */ -static int check_unaligned_access_speed_all_cpus(void) +static int __init check_unaligned_access_speed_all_cpus(void) { unsigned int cpu; unsigned int cpu_count =3D num_possible_cpus(); @@ -264,7 +264,7 @@ static int check_unaligned_access_speed_all_cpus(void) return 0; } #else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ -static int check_unaligned_access_speed_all_cpus(void) +static int __init check_unaligned_access_speed_all_cpus(void) { return 0; } @@ -379,7 +379,7 @@ static int riscv_online_cpu_vec(unsigned int cpu) } =20 /* Measure unaligned access speed on all CPUs present at boot in parallel.= */ -static int vec_check_unaligned_access_speed_all_cpus(void *unused __always= _unused) +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused _= _always_unused) { schedule_on_each_cpu(check_vector_unaligned_access); =20 @@ -393,13 +393,13 @@ static int vec_check_unaligned_access_speed_all_cpus(= void *unused __always_unuse return 0; } #else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ -static int vec_check_unaligned_access_speed_all_cpus(void *unused __always= _unused) +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused _= _always_unused) { return 0; } #endif =20 -static int check_unaligned_access_all_cpus(void) +static int __init check_unaligned_access_all_cpus(void) { bool all_cpus_emulated, all_cpus_vec_unsupported; =20 --=20 2.48.1 From nobody Mon Feb 9 13:01:20 2026 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9265A18DB04 for ; Fri, 7 Feb 2025 16:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945193; cv=none; b=KUh9eeoRnKG/rIk2fN9IWYHRxHxSJx5EglZliMRRJfAWluTAxNx27PuPSlr9aFeBCKYq7uS2VrI4zy0wyKIRh2bp9h5WpqETlTo5AF9n7JnI/YXd48C9wtSX4T3y8kbC5Z/QX5K/QnKXsxlPgJ63ahevPq8pAkXOmFEJVWJ+liY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945193; c=relaxed/simple; bh=c9+jGsuHaZ58BvCwmZlEGmua3y5mogvp457gXg6onTM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UlJWwfC7OaWnEEVpURdeCJMreBrlcMHH/W9Y/D65GuJeGDiir5uFz94Uksfb267O+CDgAb+LRGi5OO0aSaZMsxA4lx00sRMS/ptj1+QEWE31ZQ9KFKE9/m+yYFUfkM2Cr89gqtGwmVMeJEr0dQwCWfLg9UbUSvUXEChTxPj0W/A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=bcK40DDS; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="bcK40DDS" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-436a39e4891so15775495e9.1 for ; Fri, 07 Feb 2025 08:19:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1738945190; x=1739549990; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=voJ+wA65lTYRPtl00Mu/vMvJWZVBpxfrm7iohsFL00w=; b=bcK40DDSH4de9kkQ6GdKs1gzGf9R3llcem2KmMmEZClk67SWjqvcQDvYN7NepuywEa iygDJyvyPv/QXU7ujBIlIRF5UEQT5fPdBwLJUVnnX5ql1welT+clZzHofyKhQxyYnEla XQYgNRy9xuV6wBUj0WsBP2T/J0HZxJAGMivjFuvI0CIJuMIwZmCo0yjvm8XRMKsk1eOw /6/DY3WQmWld0MR5U+OXvxsDSOymxDR9L2rVX96XmKFb+lgSv+k6gAOaFUA1wt2MKhrI 5WYT0xGmF71oicb1ozP2stHOTPPOX1U4UtEyK5k3wzjGSEEBciL79Quthd1Tex9p6WVO K9LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738945190; x=1739549990; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=voJ+wA65lTYRPtl00Mu/vMvJWZVBpxfrm7iohsFL00w=; b=CSs+QVbfLCpYLUXZT831JEjEeTFX9dODNY1VxgfdMFh4VTOKhy8O0t5WBfjSOT/2c5 3B41Dhs9IzEWb8l6BrWaHNKkPZClbhlY3dtK01HdZZPJA8kWDjOBHlsovtjncqIBFm8J p2QINoakk83u0TjYN5ef1B7UFRfkB0FNcgg1Txql0nNdt0CK+m+BIAjMeC7taervRMRV 058rym8OvjS4gqausdou0DjyDJ1TvqE0pXXIg99DICnj9Md4+ZcvTUByHuYRW/cg8PZH MnViWoyl5vXSwujgf8rvSTusFfuiae3grmFMw9o89GJGrTd8EghBFLA5G2BDYMfT8aNq vGeg== X-Forwarded-Encrypted: i=1; AJvYcCUaqf1XUriGvQtB4Ly35bTJ5BmYJS1mG0EuzAYvEAOEOZ00dTGBI88WgUdUI1gjp1pyxkQwgRiQiUu0Log=@vger.kernel.org X-Gm-Message-State: AOJu0YznSCzqgdAx81gAYA3ph3iJsH/DV69ElGzbi4wH/VqxWmI3ymum urDMP11JxtP4SRt5tzHD/BQ3/yMn4XAVFS3sjbiLz/RkpxasQWFGO++lVrlxoLM= X-Gm-Gg: ASbGnct4PjE9mMMVHHiUF0qFxVBSfsqMYhEzpZRn8tGqJExU8MYYiprrIp15heR7c0k nzYaDeuHC9hkFgBwSJbbkoHA4vybRTRh/M/8rM6lbPO5P0mJfTwRZLV+LOuxtY8LNTBwK28jyQg g2t63BqREctjztd4Il3GsPWMzIjFjCwoNwgNPfDj6BGMkRvP95h6G9/IoVRniaIL7Iga+OCZpMJ aIj0ZpVK0CL9WLDrQp4zkPZy6sYyxUFzog6AXwV+FxqqaB11IC8Awb4K++frDu5l5ich8j0ItEd LUWDj1+y0LjsFgMsGt7mjIh7ajaOB0/g7IsRr7WhrwUaZfgTkH64xcVeIw== X-Google-Smtp-Source: AGHT+IGx7QtVfT1JWtMIVcFCuUhUKogTMnYDmeTHogDn6k+cWvy1lOJNfmJ1oXM4MfFvDJRwJ1K8fg== X-Received: by 2002:a05:600c:4687:b0:430:563a:b20a with SMTP id 5b1f17b1804b1-4392498b3b5mr43554075e9.11.1738945189904; Fri, 07 Feb 2025 08:19:49 -0800 (PST) Received: from localhost (089144193052.atnat0002.highway.a1.net. [89.144.193.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390d94db77sm94595135e9.15.2025.02.07.08.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 08:19:49 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel Subject: [PATCH 2/9] riscv: Fix riscv_online_cpu_vec Date: Fri, 7 Feb 2025 17:19:42 +0100 Message-ID: <20250207161939.46139-13-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207161939.46139-11-ajones@ventanamicro.com> References: <20250207161939.46139-11-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" We shouldn't probe when we already know vector is unsupported and we should probe when we see we don't yet know whether it's supported. Furthermore, we should ensure we've set the access type to unsupported when we don't have vector at all. Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe") Signed-off-by: Andrew Jones Reviewed-by: Alexandre Ghiti --- arch/riscv/kernel/unaligned_access_speed.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index b7a8ff7ba6df..161964cf2abc 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -367,10 +367,12 @@ static void check_vector_unaligned_access(struct work= _struct *work __always_unus =20 static int riscv_online_cpu_vec(unsigned int cpu) { - if (!has_vector()) + if (!has_vector()) { + per_cpu(vector_misaligned_access, cpu) =3D RISCV_HWPROBE_MISALIGNED_VECT= OR_UNSUPPORTED; return 0; + } =20 - if (per_cpu(vector_misaligned_access, cpu) !=3D RISCV_HWPROBE_MISALIGNED_= VECTOR_UNSUPPORTED) + if (per_cpu(vector_misaligned_access, cpu) !=3D RISCV_HWPROBE_MISALIGNED_= VECTOR_UNKNOWN) return 0; =20 check_vector_unaligned_access_emulated(NULL); --=20 2.48.1 From nobody Mon Feb 9 13:01:20 2026 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A722A18B47C for ; Fri, 7 Feb 2025 16:20:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945203; cv=none; b=UwTYDvyzPGFoiHKx+D2fBG4A+pqy1e5qPxvS6xjKX9atzzhZQw1aBYvxSbYgKbeEzbgwEe7mWdEj0/rV35a5AaDmr0p7CQjSY/7Oybq5i+si+ZW+ppd2iBAtATd3kLZp/7hT7L1syhcCVVHUlhimD8Z1vxGK1MRtAgvs5flsalw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945203; c=relaxed/simple; bh=TflZ8vFhqqgukB3ZACwgUQtCjZPFs1P05Aa8hDY99Ac=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Er2ldTfrZrYApqaGHkyP47uuYBWnDwKfrkBYUipLovuuRU0ziHqBgS7skN0joSWYukvadrVBuwswzP2KFFmqprRNWprboXbddLei5qp2E55ncLW+b/t7ejnmTm3pUWaPETjn0HgiODaW2bbGOlEd/TVzpyxXmbKnxCnAHc97jZY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=f35H008O; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="f35H008O" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-43621d27adeso15719175e9.2 for ; Fri, 07 Feb 2025 08:20:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1738945200; x=1739550000; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2fCHXwdFaeXSBwfTQI74JIYWCeXWis7TCtNv1LZo0xM=; b=f35H008OFN44lBNNekFfdZVYPqN+tLgii7HZJQPrPn4r8rQ9BzOzHgKZVE179xRcg1 Y2Rh94/QNLAGBN8BOWRaG7Q+ZpWPqh2ekKvns72VmiRNi8cOsHIeEKRQVAvyJl9OjeLy ELrWXQtoA6sUgLHiKmE097GfZBjDXdeSW/zs8HFgDnVnNGldMEdPZ57zuUz0Wd1lzIe1 VOv9io3MMo83R7GDnStbJ28J6MJ9IDp3iOHMuXtRmkcY0QWUwg0QoyolZ2YupaY4e9vl KVrRgArxhuWDf93MbIQ+j828kRHUInMijZebfPU1xWejriiieQjrnPGRRUmsxfwaemQ+ sN2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738945200; x=1739550000; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2fCHXwdFaeXSBwfTQI74JIYWCeXWis7TCtNv1LZo0xM=; b=nrwi10nszBc8BVwWhYLD7+qVJ8GYL+MZFgiGLDYRd/tDtsoEwlHd4TCIteEa30v+Pn aDNBEUNs+dDfVQqnllduMUZpt/JanL4En6WfDFiH6oSxZp/TUiKQEW3qy1B1lu8+M/BS i8hXRQW+WCPX8WMbJDIK47X3CWPF1xTMtUV9zVjr0Vg24R2w13w9q8mvV8XAmOWymTsk QrSRctMbRNGpk+F4eAIHkRxUhzN7acEHxxc/zPb7jzf7U9GPBGdDGK8jfVcQqgU+MN2w fBxXvhafAnCnKO0/lmNmOQ0M7RlKYrDxXBzLkuzM5Q6/FG9j4z2l8wrBWYkG+CZ6tGeJ W+MQ== X-Forwarded-Encrypted: i=1; AJvYcCV4nWTbDEnAUf1Fs3dRCCQoAUV6FqegG3QC/MC6W8yDX1opYjn6dl68pT5omCnvDXUlywNybNzMblMxlmU=@vger.kernel.org X-Gm-Message-State: AOJu0YzHbxELBx4dgEq7hjqDUV6XT0KdzGbNaxF+G17Xs8r4KjFzrOXV bv7gK9BbtmCjbD7FdJWNgAlTQ0q/nRyF/CeFPbf4riPUSByo/xaC0kMF2WyPo4Q= X-Gm-Gg: ASbGncvPbFZ0Vm5rMFVAtGmvDlcw7rdwwGi43GWYabCwyUuy5vfthRT3g8FhT84E650 JqWSsx8+GTJHXCzdRgo/MXORLhecVWfOBeFFKw+jgUuQLfsXJm+EQkWANHbOBo+5BAsMhUEspno 8fuil2GBHKqIuxYT4OVCu8SMTIo2/+LJAhmkdlsyg8NFuciSvwBUvfOrzyYGXWpg4Rrb9T1Tjqs j7T7oY9DNBz9KRhj1NU4ZIoi/QHTHLRFDgqJ3NSZ4Sz75xK1tJaPFRO6Bw/V15rseqS7CZVmMrK MgcYmvk0fx7Hv/IjZehEYwVZ9NqFxUyO/o19/o9CvA0uSECghW+HKtxAvw== X-Google-Smtp-Source: AGHT+IFhySvKCOlwcj4Qxz8J3e5OCL6BcBFdracdimWviE7gGpdopqanQ+HxZIazvgx44GvoG2zmWA== X-Received: by 2002:a5d:457a:0:b0:38d:b610:190b with SMTP id ffacd0b85a97d-38dc9350d85mr2241809f8f.46.1738945199927; Fri, 07 Feb 2025 08:19:59 -0800 (PST) Received: from localhost (089144193052.atnat0002.highway.a1.net. [89.144.193.52]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde0fd23sm4860354f8f.71.2025.02.07.08.19.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 08:19:59 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel Subject: [PATCH 3/9] riscv: Fix check_unaligned_access_all_cpus Date: Fri, 7 Feb 2025 17:19:43 +0100 Message-ID: <20250207161939.46139-14-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207161939.46139-11-ajones@ventanamicro.com> References: <20250207161939.46139-11-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" check_vector_unaligned_access_emulated_all_cpus(), like its name suggests, will return true when all cpus emulate unaligned vector accesses. If the function returned false it may have been because vector isn't supported at all (!has_vector()) or because at least one cpu doesn't emulate unaligned vector accesses. Since false may be returned for two cases, checking for it isn't sufficient when attempting to determine if we should proceed with the vector speed check. Move the !has_vector() functionality to check_unaligned_access_all_cpus() in order for check_vector_unaligned_access_emulated_all_cpus() to return false for a single case. Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe") Signed-off-by: Andrew Jones Reviewed-by: Alexandre Ghiti --- arch/riscv/kernel/traps_misaligned.c | 6 ------ arch/riscv/kernel/unaligned_access_speed.c | 11 +++++++---- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps= _misaligned.c index aacbd9d7196e..4354c87c0376 100644 --- a/arch/riscv/kernel/traps_misaligned.c +++ b/arch/riscv/kernel/traps_misaligned.c @@ -609,12 +609,6 @@ bool __init check_vector_unaligned_access_emulated_all= _cpus(void) { int cpu; =20 - if (!has_vector()) { - for_each_online_cpu(cpu) - per_cpu(vector_misaligned_access, cpu) =3D RISCV_HWPROBE_MISALIGNED_VEC= TOR_UNSUPPORTED; - return false; - } - schedule_on_each_cpu(check_vector_unaligned_access_emulated); =20 for_each_online_cpu(cpu) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index 161964cf2abc..02b485dc4bc4 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -403,13 +403,16 @@ static int __init vec_check_unaligned_access_speed_al= l_cpus(void *unused __alway =20 static int __init check_unaligned_access_all_cpus(void) { - bool all_cpus_emulated, all_cpus_vec_unsupported; + bool all_cpus_emulated; + int cpu; =20 all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus(); - all_cpus_vec_unsupported =3D check_vector_unaligned_access_emulated_all_c= pus(); =20 - if (!all_cpus_vec_unsupported && - IS_ENABLED(CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS)) { + if (!has_vector()) { + for_each_online_cpu(cpu) + per_cpu(vector_misaligned_access, cpu) =3D RISCV_HWPROBE_MISALIGNED_VEC= TOR_UNSUPPORTED; + } else if (!check_vector_unaligned_access_emulated_all_cpus() && + IS_ENABLED(CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS)) { kthread_run(vec_check_unaligned_access_speed_all_cpus, NULL, "vec_check_unaligned_access_speed_all_cpus"); } --=20 2.48.1 From nobody Mon Feb 9 13:01:20 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 095C8182D9 for ; Fri, 7 Feb 2025 16:20:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945207; cv=none; b=XugmY+qxnosfWjTdFDMCcW36TiKGNUUQSCVhoarXIHK13teUMtzxvMJPH4PFRpMNPDvGBW3L6UdQktONI+HvJmzDVsPMH4DlzaQqRpgRQducnIh/nhkKPeI2PplQ6I2jhOoUGaIfq5ue73OUSaYqwPg+CyXoIcPxTQlDt6ManW4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945207; c=relaxed/simple; bh=gt6Fw2XKGx6sF/gq8i36RjjcfICtnuHbiXOCGkVO0kk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=L2VjbfRxSqG/zzBaTcFVyWAol0IzuPVynkTBNdY2+PBuJOlK5/Nl9JUFfw7LiV14meFBrj0GTDLtQpiFoVSitHJNSmc9qJ2bVDVghWtDtUM7gz5czBA6YB+ETwzMWo8lKq5rqjHpYlhfTXsSQA34bAlhUb0D+6zyiVuv+btQzMY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=KftCLIi6; arc=none smtp.client-ip=209.85.128.52 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="KftCLIi6" Received: by mail-wm1-f52.google.com with SMTP id 5b1f17b1804b1-4361b6f9faeso13800465e9.1 for ; Fri, 07 Feb 2025 08:20:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1738945204; x=1739550004; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=uuW8lN3LlL4CuR3qOD5OEg9Po1ieu6WyRch8wZV6JCU=; b=KftCLIi6LniKERuAr+Q46HtLLq8dziUGUzUgH1F5/hkgui98HXRtszKAggsoZ2RtVh 6HDDZEXDDuOmYoVF7NGJpp4lhxHDObvVHeeQFUL7kWptPixOhQnaQkY9QcWjmoKLvEiZ FREgClRHfp1z+0CcCophxk5+6fxi5p+sZVYkcJwZqhjQSkSRrawTu3vkk17JiphzRUEU 705GgeT3WEFBNdJmDf21k8N84q7dbspKCmEzDA2MfY67mbKGhB/UJhZ1jBoADVPk/wVg Td2iNf+830SLw2zQuqf9am9dC+BL/u00AGXY0gDZ2fmWrGaOSyjsj5rGgXXbhkH31B8I DLpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738945204; x=1739550004; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=uuW8lN3LlL4CuR3qOD5OEg9Po1ieu6WyRch8wZV6JCU=; b=ZbmNTq23YKOJWChCLzEV/bAz+KR4GSI77k6XshNn/oHYcO31m/C8zzSTrY1FlHd3tF ZTlSyJkuQuvXVthSj5MD1RZtwSZ2hUz1p0S0X+SZTWhSvxapY2VEDnWTHl0nAi8RT8X1 YCNbN7nA/Yt87YH5jcO0+O9WCgG4Lmkq5nKKbdgXXjV1NJmhC6jp7fUwiELiqgGoJ6K4 fzwvVXk1dl1tuxuKu0M73sjcrhKzVkLx2/GaXvmw270syMfhpLWCz8d+g4guCBFzM4Vl Unr74owTa774+em4fFriW98fu9BVK6ORfkPdE3lQachRLgW4Y08h0eGZsb/EWuyeIxdt 3utA== X-Forwarded-Encrypted: i=1; AJvYcCVbxgzEmlc9eHJKw3GtTNwMQMHkQQcfsGE1OXQWZ5t5+9GOlnRoEKpPAamUVUj3xCIW5/xPS9Nzq2NGjKs=@vger.kernel.org X-Gm-Message-State: AOJu0YwXevv03Gf/iQXiAOJx47FpHGNEhsLvnVveE6MDfOQBI/1hUehY LlL/MVX0JfPRmPbvmjTTa3SZir7x9bSt9xjV3+a1IxNyjN8tBwfwqbXcAQEOPW0= X-Gm-Gg: ASbGncsTW8Bv55kxNAiRUPjnVBkF1HjhOJghIyRB218AlAvpW7kQ+CBkG+dDrTQXwWF OPIWjPPuXSTN8BdusoytdPz8/gDsPSQrvRPB+PFhmG2DPEQZDXctsXBzNAbao1dlsw3n9p2SeZf 322L708oinVe/EM3dBA+5rwPRtIglHbpZc0AVpursPflOI3y1x6To6wSGzk10bmWTi774113Eer A17eYsJxwp/EnVB/ImbvrsA2tujUXu3IEM1Hc6oRMWVzwI0bKrvdgpuWc38SWvGs3dGTa9zL9rK A3iAgQV721B+Bfoj19KVMiDQLxrHhN15wLH2fxCqFnill71adEiu7qD0Zw== X-Google-Smtp-Source: AGHT+IGMKi65e/Z5vWbx7WgCmphLVzyy3Q2WyYGIC9JFl7WcR1tKm4dOZKbtrD9rcb9U1JUgAquIdw== X-Received: by 2002:a05:600c:6c01:b0:436:1b77:b5aa with SMTP id 5b1f17b1804b1-43912d22565mr59485145e9.8.1738945203976; Fri, 07 Feb 2025 08:20:03 -0800 (PST) Received: from localhost (089144193052.atnat0002.highway.a1.net. [89.144.193.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391da96640sm62546005e9.8.2025.02.07.08.20.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 08:20:03 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel Subject: [PATCH 4/9] riscv: Change check_unaligned_access_speed_all_cpus to void Date: Fri, 7 Feb 2025 17:19:44 +0100 Message-ID: <20250207161939.46139-15-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207161939.46139-11-ajones@ventanamicro.com> References: <20250207161939.46139-11-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The return value of check_unaligned_access_speed_all_cpus() is always zero, so make the function void so we don't need to concern ourselves with it. The change also allows us to tidy up check_unaligned_access_all_cpus() a bit. Signed-off-by: Andrew Jones Reviewed-by: Alexandre Ghiti Reviewed-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/unaligned_access_speed.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index 02b485dc4bc4..780f1c5f512a 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -218,7 +218,7 @@ static int riscv_offline_cpu(unsigned int cpu) } =20 /* Measure unaligned access speed on all CPUs present at boot in parallel.= */ -static int __init check_unaligned_access_speed_all_cpus(void) +static void __init check_unaligned_access_speed_all_cpus(void) { unsigned int cpu; unsigned int cpu_count =3D num_possible_cpus(); @@ -226,7 +226,7 @@ static int __init check_unaligned_access_speed_all_cpus= (void) =20 if (!bufs) { pr_warn("Allocation failure, not measuring misaligned performance\n"); - return 0; + return; } =20 /* @@ -261,12 +261,10 @@ static int __init check_unaligned_access_speed_all_cp= us(void) } =20 kfree(bufs); - return 0; } #else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ -static int __init check_unaligned_access_speed_all_cpus(void) +static void __init check_unaligned_access_speed_all_cpus(void) { - return 0; } #endif =20 @@ -403,10 +401,10 @@ static int __init vec_check_unaligned_access_speed_al= l_cpus(void *unused __alway =20 static int __init check_unaligned_access_all_cpus(void) { - bool all_cpus_emulated; int cpu; =20 - all_cpus_emulated =3D check_unaligned_access_emulated_all_cpus(); + if (!check_unaligned_access_emulated_all_cpus()) + check_unaligned_access_speed_all_cpus(); =20 if (!has_vector()) { for_each_online_cpu(cpu) @@ -417,9 +415,6 @@ static int __init check_unaligned_access_all_cpus(void) NULL, "vec_check_unaligned_access_speed_all_cpus"); } =20 - if (!all_cpus_emulated) - return check_unaligned_access_speed_all_cpus(); - return 0; } =20 --=20 2.48.1 From nobody Mon Feb 9 13:01:20 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFD17182D9 for ; Fri, 7 Feb 2025 16:20:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945224; cv=none; b=O4wICwXQrYQOXpyQ7VUsfPJC0TAwBYKjaf3fi1E4/hnA0av33xQq8lwkO8az76vN7e/o6jhEZ93DnkbVfaBLqAEKbZkkDSkaNdS5JzMnOmiwk9GmqC0KPte81iEmqrbSfXOnTgdszozXdEqBYQ0lFJuZXNFOyxr+dmfnyLd7siw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945224; c=relaxed/simple; bh=uu6MdVyaN06kGkmx0osoY1uJGP5t5zipJf5Cj8Cyixw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=iHoxFbTtTxBrkmf/VeJYEjKstSYJTL5/pzqTpj35hPUsygksUPLQDXzvCozROuaM1Y7jO198iGPd5X81kY16ay5cbo8cjg6kynMxcQVWTTc5bXk3ogVazv2n2Qqil63bAKrhNRTxups3P+HBX82bqMjya3rG5waLuMjd+jQuOMY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=QF6C5SIx; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="QF6C5SIx" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-436249df846so15709755e9.3 for ; Fri, 07 Feb 2025 08:20:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1738945221; x=1739550021; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EPC+Zc9/VMADj7AL3TU4wV27hjuGZt3xK3eoVREeXu0=; b=QF6C5SIxatnSWGg2Hfad0METKiBPBEqsh+RaJqcJXPMgViPwD5OCP6MpUlPK3CS9Hm VFwu9rKKAmmQsVwGLEfdXNjRcDOMHDrcycFy+Cn3sRFWtFu71Hdwa6o8nX6syDTyCfDd PHNDKU2po5YQAjU/cmi95prYwmw/jIh7G3ZleAhumftv34mLr6dSN9tjk1JaRtHOww4z IKtnUsBnbzi7iK+nc3PKgMllknSlNKpu7D+xO4AVnF/HmNDD6tTzczAxiNsrpN5gIcM7 rqqRxjFZ8YRadnfwMzOhXs71Rg7ALOerz0S+Uj0hUuh9Z8Bv/u7dTNtcWdgJzopXbHjM pKHg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738945221; x=1739550021; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EPC+Zc9/VMADj7AL3TU4wV27hjuGZt3xK3eoVREeXu0=; b=eoKGldBeiO5pgCtpkqRGh8cGLH1US+qfa8V5YaaFaWdK+TsRlRv59b0OoGNyUoRMJE BRvE8a0DxNQn7RhMyjr+LNmwHidtioX/MQBi2o6rVyIx8uv6Ai79bthIeBmNIRnGLFS/ pCdSCxFdz2QzLoIHJWHnV9qY34vit9m7NU0Rpgmupy2Dvs55nbvMaZAX0hZIs055kXhp 3PLSbnSAyu0VbO8Makcnm/gcxY6/4pi2MDjzJe8y3aPen66ceqjIxd4B7xku3LhhBFfA Y6TxCaJJL+wRTh03pq6arf6MbccrXxpsDGfudxYqEKAkGZlk0U3SA2PWcQX8lTvPdSER d4xg== X-Forwarded-Encrypted: i=1; AJvYcCVf6etE/kPqLtjsLuKnaXEe4FaGjI4cjiKy70TwuSAgWbJ8h8U/sQSyd6+a2YHcyGSO4bz18HIHB8m+NRA=@vger.kernel.org X-Gm-Message-State: AOJu0Yx2VOlUw60HXVS37u6BYpfOPephrm+C5Sw7NGXpfHfcEGFLzGIG cL0Zs0vgL2S2jS2hiPp6N7/BRqytPu91D4KEsQd9j9tbJUPGTLxhWvFqZYviCfE= X-Gm-Gg: ASbGncs8WfOrUPiTCSIw2pH7rL8nVh83/dcrQ5jRsysy2uLRikTCmZembuU67H3O6bL 8M/6gXJV/59U1aovbupU6W5jigp1mK0+mlVrcXsfBwJKzZPwlldx+r4NyXHu8c9eo9n6vZ2cKPt HThJY+eYIAomEpedyjkJSLy27yl6CDVjtGTqM9XqNXyFSCglYBl5hXoGk5jMnpZus9k/jvK/IiT QQMR8Q+1bdmA4yIQ10E9MjFIwTDGN1ylamcZ8yADr4T1zl/glGWji6aryDeRKo3vqQVwC6OrW4a rsGXI44BlRgPbkGM5CHcmeigoTsNLbczn4Q3FqN0e/+weRY3kuVauOQu4Q== X-Google-Smtp-Source: AGHT+IGFd0vA7i2TE/EqWQzSneLkfz1wZqI3DHki2JEKLR0vkj9VuQIpV1+0LuH7EO7EbRwBTj9qwg== X-Received: by 2002:a05:600c:3c9b:b0:436:5fc9:30ba with SMTP id 5b1f17b1804b1-439249c385cmr37153945e9.29.1738945221124; Fri, 07 Feb 2025 08:20:21 -0800 (PST) Received: from localhost (089144193052.atnat0002.highway.a1.net. [89.144.193.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43907f16ffasm77934055e9.1.2025.02.07.08.20.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 08:20:20 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel Subject: [PATCH 5/9] riscv: Fix set up of cpu hotplug callbacks Date: Fri, 7 Feb 2025 17:19:45 +0100 Message-ID: <20250207161939.46139-16-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207161939.46139-11-ajones@ventanamicro.com> References: <20250207161939.46139-11-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CPU hotplug callbacks should be set up even if we detected all current cpus emulate misaligned accesses, since we want to ensure our expectations of all cpus emulating is maintained. Fixes: 6e5ce7f2eae3 ("riscv: Decouple emulated unaligned accesses from acce= ss speed") Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe") Signed-off-by: Andrew Jones Reviewed-by: Alexandre Ghiti Reviewed-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/unaligned_access_speed.c | 27 +++++++++++----------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index 780f1c5f512a..c9d3237649bb 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -247,13 +247,6 @@ static void __init check_unaligned_access_speed_all_cp= us(void) /* Check core 0. */ smp_call_on_cpu(0, check_unaligned_access, bufs[0], true); =20 - /* - * Setup hotplug callbacks for any new CPUs that come online or go - * offline. - */ - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", - riscv_online_cpu, riscv_offline_cpu); - out: for_each_cpu(cpu, cpu_online_mask) { if (bufs[cpu]) @@ -383,13 +376,6 @@ static int __init vec_check_unaligned_access_speed_all= _cpus(void *unused __alway { schedule_on_each_cpu(check_vector_unaligned_access); =20 - /* - * Setup hotplug callbacks for any new CPUs that come online or go - * offline. - */ - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", - riscv_online_cpu_vec, NULL); - return 0; } #else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ @@ -415,6 +401,19 @@ static int __init check_unaligned_access_all_cpus(void) NULL, "vec_check_unaligned_access_speed_all_cpus"); } =20 + /* + * Setup hotplug callbacks for any new CPUs that come online or go + * offline. + */ +#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS + cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", + riscv_online_cpu, riscv_offline_cpu); +#endif +#ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS + cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", + riscv_online_cpu_vec, NULL); +#endif + return 0; } =20 --=20 2.48.1 From nobody Mon Feb 9 13:01:20 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0973918BC06 for ; Fri, 7 Feb 2025 16:20:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945235; cv=none; b=cv20XRFNmVAH3HLi4tLw4hByhHZbp7w8m0/Dxz83EjBvD8QALOtVcVgQ4kp6rUW/KtoewkoqMo52zLmzzR2GBVZXYNRFLYKtzdcU3I8m3v7/AzsK46nVKKNMOMDSspmOakF0SNtnSEhH/NPWL1KL4QN13cBv2J6gDiZ/AU1Mxt8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945235; c=relaxed/simple; bh=0LXMXurC6Gawyvm4E1zu7tPTj1mQzsTQk7nAEio62/g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gYxF3EFhGXgvI4kPZadhiWd052hnKAEzX8ZcBPRK4YCUGBbDIbOGmB0y2rSj3PXcNoNB7vUhfuRmGBnYC89UN5Gd8iuB4ZslG4LDyiL0cEX3NTtfUVSFpMsu8BfLu4MM1GAFYYtb5e6/ZI9Aum2I7ncJIayTWxgP/76pklMQGQE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=AdoiEivH; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="AdoiEivH" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-38a25d4b9d4so1116837f8f.0 for ; Fri, 07 Feb 2025 08:20:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1738945232; x=1739550032; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Po82zolBmxhVPQkc00G0dtG6NMWIt9O8oQKIvW2rpQo=; b=AdoiEivHcdjrbGutj9ZmFSqjLBDNHZ8W33Hj4oinPCcJvpPsYeMssg+uRYQdOzkPrV FTsbXr1gfxwrMghFueJbOCvpHKvx/zteD/W//1pKc9derb/i6pg9p9gq/ajvdd4h11YW 5yr8CKagF21GMU01dI7bc8obWdSM2LNAeykCnNk2wJrB+5FDAldKV24IUNcxsT17aoS5 dNQK2KrdYB4HRVwSl0niQsXMq8Z5cpVdVaWoNrvfqHsA6q8zAjCxUwFZupUjlwgwBSnc XK85M2zPo3qzy2agvL398/EihlaC/Ez2x2FlBV+f9ECU5dzVddbFnXZ1YtsdCVgGUM+u TPBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738945232; x=1739550032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Po82zolBmxhVPQkc00G0dtG6NMWIt9O8oQKIvW2rpQo=; b=DyXowioMiwSZQLxYHu8QpZVz5MBH3qpQegNKhTXDZC6FCGotP+jIjuSWu9RE3H0f/T QPcqQlMBb4C44t5AtNtFnAwh0rDXK5M/s/Q0OLWRO8F3Wo34h3P4FrkHJ/40KYaSIKNH fC/jzH+mG9v/Ae/2l1YXakWF3AHNk9TJMFVcCdLCoU/AYCqkCu+TYLlPV8/yBGS4S8J+ 492wi2uBkRszI9/uqJ4kbdbaQFrTDD4Xp4cGgldo0uJv9wP/3zLn5DIi0YrjcWkwtd+j kPWBlWpwOr2j1mwwp37fE5JZIJVwoOFhtzRsSHqIEC8CWusM5qKbWVEujmPylrCelqzX 95tQ== X-Forwarded-Encrypted: i=1; AJvYcCXzgj+1EYeclusdx3Mr1kg1PSaOYbXRkKAwAD7YZxAndtNtIsz22sp5fo87gdPvirGYfd+tEMO6Lr2d//c=@vger.kernel.org X-Gm-Message-State: AOJu0Ywk0I6WrAPr3QWnTwFpKfeUQXInz37GDB+3mnNSjf4XwE4IS9CK 7bmSDeuOBL/l6LiH89s2V7WvHTezdsdKvkJfF7TNi1xLDGEyXU039mkipr01914= X-Gm-Gg: ASbGncsHyiWHdwBzbJ/hEquP2iSHcRmJkyrQlw8s/zMzD/nT0BJZjhkJ/KhcztJRonr QSwp6rVBMab9M9wP1mhRdp4EgBjW6alqaxKzb4PDKlKNb1PcmGb2BbmaiR6ec3KBO/1ZrxJf5+q Ba0CTBea0kHnrjiyztUSEKwomiteg73rikhojNXyc3D1i1HlkME4sMlCKeMQ5/2zMF7dEzBstOv XTO4ZC1RxUzAkIMq9V0xVQjL5x09P6KYfPsJqjaVSmX0xwPl5PbSFTJipo2mN2i1pFrkqKJpS39 h1YcYtmt6wke2+KlJo/SrPC/Wp2shLOansUbIu0Fzwycg+GpB3dnpQ62eA== X-Google-Smtp-Source: AGHT+IFYzRkLD2/iNXs8ekCwva+Q7XAjeoRJSdBX1SHt2e7DvSU1eBo/Pp0WwXjQHrpcwp7IId0zvg== X-Received: by 2002:a5d:598d:0:b0:38d:ac2d:6dbc with SMTP id ffacd0b85a97d-38dc8dc1ab0mr2372712f8f.17.1738945232146; Fri, 07 Feb 2025 08:20:32 -0800 (PST) Received: from localhost (089144193052.atnat0002.highway.a1.net. [89.144.193.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4390db10b2fsm94032895e9.33.2025.02.07.08.20.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 08:20:31 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel Subject: [PATCH 6/9] riscv: Fix set up of vector cpu hotplug callback Date: Fri, 7 Feb 2025 17:19:46 +0100 Message-ID: <20250207161939.46139-17-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207161939.46139-11-ajones@ventanamicro.com> References: <20250207161939.46139-11-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Whether or not we have RISCV_PROBE_VECTOR_UNALIGNED_ACCESS we need to set up a cpu hotplug callback to check if we have vector at all, since, when we don't have vector, we need to set vector_misaligned_access to unsupported rather than leave it the default of unknown. Fixes: e7c9d66e313b ("RISC-V: Report vector unaligned access speed hwprobe") Signed-off-by: Andrew Jones Reviewed-by: Alexandre Ghiti --- arch/riscv/kernel/unaligned_access_speed.c | 31 +++++++++++----------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index c9d3237649bb..d9d4ca1fadc7 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -356,6 +356,20 @@ static void check_vector_unaligned_access(struct work_= struct *work __always_unus per_cpu(vector_misaligned_access, cpu) =3D speed; } =20 +/* Measure unaligned access speed on all CPUs present at boot in parallel.= */ +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused _= _always_unused) +{ + schedule_on_each_cpu(check_vector_unaligned_access); + + return 0; +} +#else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ +static int __init vec_check_unaligned_access_speed_all_cpus(void *unused _= _always_unused) +{ + return 0; +} +#endif + static int riscv_online_cpu_vec(unsigned int cpu) { if (!has_vector()) { @@ -363,27 +377,16 @@ static int riscv_online_cpu_vec(unsigned int cpu) return 0; } =20 +#ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS if (per_cpu(vector_misaligned_access, cpu) !=3D RISCV_HWPROBE_MISALIGNED_= VECTOR_UNKNOWN) return 0; =20 check_vector_unaligned_access_emulated(NULL); check_vector_unaligned_access(NULL); - return 0; -} - -/* Measure unaligned access speed on all CPUs present at boot in parallel.= */ -static int __init vec_check_unaligned_access_speed_all_cpus(void *unused _= _always_unused) -{ - schedule_on_each_cpu(check_vector_unaligned_access); +#endif =20 return 0; } -#else /* CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS */ -static int __init vec_check_unaligned_access_speed_all_cpus(void *unused _= _always_unused) -{ - return 0; -} -#endif =20 static int __init check_unaligned_access_all_cpus(void) { @@ -409,10 +412,8 @@ static int __init check_unaligned_access_all_cpus(void) cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", riscv_online_cpu, riscv_offline_cpu); #endif -#ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", riscv_online_cpu_vec, NULL); -#endif =20 return 0; } --=20 2.48.1 From nobody Mon Feb 9 13:01:20 2026 Received: from mail-wr1-f47.google.com (mail-wr1-f47.google.com [209.85.221.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88B15188A3B for ; Fri, 7 Feb 2025 16:20:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945244; cv=none; b=PoiDMQeM2O7x4xsypQy2s1TiqWDCUHQb4gKkBxj1BMZ2l/0+Wmlja1qX0CBPKLC7Pc1RbBfCvwlCsiw2z3ixKxJ+g2LNnYQfnMHZEbWwJNfTkDmYSP2kcG9/tRUBbPGdwMbVXdP/LMUj+3Kz8RtW9SKe8aqQ2pMiZUiY2jqF73c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945244; c=relaxed/simple; bh=klAskR1qF2MHdG7hXASfNr2IJY8c+S7DOai4tT9TPY0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=khxP/62OZ1NZuNBoDsjgcR+xLohSUnopIUqM38hwTP2gbb2u1T38U81FkEKVXKbtw6VpjGNh1njU8DjBW+BlGS17cWuJ45jQnxwnRKJFdzpxo9M97Hn0Go6JJcDQfomqbNNdRG2qVyABc0gMNGkk1++//ofXOF60af9irzJKcq0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=m5H9b6wm; arc=none smtp.client-ip=209.85.221.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="m5H9b6wm" Received: by mail-wr1-f47.google.com with SMTP id ffacd0b85a97d-38daf09d37fso1595968f8f.1 for ; Fri, 07 Feb 2025 08:20:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1738945240; x=1739550040; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rZV9Bvxyy8oBnqpcvuhP90zRC/EQE6fM7xvGU71P15A=; b=m5H9b6wm6kkFCgR8RzXWbJqf0VWFgqWD/jHMxUMpF7nZRdO0RSTRDJKm0cSgxLZ3SW vt0xG/eldLhNabJYniK+//0G+a62zwfJpW+45jxxdQ5YjVshZeWVtt8SRjNuVDsKcC51 VS7bvvK1vjYw00lGjDnbVdKwOEAYjRZzsP2d1PGueO8U9ecdvWc8/Rz1y7gq2jZCDivh vmxfZ8KAb2lXqEHMW9v4gtJe/kvFi9ecojqvQiQ6FHewZIvkaEzYtvn6JVe/lH5HHTuR sgemZaAZtrJ/7c7hag1eNw2CJI6ELdL8LDwnoiloeTbfxDqDdhqur94oaPLEDl9++DnI tVQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738945240; x=1739550040; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rZV9Bvxyy8oBnqpcvuhP90zRC/EQE6fM7xvGU71P15A=; b=fy6StCQZwU/6Dkr1EIHhLwzX8mffjC3gM/jGkHJawm03WlMbFE0v+5hp1Y6EP2czG1 fnIpmbn8RslZsRQ9aZRKem3LlbOVbvyBOkBuT3yLypCxaF9jgGALWAxa8YXKhIMJHJh2 f3V639BF/W3dK12PvcraWr7vM1lpWMoUeVsCRdynTqdVmyBPltMQLozS5FXVqA+9rs9b DVQz39rm1HqHVtFQWK8R0d7OeqO0lCBPkzwQeI4P4FCHJ3qUpySKILD1HsyOI5zODSSF b7O6hYxFXz7kUyo59dinPVpPFbmvbmjd1TGHJFY0uUAqyBIgTszIkO93/w9/eqn3D0aK aFiw== X-Forwarded-Encrypted: i=1; AJvYcCUgcfVo9egDt+htxxu/2RforIQxz9tjwkfRhmoLF5z+H5/rNhRsUbQ84AoTpRsAvRR0vRx6G0GPo1ssqWU=@vger.kernel.org X-Gm-Message-State: AOJu0YzG5+ypQYuB+igdrrL+J44SrJeYugbNoXfcEYxe4ofeEy0INOmG UITL8xBe0Hzobocf/ZCuYDluY1eKqLsoKiqT4N0YjygMjpJsH809wLRzPySlhMM4ATGG4cMsjQw nbsE= X-Gm-Gg: ASbGncvtH1ERC+of0H58SJ/h7Q8NqeOl9aao55noLz2byF7sghm63ZQBqTZ7S4VPCE5 tlsRrQbsbOD/btbqvmWeos4lFekQXjIkqyanK9AkLLCD3OdIN8Hu1XttkVG1C2jwuiLAM6vgGy8 LudiWQHGFy5ltuC12ZUxuqnvtwTU87ZdA10jZLYyh2qz5v7bF7Lx5kJ0P7eWcA5T27dOtfH+vjb /tuW5DTPIIDyt1D64Vo/lIVhX/mqReoo6D8fbjJUqtFs/+xARfrcB5HVA6lEY136GRpqCi6e0IP SDFpURfT9QIqce8YN+1R+pnt+d4JQ837k18SjJS2By0RKDej78IhNXgqOA== X-Google-Smtp-Source: AGHT+IEOg6IG0kjsFKTvz6AcKlvyJUvdpYugEgGxtXEalKSZMbMjvynoGIK3ylHbblQH+CwYP9eGsQ== X-Received: by 2002:a5d:588e:0:b0:38d:d274:4533 with SMTP id ffacd0b85a97d-38dd2745860mr6721f8f.55.1738945240610; Fri, 07 Feb 2025 08:20:40 -0800 (PST) Received: from localhost (089144193052.atnat0002.highway.a1.net. [89.144.193.52]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbdd1af32sm5010225f8f.16.2025.02.07.08.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 08:20:40 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel Subject: [PATCH 7/9] riscv: Prepare for unaligned access type table lookups Date: Fri, 7 Feb 2025 17:19:47 +0100 Message-ID: <20250207161939.46139-18-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207161939.46139-11-ajones@ventanamicro.com> References: <20250207161939.46139-11-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Probing unaligned accesses on boot is time consuming. Provide a function which will be used to look up the access type in a table by id registers. Vendors which provide table entries can then skip the probing. Signed-off-by: Andrew Jones --- arch/riscv/kernel/unaligned_access_speed.c | 114 ++++++++++++--------- 1 file changed, 66 insertions(+), 48 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index d9d4ca1fadc7..f8497097e79d 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -130,6 +130,50 @@ static void __init check_unaligned_access_nonboot_cpu(= void *param) check_unaligned_access(pages[cpu]); } =20 +/* Measure unaligned access speed on all CPUs present at boot in parallel.= */ +static void __init check_unaligned_access_speed_all_cpus(void) +{ + unsigned int cpu; + unsigned int cpu_count =3D num_possible_cpus(); + struct page **bufs =3D kcalloc(cpu_count, sizeof(*bufs), GFP_KERNEL); + + if (!bufs) { + pr_warn("Allocation failure, not measuring misaligned performance\n"); + return; + } + + /* + * Allocate separate buffers for each CPU so there's no fighting over + * cache lines. + */ + for_each_cpu(cpu, cpu_online_mask) { + bufs[cpu] =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); + if (!bufs[cpu]) { + pr_warn("Allocation failure, not measuring misaligned performance\n"); + goto out; + } + } + + /* Check everybody except 0, who stays behind to tend jiffies. */ + on_each_cpu(check_unaligned_access_nonboot_cpu, bufs, 1); + + /* Check core 0. */ + smp_call_on_cpu(0, check_unaligned_access, bufs[0], true); + +out: + for_each_cpu(cpu, cpu_online_mask) { + if (bufs[cpu]) + __free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER); + } + + kfree(bufs); +} +#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ +static void __init check_unaligned_access_speed_all_cpus(void) +{ +} +#endif + DEFINE_STATIC_KEY_FALSE(fast_unaligned_access_speed_key); =20 static void modify_unaligned_access_branches(cpumask_t *mask, int weight) @@ -186,8 +230,17 @@ static int __init lock_and_set_unaligned_access_static= _branch(void) =20 arch_initcall_sync(lock_and_set_unaligned_access_static_branch); =20 +static bool check_unaligned_access_table(void) +{ + return false; +} + static int riscv_online_cpu(unsigned int cpu) { + if (check_unaligned_access_table()) + goto exit; + +#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS static struct page *buf; =20 /* We are already set since the last check */ @@ -203,6 +256,7 @@ static int riscv_online_cpu(unsigned int cpu) =20 check_unaligned_access(buf); __free_pages(buf, MISALIGNED_BUFFER_ORDER); +#endif =20 exit: set_unaligned_access_static_branches(); @@ -217,50 +271,6 @@ static int riscv_offline_cpu(unsigned int cpu) return 0; } =20 -/* Measure unaligned access speed on all CPUs present at boot in parallel.= */ -static void __init check_unaligned_access_speed_all_cpus(void) -{ - unsigned int cpu; - unsigned int cpu_count =3D num_possible_cpus(); - struct page **bufs =3D kcalloc(cpu_count, sizeof(*bufs), GFP_KERNEL); - - if (!bufs) { - pr_warn("Allocation failure, not measuring misaligned performance\n"); - return; - } - - /* - * Allocate separate buffers for each CPU so there's no fighting over - * cache lines. - */ - for_each_cpu(cpu, cpu_online_mask) { - bufs[cpu] =3D alloc_pages(GFP_KERNEL, MISALIGNED_BUFFER_ORDER); - if (!bufs[cpu]) { - pr_warn("Allocation failure, not measuring misaligned performance\n"); - goto out; - } - } - - /* Check everybody except 0, who stays behind to tend jiffies. */ - on_each_cpu(check_unaligned_access_nonboot_cpu, bufs, 1); - - /* Check core 0. */ - smp_call_on_cpu(0, check_unaligned_access, bufs[0], true); - -out: - for_each_cpu(cpu, cpu_online_mask) { - if (bufs[cpu]) - __free_pages(bufs[cpu], MISALIGNED_BUFFER_ORDER); - } - - kfree(bufs); -} -#else /* CONFIG_RISCV_PROBE_UNALIGNED_ACCESS */ -static void __init check_unaligned_access_speed_all_cpus(void) -{ -} -#endif - #ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS static void check_vector_unaligned_access(struct work_struct *work __alway= s_unused) { @@ -370,6 +380,11 @@ static int __init vec_check_unaligned_access_speed_all= _cpus(void *unused __alway } #endif =20 +static bool check_vector_unaligned_access_table(void) +{ + return false; +} + static int riscv_online_cpu_vec(unsigned int cpu) { if (!has_vector()) { @@ -377,6 +392,9 @@ static int riscv_online_cpu_vec(unsigned int cpu) return 0; } =20 + if (check_vector_unaligned_access_table()) + return 0; + #ifdef CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS if (per_cpu(vector_misaligned_access, cpu) !=3D RISCV_HWPROBE_MISALIGNED_= VECTOR_UNKNOWN) return 0; @@ -392,13 +410,15 @@ static int __init check_unaligned_access_all_cpus(voi= d) { int cpu; =20 - if (!check_unaligned_access_emulated_all_cpus()) + if (!check_unaligned_access_table() && + !check_unaligned_access_emulated_all_cpus()) check_unaligned_access_speed_all_cpus(); =20 if (!has_vector()) { for_each_online_cpu(cpu) per_cpu(vector_misaligned_access, cpu) =3D RISCV_HWPROBE_MISALIGNED_VEC= TOR_UNSUPPORTED; - } else if (!check_vector_unaligned_access_emulated_all_cpus() && + } else if (!check_vector_unaligned_access_table() && + !check_vector_unaligned_access_emulated_all_cpus() && IS_ENABLED(CONFIG_RISCV_PROBE_VECTOR_UNALIGNED_ACCESS)) { kthread_run(vec_check_unaligned_access_speed_all_cpus, NULL, "vec_check_unaligned_access_speed_all_cpus"); @@ -408,10 +428,8 @@ static int __init check_unaligned_access_all_cpus(void) * Setup hotplug callbacks for any new CPUs that come online or go * offline. */ -#ifdef CONFIG_RISCV_PROBE_UNALIGNED_ACCESS cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", riscv_online_cpu, riscv_offline_cpu); -#endif cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "riscv:online", riscv_online_cpu_vec, NULL); =20 --=20 2.48.1 From nobody Mon Feb 9 13:01:20 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 89A8318C932 for ; Fri, 7 Feb 2025 16:20:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945248; cv=none; b=H1y2nHWGAPgwU1M1w/hAaFKDmOUbUHdh9F3v31qN94pDjx4H4MKnfDsXM5k3Gi4n+X7aaDmcG1IkIXk+AHe9Tl5DvHWdNbzzNL93v+TAdt0YaJqg2bzjBcImjv48gj4+QbvAhFsGfOsqlBRk2jCZE1jSGMH4dTlVxqxOnV7Gx9Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945248; c=relaxed/simple; bh=yWRp054inoCg1j5o1hnrkV6ngQjA7+hHYhm0VHnZIzQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dSPC0YupnwTSzsM3Tu4QOyZdhSQD8y776Oc8hWtsatYy3jfm3vWHEYbvgn6LwRwUokK/nI1dj16w6zY3oCC2MYIipPcruSz8ahCYg3oU44gkjJKaZJ+k64umLVz1X9G7xHUPj7QyxmNv9UUZn9abyMm5RWA/tmbnVjOif+IMhj4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=lPfFGX2k; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="lPfFGX2k" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-4361e89b6daso15301835e9.3 for ; Fri, 07 Feb 2025 08:20:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1738945245; x=1739550045; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZaGa43r2JveY8ihF44rUo4WO7W9CMxjRpmYKl91QS2U=; b=lPfFGX2knhBGtGjHzVndRoSRYaSuT8FFqV6VwDtx5e33hwXjgubZWDibG4cbhHuXfC T8ZBRv9Kh98QPDgmOAc/mpk4JBa3OXA2cVnAiSYSGkumtGnX9b8QnV2g3MdDcHTLuvGt KK4bS+WIF3PMZx5DWH24Gwhr3maI3+BAATcKd20N7AepzbqL7eGEcb0NVlVpSzkV+0kE DCUK/kFGSkZHfFqD+dijg1iSity9pF92EowI04nxy+o958wiNzrFxhbMOe/msP0pMYLI iWMAtlL3erV8rlrSFAsg7DHnYuYJLojesAGr1ueyLEl6esM9gqegzd9tQNT5kUVbO2he aRjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738945245; x=1739550045; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZaGa43r2JveY8ihF44rUo4WO7W9CMxjRpmYKl91QS2U=; b=j+m+CsRH8MeXKLxxcHXloTt23Fk7IRgMHfKfGeUwqBa9G5TjpJD589HibwICSdmWl6 DcUe6Ne++Gv2PdR/ABCRY4WbqoMeR4VutmGOJrVYGt2mQJWqSAggcuPToVE9b6ncws93 u0Fmy/R5z431YKbOEBXoXyqYmkdm4LOw/BGnDbiPpcEOyY/E5tFNHuTWofhZXBVXTNnz M6szd3wwrGO+vgF+6YyxwjgizszwJ0UBzOHGCDwz5Au7Os0P7QhOUxNr2ROlMxKdvus6 M8yolhk/rA6/ZN7GlzvCwvK3ilnkmfUSW3h7vttLzTSCad+E6gT+wx5fuT2E2A/z/J6x 0eiw== X-Forwarded-Encrypted: i=1; AJvYcCXjeS5sorQfQM80k55WTKQLnLc79OcUUOJJfdygI6tBXXhYDRrfBnmxman5TzCsmEFWTajtiGq5CJbTozw=@vger.kernel.org X-Gm-Message-State: AOJu0YzSrLBZAq4SZo79KkHcPeSyM5yEVgSh8qLQg+KCakFau3iANqqG EgJPBTxwXtkGNm5i4UlkmIybxYbYtmYjdJ5C60GqcTkz8IzVjoTjM4wrnDBJc3s= X-Gm-Gg: ASbGnctYBmLtByKvpEnu+bAbT99jnAHF2L9hbv+6LV5eFYguq4dwc8z0jYZvesp0Bg4 otJZ+nWaTUsCgmvyP0bfwtcNusfQJfdbqUWYxEQAD7PtgBuv6YDQpSpLayBXdxCDsl2cPa2T7D1 06AjJJKJ1prCFz7QaT0pcQWYNXiqejTUMBIvGzH3IdwtSf83yADfxyNVi0Gc9vdWoEJI0FCOVA3 ZRlsJrjzV7pyRH+LZYdEStHKGv9YZephqh9ROgY8OIW+SGkfEhqlP2BXe2q8tndS5MWrc1LF/Lj jKMlmDHUYBsQbVEGfPPgOgRQLGbTxxdOiz+/L6lE453nNkODhjfTYZ58vQ== X-Google-Smtp-Source: AGHT+IEsxHTbv/ApYqI1Db4PbE3wHNdmjENh4/dQ6JTZy1CmXAHF/WRV8cibN7pL6QAb7qvzWGRwaQ== X-Received: by 2002:a05:600c:6a88:b0:434:fbda:1f44 with SMTP id 5b1f17b1804b1-439249a4033mr32953915e9.19.1738945244744; Fri, 07 Feb 2025 08:20:44 -0800 (PST) Received: from localhost (089144193052.atnat0002.highway.a1.net. [89.144.193.52]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-38dbde0ff44sm4891569f8f.76.2025.02.07.08.20.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 08:20:44 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel Subject: [PATCH 8/9] riscv: Implement check_unaligned_access_table Date: Fri, 7 Feb 2025 17:19:48 +0100 Message-ID: <20250207161939.46139-19-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207161939.46139-11-ajones@ventanamicro.com> References: <20250207161939.46139-11-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Define the table entry type and implement the table lookup to find unaligned access types by id registers which is used to skip probing. Signed-off-by: Andrew Jones --- arch/riscv/kernel/unaligned_access_speed.c | 91 +++++++++++++++++++++- 1 file changed, 89 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index f8497097e79d..bd6db4c42daf 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -12,6 +12,7 @@ #include #include #include +#include #include =20 #include "copy-unaligned.h" @@ -230,11 +231,89 @@ static int __init lock_and_set_unaligned_access_stati= c_branch(void) =20 arch_initcall_sync(lock_and_set_unaligned_access_static_branch); =20 -static bool check_unaligned_access_table(void) +/* + * An unaligned_access_table_entry maps harts (or collections of harts) to + * unaligned access types. @level is used to determine whether @marchid an= d/or + * @mimpid should to be considered. All (level, mvendorid, marchid, mimpid) + * tuples formed from each table entry must be unique. + */ +enum id_level { + LEVEL_VENDOR, + LEVEL_ARCH, + LEVEL_IMP, +}; +struct unaligned_access_table_entry { + enum id_level level; + u32 mvendorid; + ulong marchid; + ulong mimpid; + long type; +}; + +static struct unaligned_access_table_entry unaligned_access_table_entries[= ] =3D { +}; + +/* + * Search unaligned_access_table_entries[] for the most specific match, + * i.e. if there are two entries, one with mvendorid =3D V and level =3D V= ENDOR + * and another with mvendorid =3D V, level =3D ARCH, and marchid =3D A, th= en + * a hart with {V,A,?} will match the latter while a hart with {V,!A,?} + * will match the former. + */ +static bool __check_unaligned_access_table(int cpu, long *ptr, int nr_entr= ies, + struct unaligned_access_table_entry table[]) { + struct unaligned_access_table_entry *entry, *match =3D NULL; + u32 mvendorid =3D riscv_cached_mvendorid(cpu); + ulong marchid =3D riscv_cached_marchid(cpu); + ulong mimpid =3D riscv_cached_mimpid(cpu); + int i; + + for (i =3D 0; i < nr_entries; ++i) { + entry =3D &table[i]; + + switch (entry->level) { + case LEVEL_VENDOR: + if (!match && entry->mvendorid =3D=3D mvendorid) { + /* The match, unless we find an ARCH or IMP level match. */ + match =3D entry; + } + break; + case LEVEL_ARCH: + if (entry->mvendorid =3D=3D mvendorid && entry->marchid =3D=3D marchid)= { + /* The match, unless we find an IMP level match. */ + match =3D entry; + } + break; + case LEVEL_IMP: + if (entry->mvendorid =3D=3D mvendorid && entry->marchid =3D=3D marchid = && + entry->mimpid =3D=3D mimpid) { + match =3D entry; + goto matched; + } + break; + } + } + + if (match) { +matched: + *ptr =3D match->type; + return true; + } + return false; } =20 +static bool check_unaligned_access_table(void) +{ + int cpu =3D smp_processor_id(); + long *ptr =3D per_cpu_ptr(&misaligned_access_speed, cpu); + + return __check_unaligned_access_table(cpu, ptr, + ARRAY_SIZE(unaligned_access_table_entries), + unaligned_access_table_entries); +} + static int riscv_online_cpu(unsigned int cpu) { if (check_unaligned_access_table()) @@ -380,9 +459,17 @@ static int __init vec_check_unaligned_access_speed_all= _cpus(void *unused __alway } #endif =20 +static struct unaligned_access_table_entry vec_unaligned_access_table_entr= ies[] =3D { +}; + static bool check_vector_unaligned_access_table(void) { - return false; + int cpu =3D smp_processor_id(); + long *ptr =3D per_cpu_ptr(&vector_misaligned_access, cpu); + + return __check_unaligned_access_table(cpu, ptr, + ARRAY_SIZE(vec_unaligned_access_table_entries), + vec_unaligned_access_table_entries); } =20 static int riscv_online_cpu_vec(unsigned int cpu) --=20 2.48.1 From nobody Mon Feb 9 13:01:20 2026 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74ABD18DB2A for ; Fri, 7 Feb 2025 16:20:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945253; cv=none; b=LWZ6j2cTRw7PEKkHfbn6kDpNEOlVp6v+JNSn5FHv5/ZKSIxKUJwT/1EnGeAvKNx/t1A8wlsGusGTkFglc8EYgnSgaWc+HiQ/2pJIaZM3sJPIlu1XYf+y/nHlc1YwMXzaXa+l0dkrz55ic4jfKOA9ozxmAKEKFKKKo3JrRTKWnUI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738945253; c=relaxed/simple; bh=VWulZbyMlvVfWcva0zZ+7aqmPxY7IsOKefhX2tzM4Xo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P5lxExXFdVsMoQYHBU1ClhdLvCoUm+pWzAEQA21K1v0v1rcnROUdWyM27iEqVW0ZIBv8Ckpf+51JKaxERIAgJJjgcQr2UHQEJCkDd+Q2Q1Vk+afmDVMwQUyHSkS44RpNL3Tx6MmC7hMo15aGdk2wFrGK1WSO+lLcqfivLHLHGPo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com; spf=pass smtp.mailfrom=ventanamicro.com; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b=EdX+e7ob; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ventanamicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=ventanamicro.com header.i=@ventanamicro.com header.b="EdX+e7ob" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43690d4605dso15884065e9.0 for ; Fri, 07 Feb 2025 08:20:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1738945250; x=1739550050; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EXWq8j6voTaeGRr8J3gg8YAr/RtfWvANeWegFFYO8S4=; b=EdX+e7obc8XknsVYN0HTifu9gY5XLTK5MKKLRpAnzWCtePNaYz1Tv2ROsSo5/BwA9X DAE0WBjqpdszp8GAavlTIY4a89Ii5sMbXFsxn3NQjJdkEaA8Hvd/kUmXBBvOqU7pkPlO ypyvftQMQ2u0efMlFHgaVCdtRZ76JICtO6EI33VxBWJYBaOlNEb1Z3iiYRUHM6TtYdGS IwICyXjVctEegGo62UhFVzqhLG2aXTqaIZKVbGzGvsRUshV+7/Bb6QjIgZ6xOZ1s4WiX xdIFRULAv1fFIKWdaXvMWZZObVIrorToQJsiKzIIiGJfTASt9t7aQ8E+9L4nIdJ6rKS7 Y51A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1738945250; x=1739550050; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EXWq8j6voTaeGRr8J3gg8YAr/RtfWvANeWegFFYO8S4=; b=Ouwv/ry9+kLaXEBHuG2Ol+Cr1qE4zqPO+Hj4rbE3ZipDYmz74QReez7Qo1vpjKFFuL hUfwqAlp5hAWzCOV/oBQcVsoTHfWJJznxex2ARlzogA30Z4EtWca+TJiBGuHt/a3coTT 2CCm1tWId9q8aMIjmRmjQTIMChW32BswtGSArhaPcs87KtXqKB1VpQuxaQ+4cPnLWcRA PicjAtXsccZWYRQqsz5SALWlN1nO8FA+NSGnbxfsUC4hF9L+TvBuOvZQyM//28SL50iR myPPbTsoq6tRO7Hbq3PmZsuM5V5MGmooJ0WcW1+iOWmVg/0K/pMexanfsQHf5CJhOeF6 uk3Q== X-Forwarded-Encrypted: i=1; AJvYcCXi9G51PWH5x5f5D+1unyyef3dUtiupm1DRrj204o2B9Cz+UNGj2y7wDwKUK0MtI0DJ1WNEhu0eronbiuw=@vger.kernel.org X-Gm-Message-State: AOJu0YxC/0RoJv6oY5RB8Ba/aJTNu6AFFBGWSAyqKkCi+Y/eXSMc1j51 5+GBOcQmBjvkW4i36adSYr6lG2gOv+PG3Ro3btQJ+rMD8JGWwzkaoqRYoQ6HOpo= X-Gm-Gg: ASbGnctxxeGqTVPkTv8VU577N+7lWR6DfScKU1tQRFVn8jl7tombivipIVQBxY5PxhB hK/aREi6nc+j+FZ3ub7F3njXemQXOu9zHmzq61yLpyQQwcXsQ5oYZ9KV/ojEb4dkVadtnNqkLxS cevTLcaJyGbdjSPnJVNkb//EhPgqLSOqUWVNRqycbS4dO6VAZJ0pzNztJfDUT6J78oZyOvNjavd Jp5h4C/RibqkvLl9bPNMYwIEyxT2DrnCMMcqTgpxq2FAZB4Gj+vnbvsrbKwE8ozLPvnAuepi8ro mU2a+fyJV2dSztpXXWuqTTD5+xJumZwUbWz1WR24zQGyFRR9RkO1k9yg5w== X-Google-Smtp-Source: AGHT+IHh6JwLYQePZBMujNRYI8A6XwD5WkfD3Ot/VtJsrqiS9T18sjhPkT+oNZek1pT+BypYrsY7PQ== X-Received: by 2002:a05:6000:18a3:b0:38a:a037:a517 with SMTP id ffacd0b85a97d-38dc8dd27f1mr2638562f8f.19.1738945249611; Fri, 07 Feb 2025 08:20:49 -0800 (PST) Received: from localhost (089144193052.atnat0002.highway.a1.net. [89.144.193.52]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dfd8448sm60238835e9.38.2025.02.07.08.20.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 08:20:49 -0800 (PST) From: Andrew Jones To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: paul.walmsley@sifive.com, palmer@dabbelt.com, charlie@rivosinc.com, jesse@rivosinc.com, Anup Patel Subject: [PATCH 9/9] riscv: Add Ventana unaligned access table entries Date: Fri, 7 Feb 2025 17:19:49 +0100 Message-ID: <20250207161939.46139-20-ajones@ventanamicro.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250207161939.46139-11-ajones@ventanamicro.com> References: <20250207161939.46139-11-ajones@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Ventana harts always have fast unaligned access speeds, so skip the unnecessary probing. Signed-off-by: Andrew Jones --- arch/riscv/include/asm/vendorid_list.h | 1 + arch/riscv/kernel/unaligned_access_speed.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/as= m/vendorid_list.h index a5150cdf34d8..8dd55a847893 100644 --- a/arch/riscv/include/asm/vendorid_list.h +++ b/arch/riscv/include/asm/vendorid_list.h @@ -9,5 +9,6 @@ #define MICROCHIP_VENDOR_ID 0x029 #define SIFIVE_VENDOR_ID 0x489 #define THEAD_VENDOR_ID 0x5b7 +#define VENTANA_VENDOR_ID 0x61f =20 #endif diff --git a/arch/riscv/kernel/unaligned_access_speed.c b/arch/riscv/kernel= /unaligned_access_speed.c index bd6db4c42daf..ff9905274c60 100644 --- a/arch/riscv/kernel/unaligned_access_speed.c +++ b/arch/riscv/kernel/unaligned_access_speed.c @@ -14,6 +14,7 @@ #include #include #include +#include =20 #include "copy-unaligned.h" =20 @@ -251,6 +252,7 @@ struct unaligned_access_table_entry { }; =20 static struct unaligned_access_table_entry unaligned_access_table_entries[= ] =3D { + { LEVEL_VENDOR, VENTANA_VENDOR_ID, 0, 0, RISCV_HWPROBE_MISALIGNED_SCALAR_= FAST }, }; =20 /* @@ -460,6 +462,7 @@ static int __init vec_check_unaligned_access_speed_all_= cpus(void *unused __alway #endif =20 static struct unaligned_access_table_entry vec_unaligned_access_table_entr= ies[] =3D { + { LEVEL_VENDOR, VENTANA_VENDOR_ID, 0, 0, RISCV_HWPROBE_MISALIGNED_VECTOR_= FAST }, }; =20 static bool check_vector_unaligned_access_table(void) --=20 2.48.1