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From: Dikshita Agarwal <quic_dikshita@quicinc.com>
Date: Fri, 7 Feb 2025 13:24:45 +0530
Subject: [PATCH v10 05/28] media: iris: implement video firmware
load/unload
Precedence: bulk
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Message-ID: <20250207-qcom-video-iris-v10-5-ab66eeffbd20@quicinc.com>
References: <20250207-qcom-video-iris-v10-0-ab66eeffbd20@quicinc.com>
In-Reply-To: <20250207-qcom-video-iris-v10-0-ab66eeffbd20@quicinc.com>
To: Vikash Garodia <quic_vgarodia@quicinc.com>,
Abhinav Kumar
<quic_abhinavk@quicinc.com>,
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CC: Hans Verkuil <hverkuil@xs4all.nl>,
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<sebastian.fricke@collabora.com>,
Bryan O'Donoghue
<bryan.odonoghue@linaro.org>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Nicolas Dufresne
<nicolas@ndufresne.ca>,
=?utf-8?q?Uwe_Kleine-K=C3=B6nig?=
<u.kleine-koenig@baylibre.com>,
Jianhua Lu <lujianhua000@gmail.com>,
"Stefan
Schmidt" <stefan.schmidt@linaro.org>,
Joel Stanley <joel@jms.id.au>, "Johan
Hovold" <johan@kernel.org>,
<linux-media@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Dikshita Agarwal <quic_dikshita@quicinc.com>
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Load/unload the firmware into/from memory via the MDT loader.
The firmware is loaded as part of core initialization and unloaded as
part of core de-initialization.
Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org> # x1e80100 (Dell XPS =
13 9345)
Reviewed-by: Stefan Schmidt <stefan.schmidt@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-HDK
Signed-off-by: Dikshita Agarwal <quic_dikshita@quicinc.com>
---
drivers/media/platform/qcom/iris/Kconfig | 2 +
drivers/media/platform/qcom/iris/Makefile | 1 +
drivers/media/platform/qcom/iris/iris_core.c | 8 ++
drivers/media/platform/qcom/iris/iris_firmware.c | 111 +++++++++++++++++=
++++
drivers/media/platform/qcom/iris/iris_firmware.h | 14 +++
.../platform/qcom/iris/iris_platform_common.h | 12 +++
.../platform/qcom/iris/iris_platform_sm8550.c | 10 ++
7 files changed, 158 insertions(+)
diff --git a/drivers/media/platform/qcom/iris/Kconfig b/drivers/media/platf=
orm/qcom/iris/Kconfig
index 8debddec87a5..f92cc7fe9378 100644
--- a/drivers/media/platform/qcom/iris/Kconfig
+++ b/drivers/media/platform/qcom/iris/Kconfig
@@ -3,6 +3,8 @@ config VIDEO_QCOM_IRIS
depends on VIDEO_DEV
depends on ARCH_QCOM || COMPILE_TEST
select V4L2_MEM2MEM_DEV
+ select QCOM_MDT_LOADER if ARCH_QCOM
+ select QCOM_SCM
help
This is a V4L2 driver for Qualcomm iris video accelerator
hardware. It accelerates decoding operations on various
diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat=
form/qcom/iris/Makefile
index 93711f108a77..6906caa2c481 100644
--- a/drivers/media/platform/qcom/iris/Makefile
+++ b/drivers/media/platform/qcom/iris/Makefile
@@ -1,4 +1,5 @@
iris-objs +=3D iris_core.o \
+ iris_firmware.o \
iris_hfi_gen1_command.o \
iris_hfi_gen2_command.o \
iris_hfi_queue.o \
diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/p=
latform/qcom/iris/iris_core.c
index 360a54909ef6..8c7d53c57086 100644
--- a/drivers/media/platform/qcom/iris/iris_core.c
+++ b/drivers/media/platform/qcom/iris/iris_core.c
@@ -4,11 +4,13 @@
*/
=20
#include "iris_core.h"
+#include "iris_firmware.h"
#include "iris_state.h"
=20
void iris_core_deinit(struct iris_core *core)
{
mutex_lock(&core->lock);
+ iris_fw_unload(core);
iris_hfi_queues_deinit(core);
core->state =3D IRIS_CORE_DEINIT;
mutex_unlock(&core->lock);
@@ -33,10 +35,16 @@ int iris_core_init(struct iris_core *core)
if (ret)
goto error;
=20
+ ret =3D iris_fw_load(core);
+ if (ret)
+ goto error_queue_deinit;
+
mutex_unlock(&core->lock);
=20
return 0;
=20
+error_queue_deinit:
+ iris_hfi_queues_deinit(core);
error:
core->state =3D IRIS_CORE_DEINIT;
exit:
diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med=
ia/platform/qcom/iris/iris_firmware.c
new file mode 100644
index 000000000000..3d14e596a471
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_firmware.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res=
erved.
+ */
+
+#include <linux/firmware.h>
+#include <linux/firmware/qcom/qcom_scm.h>
+#include <linux/of_address.h>
+#include <linux/of_reserved_mem.h>
+#include <linux/soc/qcom/mdt_loader.h>
+
+#include "iris_core.h"
+#include "iris_firmware.h"
+
+#define MAX_FIRMWARE_NAME_SIZE 128
+
+static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_n=
ame)
+{
+ u32 pas_id =3D core->iris_platform_data->pas_id;
+ const struct firmware *firmware =3D NULL;
+ struct device *dev =3D core->dev;
+ struct reserved_mem *rmem;
+ struct device_node *node;
+ phys_addr_t mem_phys;
+ size_t res_size;
+ ssize_t fw_size;
+ void *mem_virt;
+ int ret;
+
+ if (strlen(fw_name) >=3D MAX_FIRMWARE_NAME_SIZE - 4)
+ return -EINVAL;
+
+ node =3D of_parse_phandle(dev->of_node, "memory-region", 0);
+ if (!node)
+ return -EINVAL;
+
+ rmem =3D of_reserved_mem_lookup(node);
+ of_node_put(node);
+ if (!rmem)
+ return -EINVAL;
+
+ mem_phys =3D rmem->base;
+ res_size =3D rmem->size;
+
+ ret =3D request_firmware(&firmware, fw_name, dev);
+ if (ret)
+ return ret;
+
+ fw_size =3D qcom_mdt_get_size(firmware);
+ if (fw_size < 0 || res_size < (size_t)fw_size) {
+ ret =3D -EINVAL;
+ goto err_release_fw;
+ }
+
+ mem_virt =3D memremap(mem_phys, res_size, MEMREMAP_WC);
+ if (!mem_virt)
+ goto err_release_fw;
+
+ ret =3D qcom_mdt_load(dev, firmware, fw_name,
+ pas_id, mem_virt, mem_phys, res_size, NULL);
+ if (ret)
+ goto err_mem_unmap;
+
+ ret =3D qcom_scm_pas_auth_and_reset(pas_id);
+ if (ret)
+ goto err_mem_unmap;
+
+ return ret;
+
+err_mem_unmap:
+ memunmap(mem_virt);
+err_release_fw:
+ release_firmware(firmware);
+
+ return ret;
+}
+
+int iris_fw_load(struct iris_core *core)
+{
+ struct tz_cp_config *cp_config =3D core->iris_platform_data->tz_cp_config=
_data;
+ const char *fwpath =3D NULL;
+ int ret;
+
+ ret =3D of_property_read_string_index(core->dev->of_node, "firmware-name"=
, 0,
+ &fwpath);
+ if (ret)
+ fwpath =3D core->iris_platform_data->fwname;
+
+ ret =3D iris_load_fw_to_memory(core, fwpath);
+ if (ret) {
+ dev_err(core->dev, "firmware download failed\n");
+ return -ENOMEM;
+ }
+
+ ret =3D qcom_scm_mem_protect_video_var(cp_config->cp_start,
+ cp_config->cp_size,
+ cp_config->cp_nonpixel_start,
+ cp_config->cp_nonpixel_size);
+ if (ret) {
+ dev_err(core->dev, "protect memory failed\n");
+ qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
+ return ret;
+ }
+
+ return ret;
+}
+
+int iris_fw_unload(struct iris_core *core)
+{
+ return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id);
+}
diff --git a/drivers/media/platform/qcom/iris/iris_firmware.h b/drivers/med=
ia/platform/qcom/iris/iris_firmware.h
new file mode 100644
index 000000000000..266bdd92a124
--- /dev/null
+++ b/drivers/media/platform/qcom/iris/iris_firmware.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res=
erved.
+ */
+
+#ifndef __IRIS_FIRMWARE_H__
+#define __IRIS_FIRMWARE_H__
+
+struct iris_core;
+
+int iris_fw_load(struct iris_core *core);
+int iris_fw_unload(struct iris_core *core);
+
+#endif
diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv=
ers/media/platform/qcom/iris/iris_platform_common.h
index b4d63d6677c5..42c1fe8e4fa6 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_common.h
+++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
@@ -6,6 +6,8 @@
#ifndef __IRIS_PLATFORM_COMMON_H__
#define __IRIS_PLATFORM_COMMON_H__
=20
+#define IRIS_PAS_ID 9
+
extern struct iris_platform_data sm8550_data;
=20
enum platform_clk_type {
@@ -19,6 +21,13 @@ struct platform_clk_data {
const char *clk_name;
};
=20
+struct tz_cp_config {
+ u32 cp_start;
+ u32 cp_size;
+ u32 cp_nonpixel_start;
+ u32 cp_nonpixel_size;
+};
+
struct iris_platform_data {
struct iris_inst *(*get_instance)(void);
const struct icc_info *icc_tbl;
@@ -32,6 +41,9 @@ struct iris_platform_data {
const char * const *clk_rst_tbl;
unsigned int clk_rst_tbl_size;
u64 dma_mask;
+ const char *fwname;
+ u32 pas_id;
+ struct tz_cp_config *tz_cp_config_data;
};
=20
#endif
diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c b/driv=
ers/media/platform/qcom/iris/iris_platform_sm8550.c
index ddaa4991d645..bf389181d8cc 100644
--- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c
+++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c
@@ -24,6 +24,13 @@ static const struct platform_clk_data sm8550_clk_table[]=
=3D {
{IRIS_HW_CLK, "vcodec0_core" },
};
=20
+static struct tz_cp_config tz_cp_config_sm8550 =3D {
+ .cp_start =3D 0,
+ .cp_size =3D 0x25800000,
+ .cp_nonpixel_start =3D 0x01000000,
+ .cp_nonpixel_size =3D 0x24800000,
+};
+
struct iris_platform_data sm8550_data =3D {
.get_instance =3D iris_hfi_gen2_get_instance,
.icc_tbl =3D sm8550_icc_table,
@@ -38,4 +45,7 @@ struct iris_platform_data sm8550_data =3D {
.clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table),
/* Upper bound of DMA address range */
.dma_mask =3D 0xe0000000 - 1,
+ .fwname =3D "qcom/vpu/vpu30_p4.mbn",
+ .pas_id =3D IRIS_PAS_ID,
+ .tz_cp_config_data =3D &tz_cp_config_sm8550,
};
--=20
2.34.1