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Thu, 06 Feb 2025 15:29:24 -0800 (PST) X-Google-Smtp-Source: AGHT+IHVvvYMobydfHRdWhzMPIv8JZmHyxD+Mh3A0E5Fwkz+JeyDtuYL5YSOAi+LGBdODS/8LGwWcw== X-Received: by 2002:a05:6a21:7101:b0:1ed:e2bc:5c9 with SMTP id adf61e73a8af0-1ee03b71f2emr2036920637.38.1738884562752; Thu, 06 Feb 2025 15:29:22 -0800 (PST) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73048ae7f6esm1845905b3a.74.2025.02.06.15.29.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Feb 2025 15:29:22 -0800 (PST) From: Krishna Chaitanya Chundru Date: Fri, 07 Feb 2025 04:58:58 +0530 Subject: [PATCH v4 3/4] PCI: dwc: Reduce DT reads by allocating host bridge via DWC glue driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250207-ecam_v4-v4-3-94b5d5ec5017@oss.qualcomm.com> References: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> In-Reply-To: <20250207-ecam_v4-v4-0-94b5d5ec5017@oss.qualcomm.com> To: cros-qcom-dts-watchers@chromium.org, Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Jingoo Han Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, quic_vbadigan@quicinc.com, quic_mrana@quicinc.com, quic_vpernami@quicinc.com, mmareddy@quicinc.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738884540; l=1728; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=SWWzA0HUJcFMbO1HqY5NCoLambaGtXZLJb30DVpO5fc=; b=fZyiGh+iMPqdX/K4h9jdTW+5zikUfOPuZjl5KcMx85+JOe7+rbVN381UpyvurlnEV16UJ7VQd jDdcMRo+q70DPlgYt791jj0Frlgw0Nhyo/Av/N0hwH9New5yG8qcNw9 X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: nBOPrh0KNnNRatBx8yhEVPWKHpN73ZYB X-Proofpoint-ORIG-GUID: nBOPrh0KNnNRatBx8yhEVPWKHpN73ZYB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-06_07,2025-02-05_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=930 priorityscore=1501 bulkscore=0 clxscore=1015 spamscore=0 phishscore=0 impostorscore=0 lowpriorityscore=0 mlxscore=0 malwarescore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2501170000 definitions=main-2502060182 dw_pcie_ecam_supported() needs to read bus-range to find the maximum bus range value. The devm_pci_alloc_host_bridge() is already reading bus range and storing it in host bridge.If devm_pci_alloc_host_bridge() moved to start of the controller probe, the dt reading can be avoided and use values stored in the host bridge. Allow DWC glue drivers to allocate the host bridge, avoiding redundant device tree reads primarily in dw_pcie_ecam_supported(). Suggested-by: Bjorn Helgaas Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-designware-host.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index 826ff9338646..a18cb1e411e4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -484,8 +484,8 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) struct device *dev =3D pci->dev; struct device_node *np =3D dev->of_node; struct platform_device *pdev =3D to_platform_device(dev); + struct pci_host_bridge *bridge =3D pp->bridge; struct resource_entry *win; - struct pci_host_bridge *bridge; struct resource *res; int ret; =20 @@ -527,7 +527,12 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (!bridge) return -ENOMEM; =20 - pp->bridge =3D bridge; + if (!pp->bridge) { + bridge =3D devm_pci_alloc_host_bridge(dev, 0); + if (!bridge) + return -ENOMEM; + pp->bridge =3D bridge; + } =20 /* Get the I/O range from DT */ win =3D resource_list_first_type(&bridge->windows, IORESOURCE_IO); --=20 2.34.1