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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5fc544b08d4sm930387eaf.2.2025.02.07.12.09.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Feb 2025 12:09:43 -0800 (PST) From: David Lechner Date: Fri, 07 Feb 2025 14:09:07 -0600 Subject: [PATCH v8 10/17] iio: adc: ad7944: don't use storagebits for sizing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250207-dlech-mainline-spi-engine-offload-2-v8-10-e48a489be48c@baylibre.com> References: <20250207-dlech-mainline-spi-engine-offload-2-v8-0-e48a489be48c@baylibre.com> In-Reply-To: <20250207-dlech-mainline-spi-engine-offload-2-v8-0-e48a489be48c@baylibre.com> To: Mark Brown , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Nuno_S=C3=A1?= Cc: =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Michael Hennerich , Lars-Peter Clausen , David Jander , Martin Sperl , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, Jonathan Cameron , David Lechner X-Mailer: b4 0.14.2 Replace use of storagebits with realbits for determining the number of bytes needed for SPI transfers. When adding SPI offload support, storagebits will always be 32 rather than 16 for 16-bit 16-bit chips so we can no longer rely on storagebits being the correct size expected by the SPI framework (it always uses 4 bytes for > 16-bit xfers and 2 bytes for > 8-bit xfers). Instead, derive the correct size from realbits since it will always be correct even when SPI offloading is used. Reviewed-by: Jonathan Cameron Reviewed-vy: Nuno Sa Signed-off-by: David Lechner --- v7 changes: * Make commit message more specific about numbers. v6 changes: none v5 changes: none v4 changes: new patch in v4 --- drivers/iio/adc/ad7944.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/ad7944.c b/drivers/iio/adc/ad7944.c index 0ec9cda10f5f8f61727581b152fb921f2e0b4bff..abfababcea10152fe1faa8afc2e= c1ea2dc40ae52 100644 --- a/drivers/iio/adc/ad7944.c +++ b/drivers/iio/adc/ad7944.c @@ -98,6 +98,9 @@ struct ad7944_chip_info { const struct iio_chan_spec channels[2]; }; =20 +/* get number of bytes for SPI xfer */ +#define AD7944_SPI_BYTES(scan_type) ((scan_type).realbits > 16 ? 4 : 2) + /* * AD7944_DEFINE_CHIP_INFO - Define a chip info structure for a specific c= hip * @_name: The name of the chip @@ -164,7 +167,7 @@ static int ad7944_3wire_cs_mode_init_msg(struct device = *dev, struct ad7944_adc * =20 /* Then we can read the data during the acquisition phase */ xfers[2].rx_buf =3D &adc->sample.raw; - xfers[2].len =3D BITS_TO_BYTES(chan->scan_type.storagebits); + xfers[2].len =3D AD7944_SPI_BYTES(chan->scan_type); xfers[2].bits_per_word =3D chan->scan_type.realbits; =20 spi_message_init_with_transfers(&adc->msg, xfers, 3); @@ -193,7 +196,7 @@ static int ad7944_4wire_mode_init_msg(struct device *de= v, struct ad7944_adc *adc xfers[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; =20 xfers[1].rx_buf =3D &adc->sample.raw; - xfers[1].len =3D BITS_TO_BYTES(chan->scan_type.storagebits); + xfers[1].len =3D AD7944_SPI_BYTES(chan->scan_type); xfers[1].bits_per_word =3D chan->scan_type.realbits; =20 spi_message_init_with_transfers(&adc->msg, xfers, 2); @@ -228,7 +231,7 @@ static int ad7944_chain_mode_init_msg(struct device *de= v, struct ad7944_adc *adc xfers[0].delay.unit =3D SPI_DELAY_UNIT_NSECS; =20 xfers[1].rx_buf =3D adc->chain_mode_buf; - xfers[1].len =3D BITS_TO_BYTES(chan->scan_type.storagebits) * n_chain_dev; + xfers[1].len =3D AD7944_SPI_BYTES(chan->scan_type) * n_chain_dev; xfers[1].bits_per_word =3D chan->scan_type.realbits; =20 spi_message_init_with_transfers(&adc->msg, xfers, 2); @@ -274,12 +277,12 @@ static int ad7944_single_conversion(struct ad7944_adc= *adc, return ret; =20 if (adc->spi_mode =3D=3D AD7944_SPI_MODE_CHAIN) { - if (chan->scan_type.storagebits > 16) + if (chan->scan_type.realbits > 16) *val =3D ((u32 *)adc->chain_mode_buf)[chan->scan_index]; else *val =3D ((u16 *)adc->chain_mode_buf)[chan->scan_index]; } else { - if (chan->scan_type.storagebits > 16) + if (chan->scan_type.realbits > 16) *val =3D adc->sample.raw.u32; else *val =3D adc->sample.raw.u16; @@ -409,8 +412,7 @@ static int ad7944_chain_mode_alloc(struct device *dev, /* 1 word for each voltage channel + aligned u64 for timestamp */ =20 chain_mode_buf_size =3D ALIGN(n_chain_dev * - BITS_TO_BYTES(chan[0].scan_type.storagebits), sizeof(u64)) - + sizeof(u64); + AD7944_SPI_BYTES(chan[0].scan_type), sizeof(u64)) + sizeof(u64); buf =3D devm_kzalloc(dev, chain_mode_buf_size, GFP_KERNEL); if (!buf) return -ENOMEM; --=20 2.43.0