From nobody Tue Dec 16 02:33:32 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B38022654C; Thu, 6 Feb 2025 23:52:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738885931; cv=none; b=hCvWRiRdCqE0hvplE1/zEPbc5j9xC/lsiCqWkCM6dCFJ17Q+THmG7cP/L+E5TW/d+DzbDxlTIcQxLgmj+khqgxVQdcRRwJrNlBl8cHj31kYNU6X3Ht4uJc1KAgSCzX0d4Heu2K3wKwWPHqneBNSrhheOowLNapue+Uos0cr1y4c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738885931; c=relaxed/simple; bh=LV3I6aVFmaJSPAUOkS1Eis+/TZyRS8nAHgbQe8T+WjU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=h1bvDBtjATJzKj4iWsJAsriNZOgbY2GjhT2oWqkcKA1vqzSNXRz6OgDmViWgpkA8Jvwvl/RStrO/Xugr2sj8w1iUnJEZkIunS1os05k0jVPNEiiz+GXtlF0lMi8IiZgA7kVCIo1/PIoP/o7dZnG6UTJslwLf9yRwurxYw2KBST0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=eB0mmLx4; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="eB0mmLx4" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 516Nq05N2820121 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 6 Feb 2025 17:52:00 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1738885921; bh=2tK3lI0djpS/6LRZIvhHPLKSSVignyzxq9XZE0uHegg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=eB0mmLx4myPCt6EV7h+EwVfJDYTrLWdLrCY4eAKToOdW7DPGjssnphGPcVBfWwvZR Motxhb/jow0x8xwS+r5rk8ygU6ZeAhFaU4p+/22pU8N2VwqVC64Ymct6m67k/h67iz ElO3hiq4itKHEXIhugkZbwbO5cPJ5KhMZAjpvr3k= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 516Nq0lM018984 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 6 Feb 2025 17:52:00 -0600 Received: from DLEE108.ent.ti.com (157.170.170.38) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 6 Feb 2025 17:52:00 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 6 Feb 2025 17:52:00 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 516Nq0vC021560; Thu, 6 Feb 2025 17:52:00 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v4 1/9] arm64: dts: ti: k3-am62-wakeup: Add wakeup R5F node Date: Thu, 6 Feb 2025 17:51:51 -0600 Message-ID: <20250206235200.3128163-2-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250206235200.3128163-1-jm@ti.com> References: <20250206235200.3128163-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla AM62 SoC devices have a single core R5F processor in wakeup domain. The R5F processor in wakeup domain is used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v3: - No change --- arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 25 ++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/d= ts/ti/k3-am62-wakeup.dtsi index 9b8a1f85aa15c..061819a64300f 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi @@ -106,6 +106,31 @@ wkup_rti0: watchdog@2b000000 { status =3D "reserved"; }; =20 + wkup_r5fss0: r5fss@78000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains =3D <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names =3D "atcm", "btcm"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <121>; + ti,sci-proc-ids =3D <0x01 0xff>; + resets =3D <&k3_reset 121 1>; + firmware-name =3D "am62-wkup-r5f0_0-fw"; + ti,atcm-enable =3D <1>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <1>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible =3D "ti,j7200-vtm"; reg =3D <0x00 0xb00000 0x00 0x400>, --=20 2.48.0 From nobody Tue Dec 16 02:33:32 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 08447239574; Thu, 6 Feb 2025 23:52:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738885932; cv=none; b=jYyVR8bZ6DNgFAuKw5nx7qfT6ntRQJFCCOs2bHx+3uxWJtDPSMdcB9aSnwg1KGKt42v0MODiqLAF+bcyU3P+ls7EJbpUG2vecW3zdIt22cC2dfTfCJLax8bVqxszB3YEc34CrTCRdUKvMgJKVJjyRjApJq8fa5qC5J6Hofojdy4= ARC-Message-Signature: i=1; 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Thu, 6 Feb 2025 17:52:00 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 516Nq0vD021560; Thu, 6 Feb 2025 17:52:00 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v4 2/9] arm64: dts: ti: k3-am62a-mcu: Add R5F remote proc node Date: Thu, 6 Feb 2025 17:51:52 -0600 Message-ID: <20250206235200.3128163-3-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250206235200.3128163-1-jm@ti.com> References: <20250206235200.3128163-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla AM62A SoCs have a single R5F core in the MCU voltage domain. The MCU domain also has a 512KB sram memory, the R5F core can use for applications needing fast memory access. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v3: - No change --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62a-mcu.dtsi index 0469c766b769e..e9042c986e68a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -6,6 +6,18 @@ */ =20 &cbass_mcu { + mcu_ram: sram@79100000 { + compatible =3D "mmio-sram"; + reg =3D <0x00 0x79100000 0x00 0x80000>; + ranges =3D <0x00 0x00 0x79100000 0x80000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mcu1-sram@0 { + reg =3D <0x0 0x80000>; + }; + }; + mcu_pmx0: pinctrl@4084000 { compatible =3D "pinctrl-single"; reg =3D <0x00 0x04084000 0x00 0x88>; @@ -175,4 +187,30 @@ mcu_mcan1: can@4e18000 { bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; status =3D "disabled"; }; + + mcu_r5fss0: r5fss@79000000 { + compatible =3D "ti,am62-r5fss"; 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charset="utf-8" From: Devarsh Thakkar AM62A SoCs have a single R5F core in wakeup domain. This core is also used as a device manager for the SoC. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v3: - No change --- arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi | 25 +++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi b/arch/arm64/boot/= dts/ti/k3-am62a-wakeup.dtsi index b2c8f53517438..785b9f00033a4 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-wakeup.dtsi @@ -103,6 +103,31 @@ wkup_rti0: watchdog@2b000000 { status =3D "reserved"; }; =20 + wkup_r5fss0: r5fss@78000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x78000000 0x00 0x78000000 0x8000>, + <0x78100000 0x00 0x78100000 0x8000>; + power-domains =3D <&k3_pds 119 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + wkup_r5fss0_core0: r5f@78000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x78000000 0x00008000>, + <0x78100000 0x00008000>; + reg-names =3D "atcm", "btcm"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <121>; + ti,sci-proc-ids =3D <0x01 0xff>; + resets =3D <&k3_reset 121 1>; + firmware-name =3D "am62a-wkup-r5f0_0-fw"; + ti,atcm-enable =3D <1>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <1>; + }; + }; + wkup_vtm0: temperature-sensor@b00000 { compatible =3D "ti,j7200-vtm"; reg =3D <0x00 0xb00000 0x00 0x400>, --=20 2.48.0 From nobody Tue Dec 16 02:33:32 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B3EA229B20; Thu, 6 Feb 2025 23:52:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738885930; cv=none; b=HyLrBYiBvlyVTiNJu5OO8UT8joXnX/tjRgGIf0K/NdL3/RON1lmlWYFWBZsKmLVlzR8tnRnKJI1vHvqBTap4IuYlmAuO3mpANZexSN/nM/R3G9Sut17Sq6HrOuL/cT8zsV2KynLdzexvcEAN/8+8v4yxU1PyvJl30lASi3gS5XM= ARC-Message-Signature: i=1; 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Thu, 6 Feb 2025 17:52:00 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 516Nq0vF021560; Thu, 6 Feb 2025 17:52:00 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v4 4/9] arm64: dts: ti: k3-am62a-main: Add C7xv device node Date: Thu, 6 Feb 2025 17:51:54 -0600 Message-ID: <20250206235200.3128163-5-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250206235200.3128163-1-jm@ti.com> References: <20250206235200.3128163-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Jai Luthra AM62A SoCs have a C7xv DSP subsystem with Analytics engine capability. This subsystem is intended for deep learning purposes. Define the device node for C7xv DSP. Signed-off-by: Jai Luthra Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v3: - No change --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index a1daba7b1fad5..f6ebc4eabaf14 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -1123,6 +1123,18 @@ vpu: video-codec@30210000 { power-domains =3D <&k3_pds 204 TI_SCI_PD_EXCLUSIVE>; }; =20 + c7x_0: dsp@7e000000 { + compatible =3D "ti,am62a-c7xv-dsp"; + reg =3D <0x00 0x7e000000 0x00 0x00100000>; + reg-names =3D "l2sram"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <208>; + ti,sci-proc-ids =3D <0x04 0xff>; + resets =3D <&k3_reset 208 1>; + firmware-name =3D "am62a-c71_0-fw"; + status =3D "disabled"; + }; + e5010: jpeg-encoder@fd20000 { compatible =3D "ti,am62a-jpeg-enc", "img,e5010-jpeg-enc"; reg =3D <0x00 0xfd20000 0x00 0x100>, --=20 2.48.0 From nobody Tue Dec 16 02:33:32 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 049542417D3; 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charset="utf-8" From: Devarsh Thakkar For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v3: - No change --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 90 +++++++++++++++++++++++-- 1 file changed, 84 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index a6f0d87a50d8a..eaffbab093cc1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -49,6 +49,42 @@ linux,cma { linux,cma-default; }; =20 + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0x1e00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -60,12 +96,6 @@ secure_ddr: optee@9e800000 { alignment =3D <0x1000>; no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; =20 opp-table { @@ -737,3 +767,51 @@ dpi1_out: endpoint { }; }; }; + +&mailbox0_cluster0 { + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; 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charset="utf-8" From: Devarsh Thakkar For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v3: - Add SRAM child node for am62p MCU R5 core 0 --- .../dts/ti/k3-am62p-j722s-common-mcu.dtsi | 13 +++++ arch/arm64/boot/dts/ti/k3-am62p5-sk.dts | 50 ++++++++++++++++--- 2 files changed, 57 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi b/arch/a= rm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi index b33aff0d65c9d..0be3463bc21c5 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-mcu.dtsi @@ -6,6 +6,18 @@ */ =20 &cbass_mcu { + mcu_ram: sram@79100000 { + compatible =3D "mmio-sram"; + reg =3D <0x00 0x79100000 0x00 0x80000>; + ranges =3D <0x00 0x00 0x79100000 0x80000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mcu_sram1@0 { + reg =3D <0x0 0x80000>; + }; + }; + mcu_pmx0: pinctrl@4084000 { compatible =3D "pinctrl-single"; reg =3D <0x00 0x04084000 0x00 0x88>; @@ -213,6 +225,7 @@ mcu_r5fss0_core0: r5f@79000000 { ti,atcm-enable =3D <0>; ti,btcm-enable =3D <1>; ti,loczrama =3D <0>; + sram =3D <&mcu_ram>; }; }; }; diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62p5-sk.dts index ad71d2f27f538..9609727d042d3 100644 --- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts @@ -48,6 +48,30 @@ reserved-memory { #size-cells =3D <2>; ranges; =20 + mcu_r5fss0_core0_dma_memory_region: mcu-r5fss-dma-memory-region@9b800000= { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: mcu-r5fss-memory-region@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0x1e00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; no-map; @@ -57,12 +81,6 @@ secure_ddr: optee@9e800000 { reg =3D <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; =20 vmain_pd: regulator-0 { @@ -638,6 +656,26 @@ mbox_mcu_r5_0: mbox-mcu-r5-0 { }; }; =20 +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0 &mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster1 &mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + &main_uart0 { pinctrl-names =3D "default"; pinctrl-0 =3D <&main_uart0_pins_default>; --=20 2.48.0 From nobody Tue Dec 16 02:33:32 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1A6323909C; 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charset="utf-8" From: Hari Nagalla For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v3: - No change --- .../arm64/boot/dts/ti/k3-am62x-sk-common.dtsi | 32 ++++++++++++++++--- 1 file changed, 27 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi b/arch/arm64/bo= ot/dts/ti/k3-am62x-sk-common.dtsi index 2f129e8cd5b9f..9ea4de9303f51 100644 --- a/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62x-sk-common.dtsi @@ -68,6 +68,18 @@ mcu_m4fss_memory_region: m4f-memory@9cc00000 { no-map; }; =20 + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9da00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9da00000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-memory@9db00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9db00000 0x00 0xc00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -80,11 +92,6 @@ secure_ddr: optee@9e800000 { no-map; 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charset="utf-8" From: Hari Nagalla C7x DSP uses main_timer2, so mark it as reserved in linux DT. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v3: - No change --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index eaffbab093cc1..f03b06b7de51d 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -679,6 +679,11 @@ &main_uart1 { status =3D "reserved"; }; =20 +/* main_timer2 is used by C7x DSP */ +&main_timer2 { + status =3D "reserved"; +}; + &usbss0 { status =3D "okay"; ti,vbus-divider; --=20 2.48.0 From nobody Tue Dec 16 02:33:32 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1AAAB224B12; Thu, 6 Feb 2025 23:52:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738885930; cv=none; b=hnTM9Cp/lj7giEloPbImf4Bw9cHjS3TUN/+u5POTbco26LObUQntoA8ZCl/tdVwFPhIW3QQbEOCbaiz8eTRRI60pVciUdYUdHjPnNm7iW2adum24BgUO2I19MtYWVdVS2jHv2QK57wGu76E6UyL/OWuh0sW+HBzsb944vl0LH1Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738885930; c=relaxed/simple; bh=GsHIkMOuGCjJxEvY+F789o8gz9LbTW0OyAT6badSL28=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=K1ndzkAKUyhiQSlIK5votSq8GJtpUjdWRQeOYeVg/2iQ7tfEd5Q/jWLZ6fnY8RF7pvvQ02qLb8BdLhSaAIL8jBR7IFadu5ZPRPS6rKUVe1IL6nS20NdCFICa7ASjFvvwuxG5vJHPGp0K5ozhjYmR9Vphl/LDhmx9N29+LwkcVT4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=txwHdXJ4; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="txwHdXJ4" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 516Nq16u3642675 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 6 Feb 2025 17:52:01 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1738885921; bh=7qwbmdEpjuUvEJ9zZbBb6m11hhz/AufPH/BP4AJH1mM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=txwHdXJ44a8ebYQb2t67D2TCQUhvHeHIhJp5K6EbnRMJNbBh+DjQRNPnAH0Uzlx38 dF+BlkQx/ZmRcFyMb8h8VfAj4N9WOtqLhjLmYLVCKKrXrZpgbZFBDCG3Z5uT42Dv7e 4us7Q5o9yvJYAyQwXFuplbZ2VcVcAIfx1eoE2/jI= Received: from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 516Nq1ml026291 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 6 Feb 2025 17:52:01 -0600 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 6 Feb 2025 17:52:00 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 6 Feb 2025 17:52:00 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 516Nq0vK021560; Thu, 6 Feb 2025 17:52:00 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla , Judith Mendez Subject: [PATCH v4 9/9] arm64: dts: ti: k3-am62a7-sk: Reserve main_rti4 for C7x DSP Date: Thu, 6 Feb 2025 17:51:59 -0600 Message-ID: <20250206235200.3128163-10-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250206235200.3128163-1-jm@ti.com> References: <20250206235200.3128163-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla The main rti4 watchdog timer is used by the C7x DSP, so reserve the timer in the linux device tree. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v3: - No change --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index f03b06b7de51d..ffa437873f6d1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -820,3 +820,8 @@ &c7x_0 { <&c7x_0_memory_region>; status =3D "okay"; }; + +/* main_rti4 is used by C7x DSP */ +&main_rti4 { + status =3D "reserved"; +}; --=20 2.48.0