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Thu, 06 Feb 2025 05:19:51 -0800 (PST) From: Rui Qi X-Google-Original-From: Rui Qi To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, ardb@kernel.org, haibo1.xu@intel.com, guohanjun@huawei.com, sunilvl@ventanamicro.com, samuel.holland@sifive.com, parri.andrea@gmail.com, ericchancf@google.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Rui Qi Subject: [RFC 1/5] riscv: select HAVE_ACPI_APEI Date: Thu, 6 Feb 2025 21:19:22 +0800 Message-Id: <20250206131926.91289-2-qirui.001@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250206131926.91289-1-qirui.001@bytedance.com> References: <20250206131926.91289-1-qirui.001@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rui Qi The current riscv architecture code can already support GHES, GHES depends on HAVE_ACPI_APEI, so enable it Signed-off-by: Rui Qi --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 7612c52e9b1e..df01fe8cc24a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -120,6 +120,7 @@ config RISCV select HARDIRQS_SW_RESEND select HAS_IOPORT if MMU select HAVE_ALIGNED_STRUCT_PAGE + select HAVE_ACPI_APEI if ACPI select HAVE_ARCH_AUDITSYSCALL select HAVE_ARCH_HUGE_VMALLOC if HAVE_ARCH_HUGE_VMAP select HAVE_ARCH_HUGE_VMAP if MMU && 64BIT --=20 2.20.1 From nobody Mon Feb 9 00:27:20 2026 Received: from mail-pl1-f178.google.com (mail-pl1-f178.google.com [209.85.214.178]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38DBF226884 for ; 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charset="utf-8" From: Rui Qi Add support for riscv Common Platform Error Record (CPER). Signed-off-by: Rui Qi --- drivers/firmware/efi/cper.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index b69e68ef3f02..50f84a0f2801 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -110,6 +110,7 @@ static const char * const proc_type_strs[] =3D { "IA32/X64", "IA64", "ARM", + "RISCV", }; =20 static const char * const proc_isa_strs[] =3D { @@ -118,6 +119,9 @@ static const char * const proc_isa_strs[] =3D { "X64", "ARM A32/T32", "ARM A64", + "RISCV32", + "RISCV64", + }; =20 const char * const cper_proc_error_type_strs[] =3D { --=20 2.20.1 From nobody Mon Feb 9 00:27:20 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 996DC2451D0 for ; Thu, 6 Feb 2025 13:20:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" From: Rui Qi GHES error handling requires fixmap entries for IRQ notifications. Add fixmap index for it. Signed-off-by: Rui Qi --- arch/riscv/include/asm/fixmap.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/riscv/include/asm/fixmap.h b/arch/riscv/include/asm/fixma= p.h index 0a55099bb734..bca75c0e66a1 100644 --- a/arch/riscv/include/asm/fixmap.h +++ b/arch/riscv/include/asm/fixmap.h @@ -36,6 +36,9 @@ enum fixed_addresses { FIX_P4D, FIX_TEXT_POKE1, FIX_TEXT_POKE0, +#ifdef CONFIG_ACPI_APEI_GHES + FIX_APEI_GHES_IRQ, +#endif FIX_EARLYCON_MEM_BASE, =20 __end_of_permanent_fixed_addresses, --=20 2.20.1 From nobody Mon Feb 9 00:27:20 2026 Received: from mail-pl1-f182.google.com (mail-pl1-f182.google.com [209.85.214.182]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA0EA24634C for ; Thu, 6 Feb 2025 13:20:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.182 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" From: Rui Qi we need arch_apei_get_mem_attribute to get protection bits for a given physical address. These protection bits are then used to map the physical address. Signed-off-by: Rui Qi --- arch/riscv/include/asm/acpi.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6e13695120bc..c35dd4e5a84d 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -90,6 +90,24 @@ static inline void acpi_get_cbo_block_size(struct acpi_t= able_header *table, =20 #endif /* CONFIG_ACPI */ =20 +#ifdef CONFIG_ACPI_APEI +/* + * acpi_disable_cmcff is used in drivers/acpi/apei/hest.c for disabling + * IA-32 Architecture Corrected Machine Check (CMC) Firmware-First mode + * with a kernel command line parameter "acpi=3Dnocmcoff". But we don't + * have this IA-32 specific feature on RISC-V, this definition is only + * for compatibility. + */ +#define acpi_disable_cmcff 1 +static inline pgprot_t arch_apei_get_mem_attribute(phys_addr_t addr) +{ + return PAGE_KERNEL_IO; +} + +#else +#define acpi_disable_cmcff 0 +#endif + #ifdef CONFIG_ACPI_NUMA void acpi_map_cpus_to_nodes(void); #else --=20 2.20.1 From nobody Mon Feb 9 00:27:20 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0A978248184 for ; Thu, 6 Feb 2025 13:20:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738848028; cv=none; b=ObEdMo2b+8Aterud9Hm9zJUOTpTAzFPa33OwTORETk9rfRg5f459pQqbcjcjCVPMp2JGiIAzLUGw8WEyqLur8BpYYk2Q5HPMTBL0jK9fzk6f2hUNyN2V1CYhaFL5AOQRgEQgFrWkCvYgVCT8fSOjwlElFzGmpGbvbUfq3RSTh6A= ARC-Message-Signature: i=1; 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Thu, 06 Feb 2025 05:20:25 -0800 (PST) Received: from L4CR4519N7.bytedance.net ([203.208.189.11]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-21f3683d987sm12170775ad.120.2025.02.06.05.20.20 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 06 Feb 2025 05:20:25 -0800 (PST) From: Rui Qi X-Google-Original-From: Rui Qi To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, ardb@kernel.org, haibo1.xu@intel.com, guohanjun@huawei.com, sunilvl@ventanamicro.com, samuel.holland@sifive.com, parri.andrea@gmail.com, ericchancf@google.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-efi@vger.kernel.org, Rui Qi Subject: [RFC 5/5] RISC-V: define ioremap_cache Date: Thu, 6 Feb 2025 21:19:26 +0800 Message-Id: <20250206131926.91289-6-qirui.001@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250206131926.91289-1-qirui.001@bytedance.com> References: <20250206131926.91289-1-qirui.001@bytedance.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Rui Qi Define ioremap_cache for riscv, otherwise it will cause compile errors for bert.c and einj.c Signed-off-by: Rui Qi --- arch/riscv/include/asm/io.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index 1c5c641075d2..c81d2de007bc 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -134,6 +134,11 @@ __io_writes_outs(outs, u64, q, __io_pbr(), __io_paw()) #endif =20 #include +#define ioremap_cache ioremap_cache +static inline void __iomem *ioremap_cache(phys_addr_t addr, size_t size) +{ + return (__force void *)ioremap_prot(addr, size, _PAGE_KERNEL); +} =20 #ifdef CONFIG_MMU #define arch_memremap_wb(addr, size) \ --=20 2.20.1