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(unknown []) by gzga-smtp-mtada-g1-0 (Coremail) with SMTP id _____wD3fyNsWqRnb3bDKQ--.52146S4; Thu, 06 Feb 2025 14:45:06 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, krzk+dt@kernel.org, devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, derek.foreman@collabora.com, detlev.casanova@collabora.com, daniel@fooishbar.org, robh@kernel.org, sebastian.reichel@collabora.com, Andy Yan Subject: [PATCH v13 02/13] drm/rockchip: vop2: Rename TRANSFORM_OFFSET to TRANSFORM_OFFS Date: Thu, 6 Feb 2025 14:44:30 +0800 Message-ID: <20250206064457.11396-3-andyshrk@163.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250206064457.11396-1-andyshrk@163.com> References: <20250206064457.11396-1-andyshrk@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: _____wD3fyNsWqRnb3bDKQ--.52146S4 X-Coremail-Antispam: 1Uf129KBjvJXoWxCrWxKw4rJw15Jr18uw17Wrg_yoWrCr18pr W3JayDWF4UKFs2gFWkAr15AF48Xan2y3yfGa9xJrnIqFyaga4DWwnFka4UJr4Uta4I9FZ2 q3saqrW7urW3tr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jYtC7UUUUU= X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiqRnrXmekUdSnkAAAs0 Content-Type: text/plain; charset="utf-8" From: Andy Yan This help avoid "exceeds 100 columns" warning from checkpatch Signed-off-by: Andy Yan --- (no changes since v1) drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 ++++---- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 4 ++-- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.c index 03248ac4ba4a..5ee8a7b86d0b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1517,7 +1517,7 @@ static void vop2_plane_atomic_update(struct drm_plane= *plane, transform_offset =3D vop2_afbc_transform_offset(pstate, half_block_en); vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); - vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset); + vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFS, transform_offset); vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1= )); vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 1= 6))); vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride); @@ -1528,7 +1528,7 @@ static void vop2_plane_atomic_update(struct drm_plane= *plane, } else { if (vop2_cluster_window(win)) { vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 0); - vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, 0); + vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFS, 0); } =20 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4)); @@ -3420,7 +3420,7 @@ static const struct reg_field vop2_cluster_regs[VOP2_= WIN_MAX_REG] =3D { [VOP2_WIN_AFBC_TILE_NUM] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH= , 16, 31), [VOP2_WIN_AFBC_PIC_OFFSET] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFF= SET, 0, 31), [VOP2_WIN_AFBC_DSP_OFFSET] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFF= SET, 0, 31), - [VOP2_WIN_AFBC_TRANSFORM_OFFSET] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_T= RANSFORM_OFFSET, 0, 31), + [VOP2_WIN_AFBC_TRANSFORM_OFFS] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRA= NSFORM_OFFS, 0, 31), [VOP2_WIN_AFBC_ROTATE_90] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_M= ODE, 0, 0), [VOP2_WIN_AFBC_ROTATE_270] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_= MODE, 1, 1), [VOP2_WIN_XMIRROR] =3D REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2,= 2), @@ -3519,7 +3519,7 @@ static const struct reg_field vop2_esmart_regs[VOP2_W= IN_MAX_REG] =3D { [VOP2_WIN_AFBC_PIC_OFFSET] =3D { .reg =3D 0xffffffff }, [VOP2_WIN_AFBC_PIC_SIZE] =3D { .reg =3D 0xffffffff }, [VOP2_WIN_AFBC_DSP_OFFSET] =3D { .reg =3D 0xffffffff }, - [VOP2_WIN_AFBC_TRANSFORM_OFFSET] =3D { .reg =3D 0xffffffff }, + [VOP2_WIN_AFBC_TRANSFORM_OFFS] =3D { .reg =3D 0xffffffff }, [VOP2_WIN_AFBC_HDR_PTR] =3D { .reg =3D 0xffffffff }, [VOP2_WIN_AFBC_HALF_BLOCK_EN] =3D { .reg =3D 0xffffffff }, [VOP2_WIN_AFBC_ROTATE_270] =3D { .reg =3D 0xffffffff }, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm= /rockchip/rockchip_drm_vop2.h index 29cc7fb8f6d8..8510140b0869 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -118,7 +118,7 @@ enum vop2_win_regs { VOP2_WIN_AFBC_PIC_OFFSET, VOP2_WIN_AFBC_PIC_SIZE, VOP2_WIN_AFBC_DSP_OFFSET, - VOP2_WIN_AFBC_TRANSFORM_OFFSET, + VOP2_WIN_AFBC_TRANSFORM_OFFS, VOP2_WIN_AFBC_HDR_PTR, VOP2_WIN_AFBC_HALF_BLOCK_EN, VOP2_WIN_AFBC_ROTATE_270, @@ -335,7 +335,7 @@ enum dst_factor_mode { #define RK3568_CLUSTER_WIN_DSP_INFO 0x24 #define RK3568_CLUSTER_WIN_DSP_ST 0x28 #define RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB 0x30 -#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET 0x3C +#define RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFS 0x3C #define RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL 0x50 #define RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE 0x54 #define RK3568_CLUSTER_WIN_AFBCD_HDR_PTR 0x58 --=20 2.34.1