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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Feb 2025 13:37:41.8207 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f9aaaee9-2829-4150-c608-08dd45ea43cf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B36D.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9418 Content-Type: text/plain; charset="utf-8" The AMD QSPI controller supports an advanced connection modes called Stacked mode which allow the controller to treat two different flashes as one storage. In Stacked connection mode flashes share the same SPI bus, but different CS line, controller driver asserts the CS of the flash to which it needs to communicate. Stacked mode is a software abstraction rather than a controller feature or capability. At any given time, the controller communicates with one of the two connected flash devices, as determined by the requested address and data length. If an operation starts on one flash and ends on the other, the mtd layer needs to split it into two separate operations and adjust the data length accordingly. For more information on the modes please feel free to go through the controller flash interface below [1]. Introduce new DT property to specify which partitions are concatenated to each other. flash@0 { reg =3D <0>; partitions { compatible =3D "fixed-partitions"; part-concat =3D <&flash0_part1>, <&flash1_part0>; flash0_part0: part0@0 { label =3D "part0_0"; reg =3D <0x0 0x800000>; }; flash0_part1: part1@800000 { label =3D "part0_1"; reg =3D <0x800000 0x800000>; }; }; }; flash@1 { reg =3D <1>; partitions { compatible =3D "fixed-partitions"; flash1_part0: part1@0 { label =3D "part1_0"; reg =3D <0x0 0x800000>; }; flash1_part1: part1@800000 { label =3D "part1_1"; reg =3D <0x800000 0x800000>; }; }; }; The partitions that gets created are part0_0 part1_1 part0_1-part1_0-concat [1] https://docs.amd.com/r/en-US/am011-versal-acap-trm/QSPI-Flash-Device-In= terface Suggested-by: Miquel Raynal Signed-off-by: Amit Kumar Mahapatra --- .../bindings/mtd/partitions/partition.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/mtd/partitions/partition.yam= l b/Documentation/devicetree/bindings/mtd/partitions/partition.yaml index 80d0452a2a33..f77fef368211 100644 --- a/Documentation/devicetree/bindings/mtd/partitions/partition.yaml +++ b/Documentation/devicetree/bindings/mtd/partitions/partition.yaml @@ -57,6 +57,12 @@ properties: user space from type: boolean =20 + part-concat: + description: List of MTD partitions phandles that should be concatenat= ed. + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 2 + maxItems: 16 + align: $ref: /schemas/types.yaml#/definitions/uint32 minimum: 2 @@ -125,6 +131,7 @@ examples: compatible =3D "fixed-partitions"; #address-cells =3D <1>; #size-cells =3D <1>; + part-concat =3D <&part0>, <&part1>; =20 partition@100000 { compatible =3D "u-boot"; @@ -138,4 +145,14 @@ examples: reg =3D <0x200000 0x100000>; align =3D <0x4000>; }; + + part0: partition@400000 { + label =3D "part0_0"; + reg =3D <0x400000 0x100000>; + }; + + part1: partition@800000 { + label =3D "part0_1"; + reg =3D <0x800000 0x800000>; + }; }; --=20 2.34.1