From nobody Wed Feb 5 19:08:39 2025 Received: from shelob.surriel.com (shelob.surriel.com [96.67.55.147]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F48F213220 for ; Wed, 5 Feb 2025 01:41:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=96.67.55.147 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738719662; cv=none; b=sxSQK1vNI9BN/YAw/7+V3LjMYZVwl72CMmilC2RHEsqtNVaLTbdnolbUzk4XlvUVC6jkWW8FZ6Skm8JPW2P/PJ/5Q9bTEmgBvYnpzkxgbbRvXMV+hqCQ0nSZHqpGon4Gl4pX2aRcNxzy4nFYN6xFReCrgg+uN5x6MngsAvvwDC4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738719662; c=relaxed/simple; bh=AY3XDvm39GFsGN4Au2lRefxGo/K41JWz9nL19FtfpPQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=q+7slTvx2L3jqPUy29oXAF/jOj3VdE9GZ7lfnQSR2YqMlvwbcEVjJwJjMs3OQFHJ6cE/lKUYYQdEujt09rlRuaTdrNz4R0WD7Oxmoav7lXOwmr7LUlr67/AMHxUzS/ARP2oro/Lnf8TbKvuTQnVKdEr8nTHsDbk40WeOuPd7Dvk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com; spf=pass smtp.mailfrom=shelob.surriel.com; arc=none smtp.client-ip=96.67.55.147 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=surriel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=shelob.surriel.com Received: from fangorn.home.surriel.com ([10.0.13.7]) by shelob.surriel.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.97.1) (envelope-from ) id 1tfUP4-000000004Cs-2eJa; Tue, 04 Feb 2025 20:40:34 -0500 From: Rik van Riel To: x86@kernel.org Cc: linux-kernel@vger.kernel.org, bp@alien8.de, peterz@infradead.org, dave.hansen@linux.intel.com, zhengqi.arch@bytedance.com, nadav.amit@gmail.com, thomas.lendacky@amd.com, kernel-team@meta.com, linux-mm@kvack.org, akpm@linux-foundation.org, jannh@google.com, mhklinux@outlook.com, andrew.cooper3@citrix.com, Rik van Riel , Dave Hansen Subject: [PATCH v8 03/12] x86/mm: consolidate full flush threshold decision Date: Tue, 4 Feb 2025 20:39:52 -0500 Message-ID: <20250205014033.3626204-4-riel@surriel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250205014033.3626204-1-riel@surriel.com> References: <20250205014033.3626204-1-riel@surriel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Sender: riel@surriel.com Content-Type: text/plain; charset="utf-8" Reduce code duplication by consolidating the decision point for whether to do individual invalidations or a full flush inside get_flush_tlb_info. Signed-off-by: Rik van Riel Suggested-by: Dave Hansen --- arch/x86/mm/tlb.c | 52 ++++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 25 deletions(-) diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c index 6cf881a942bb..02e1f5c5bca3 100644 --- a/arch/x86/mm/tlb.c +++ b/arch/x86/mm/tlb.c @@ -1000,8 +1000,13 @@ static struct flush_tlb_info *get_flush_tlb_info(str= uct mm_struct *mm, BUG_ON(this_cpu_inc_return(flush_tlb_info_idx) !=3D 1); #endif =20 - info->start =3D start; - info->end =3D end; + /* + * Round the start and end addresses to the page size specified + * by the stride shift. This ensures partial pages at the end of + * a range get fully invalidated. + */ + info->start =3D round_down(start, 1 << stride_shift); + info->end =3D round_up(end, 1 << stride_shift); info->mm =3D mm; info->stride_shift =3D stride_shift; info->freed_tables =3D freed_tables; @@ -1009,6 +1014,15 @@ static struct flush_tlb_info *get_flush_tlb_info(str= uct mm_struct *mm, info->initiating_cpu =3D smp_processor_id(); info->trim_cpumask =3D 0; =20 + /* + * If the number of flushes is so large that a full flush + * would be faster, do a full flush. + */ + if ((end - start) >> stride_shift > tlb_single_page_flush_ceiling) { + info->start =3D 0; + info->end =3D TLB_FLUSH_ALL; + } + return info; } =20 @@ -1026,17 +1040,8 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsign= ed long start, bool freed_tables) { struct flush_tlb_info *info; + int cpu =3D get_cpu(); u64 new_tlb_gen; - int cpu; - - cpu =3D get_cpu(); - - /* Should we flush just the requested range? */ - if ((end =3D=3D TLB_FLUSH_ALL) || - ((end - start) >> stride_shift) > tlb_single_page_flush_ceiling) { - start =3D 0; - end =3D TLB_FLUSH_ALL; - } =20 /* This is also a barrier that synchronizes with switch_mm(). */ new_tlb_gen =3D inc_mm_tlb_gen(mm); @@ -1089,22 +1094,19 @@ static void do_kernel_range_flush(void *info) =20 void flush_tlb_kernel_range(unsigned long start, unsigned long end) { - /* Balance as user space task's flush, a bit conservative */ - if (end =3D=3D TLB_FLUSH_ALL || - (end - start) > tlb_single_page_flush_ceiling << PAGE_SHIFT) { - on_each_cpu(do_flush_tlb_all, NULL, 1); - } else { - struct flush_tlb_info *info; + struct flush_tlb_info *info; =20 - preempt_disable(); - info =3D get_flush_tlb_info(NULL, start, end, 0, false, - TLB_GENERATION_INVALID); + guard(preempt)(); + + info =3D get_flush_tlb_info(NULL, start, end, PAGE_SHIFT, false, + TLB_GENERATION_INVALID); =20 + if (info->end =3D=3D TLB_FLUSH_ALL) + on_each_cpu(do_flush_tlb_all, NULL, 1); + else on_each_cpu(do_kernel_range_flush, info, 1); =20 - put_flush_tlb_info(); - preempt_enable(); - } + put_flush_tlb_info(); } =20 /* @@ -1276,7 +1278,7 @@ void arch_tlbbatch_flush(struct arch_tlbflush_unmap_b= atch *batch) =20 int cpu =3D get_cpu(); =20 - info =3D get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, 0, false, + info =3D get_flush_tlb_info(NULL, 0, TLB_FLUSH_ALL, PAGE_SHIFT, false, TLB_GENERATION_INVALID); /* * flush_tlb_multi() is not optimized for the common case in which only --=20 2.47.1