From nobody Thu Feb 12 21:25:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A6EB1993B2; Wed, 5 Feb 2025 16:08:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738771699; cv=none; b=JWCV4If8zG4vo6IHw42GyuqbQDmGhlE+x68DBBaDGGwvaDx7HnsLqICxdZMK6dQzTgcfG3Sp0+GLDJrm0wladPl3ezdQ6O0J9szlSRRd4HhPWft+ujjswRccXaZZlE7uE+OUHgSiFXkt7I8I+ohsXm8hyPxisv0kiqQdEXGYYkg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738771699; c=relaxed/simple; bh=5QR3iPATmuktdgNOBba8w7ssdWLJhWF/6VGlhDvPsj0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kyoKmRiUxGRCBOr/Xyp5VY/1JTeY3E+BW4XtJCbI7LdKjzQ3UadWO0pe/9cejumc+kN7JtlxWu3dNbDTswDMpZAnWfKCMdlG3NY52vtw2THBG0LANrUal1QoGmaaYvPwQfpHhpya6gDcjrQVhyKYIRD27YhDAERPcOttb/c/M8A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aLvIaPvw; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aLvIaPvw" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 90D1AC4CED6; Wed, 5 Feb 2025 16:08:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738771697; bh=5QR3iPATmuktdgNOBba8w7ssdWLJhWF/6VGlhDvPsj0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aLvIaPvweNguBRtxG2PVkZ93J3+oygkCNsj/duA3DBRj/3r2ajL31uQLqfZQHuP+b YYyzZTL9SBDDtm4zOphBLeg7YAz8V5GPFcNrKbKyRwZsoNnCNbDTgQBqu3YawlyA7+ 0ddiBpKLAUtLgIcQM77dRn3qbH8FScv49+C+M0+Pg/0K5kkXKZrgcmFx2Wv0QKpJ+Y 2NjkMJwizwQfwQ/wg3IP2Ys1rVUjw7XHdF8+QhuwtHP+HLto0YyKutdKTfcanQwo0X jXh/D7gnUDnUZmqCHH182HqQyowp4eMAznElUf7PAUaJANnM4iwTerkGQ5Mgn2fGoD wKBNWd/d8QUMg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Eric Biggers , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/6] RISC-V: add vector extension validation checks Date: Wed, 5 Feb 2025 16:05:07 +0000 Message-ID: <20250205-defensive-lent-04936dac6bdd@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250205-cobbler-unpadded-5580c1f5d946@spud> References: <20250205-cobbler-unpadded-5580c1f5d946@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5885; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=Xll3sNeiVHrSCgmDC5jcXvVZqlI6Wuid0Q1Ycn1USfY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOmLe6wf/TdRP7vNJMmXT6dC2U9Ca9K/CUGtD/9uEZ0fU qG9t8mpo5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABPp5mNkmN8l8++9kVgNW5+x xXQV4fj9/jWyK+cs17qz79YXs//f1jH8d/znt+z6nQdVOvK7p/nw71p3pGb2X92ijwf6os6wRK0 x4gUA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Using Clement's new validation callbacks, support checking that dependencies have been satisfied for the vector extensions. From the kernel's perfective, it's not required to differentiate between the conditions for all the various vector subsets - it's the firmware's job to not report impossible combinations. Instead, the kernel only has to check that the correct config options are enabled and to enforce its requirement of the d extension being present for FPU support. Since vector will now be disabled proactively, there's no need to clear the bit in elf_hwcap in riscv_fill_hwcap() any longer. Signed-off-by: Conor Dooley --- arch/riscv/include/asm/cpufeature.h | 3 ++ arch/riscv/kernel/cpufeature.c | 57 +++++++++++++++++++---------- 2 files changed, 40 insertions(+), 20 deletions(-) diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/c= pufeature.h index 569140d6e639..5d9427ccbc7a 100644 --- a/arch/riscv/include/asm/cpufeature.h +++ b/arch/riscv/include/asm/cpufeature.h @@ -56,6 +56,9 @@ void __init riscv_user_isa_enable(void); #define __RISCV_ISA_EXT_BUNDLE(_name, _bundled_exts) \ _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ ARRAY_SIZE(_bundled_exts), NULL) +#define __RISCV_ISA_EXT_BUNDLE_VALIDATE(_name, _bundled_exts, _validate) \ + _RISCV_ISA_EXT_DATA(_name, RISCV_ISA_EXT_INVALID, _bundled_exts, \ + ARRAY_SIZE(_bundled_exts), _validate) =20 /* Used to declare extensions that are a superset of other extensions (Zvb= b for instance) */ #define __RISCV_ISA_EXT_SUPERSET(_name, _id, _sub_exts) \ diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c6ba750536c3..40a24b08d905 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -109,6 +109,35 @@ static int riscv_ext_zicboz_validate(const struct risc= v_isa_ext_data *data, return 0; } =20 +static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *da= ta, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + return -EINVAL; + + return 0; +} + +static int riscv_ext_vector_float_validate(const struct riscv_isa_ext_data= *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + return -EINVAL; + + if (!IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + /* + * The kernel doesn't support systems that don't implement both of + * F and D, so if any of the vector extensions that do floating point + * are to be usable, both floating point extensions need to be usable. + */ + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) + return -EINVAL; + + return 0; +} + static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { @@ -326,12 +355,10 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), - __RISCV_ISA_EXT_SUPERSET(v, RISCV_ISA_EXT_v, riscv_v_exts), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv= _ext_vector_float_validate), __RISCV_ISA_EXT_DATA(h, RISCV_ISA_EXT_h), - __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, - riscv_ext_zicbom_validate), - __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, - riscv_ext_zicboz_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicbom, RISCV_ISA_EXT_ZICBOM, riscv_xli= nuxenvcfg_exts, riscv_ext_zicbom_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zicboz, RISCV_ISA_EXT_ZICBOZ, riscv_xli= nuxenvcfg_exts, riscv_ext_zicboz_validate), __RISCV_ISA_EXT_DATA(ziccrse, RISCV_ISA_EXT_ZICCRSE), __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR), __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND), @@ -372,11 +399,11 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), - __RISCV_ISA_EXT_SUPERSET(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve32f_exts), - __RISCV_ISA_EXT_DATA(zve32x, RISCV_ISA_EXT_ZVE32X), - __RISCV_ISA_EXT_SUPERSET(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve64d_exts), - __RISCV_ISA_EXT_SUPERSET(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve64f_exts), - __RISCV_ISA_EXT_SUPERSET(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve64x_exts), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve= 32f_exts, riscv_ext_vector_float_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zve32x, RISCV_ISA_EXT_ZVE32X, riscv_ext_vec= tor_x_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve= 64d_exts, riscv_ext_vector_float_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64f, RISCV_ISA_EXT_ZVE64F, riscv_zve= 64f_exts, riscv_ext_vector_float_validate), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve= 64x_exts, riscv_ext_vector_x_validate), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), @@ -960,16 +987,6 @@ void __init riscv_fill_hwcap(void) riscv_v_setup_vsize(); } =20 - if (elf_hwcap & COMPAT_HWCAP_ISA_V) { - /* - * ISA string in device tree might have 'v' flag, but - * CONFIG_RISCV_ISA_V is disabled in kernel. - * Clear V flag in elf_hwcap if CONFIG_RISCV_ISA_V is disabled. - */ - if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) - elf_hwcap &=3D ~COMPAT_HWCAP_ISA_V; - } - memset(print_str, 0, sizeof(print_str)); for (i =3D 0, j =3D 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) --=20 2.45.2 From nobody Thu Feb 12 21:25:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74E441D86F7; Wed, 5 Feb 2025 16:08:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738771700; cv=none; b=ZtyA9XJJzlAYPQ39d8MXnc/92gfKexFLsHvRoION5tNzm9P0GeCgtp4OeySw5HMx8xjL7ywE3cyPK5y6veL0yJn95EDrGncJexh9MrPHF4Vk9tNpYWEiKWe8jXFUuWwWXkqfXtU9mJKlNHFbtLdXjqsCF1HnzSIPr8wg3OBN+7U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738771700; c=relaxed/simple; bh=qJFZa1EKck3rTDkEkJN+mxWME2YNA+lKI4hydp08qho=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FXdamjTVaYEva1/TjZUC74ktPgIPRwPZ1hHF5dVAm/Gnvp7F0Dfaxh2qJUJwCXrbiQy7araa3EJKUlyT47kPnBgBCTt/S/Yner4yaqkdNuZ0TXUFnc3LLTNUpSl7ONSyp48QOaYwKUw0yL6IOmof9Hp9e5PKA3w5xne3R0UV0pI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UpNG8ZMt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UpNG8ZMt" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2727EC4CED1; Wed, 5 Feb 2025 16:08:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738771700; bh=qJFZa1EKck3rTDkEkJN+mxWME2YNA+lKI4hydp08qho=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=UpNG8ZMtZrQa2NketkiehLRBvneCbXCG3J24ifhHwc6Lu8+vkuJpk55h21GBAd258 WVvk/OWpKJV+KR+vnjeD4/DwNtr4l/6nuMkTp47khFLds/JiZuZzyfF53dAUBdEewA LqsvzIQxOhU8J6HEu711yHDvUx0MdNHcqsSTDdcbWyXu6ZHWvZVy5gflfOQpAFpxFT TfH93rgJ483hgIx+ZtZSuG5tILERQ9+PMY4AWd92P/TmjmWuFaGyJ0WCtncIU50Aa2 Uz7ckmtjWlZtPuLDljHiNw7rcPX6PrBZ9P8EwH9a52b/i2nV/VFseOwzxA0DYBa7Iq j9Vg6DUqLZGog== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Eric Biggers , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/6] RISC-V: add vector crypto extension validation checks Date: Wed, 5 Feb 2025 16:05:08 +0000 Message-ID: <20250205-quench-entrench-09bed8c8c823@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250205-cobbler-unpadded-5580c1f5d946@spud> References: <20250205-cobbler-unpadded-5580c1f5d946@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=6134; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=ONsc8bsazl5cw6gaE940j7lsoq9zYTyfrqkv0H4vDBo=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOmLe2wcLVxvXpZ0yjRwiNdbHcT+Xz2w1GD1RqGTVf9ld nNyOF7vKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwEQ+5zD8j1r37Kf/60ks+337 PfzL1I8rlejOniLcYfTVvEN31fvNJowMPcHM+yfemrjEsvPnXlWu64nzuM+xrA6+xVzaPnfZzB3 GrAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Using Clement's new validation callbacks, support checking that dependencies have been satisfied for the vector crpyto extensions. Currently riscv_isa_extension_available() will return true on systems that support the extensions but vector itself has been disabled by the kernel, adding validation callbacks will prevent such a scenario from occuring and make the behaviour of the extension detection functions more consistent with user expectations - it's not expected to have to check for vector AND the specific crypto extension. The 1.0.0 Vector crypto spec states: The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the composite extensions Zvkn and Zvks-- require a Zve64x base, or application ("V") base Vector Extension. All of the other Vector Crypto Extensions can be built on any embedded (Zve*) or application ("V") base Vector Extension. and this could be used as the basis for checking that the correct base for individual crypto extensions, but that's not really the kernel's job in my opinion and it is sufficient to leave that sort of precision to the dt-bindings. The kernel only needs to make sure that vector, in some form, is available. Since vector will now be disabled proactively, there's no need to clear the bit in elf_hwcap in riscv_fill_hwcap() any longer. Link: https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0 Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 49 +++++++++++++++++++++++----------- 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 40a24b08d905..1c148ecea612 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -138,6 +138,23 @@ static int riscv_ext_vector_float_validate(const struc= t riscv_isa_ext_data *data return 0; } =20 +static int riscv_ext_vector_crypto_validate(const struct riscv_isa_ext_dat= a *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_RISCV_ISA_V)) + return -EINVAL; + + /* + * It isn't the kernel's job to check that the binding is correct, so + * it should be enough to check that any of the vector extensions are + * enabled, which in-turn means that vector is usable in this kernel + */ + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZVE32X)) + return -EINVAL; + + return 0; +} + static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { @@ -397,8 +414,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(zksed, RISCV_ISA_EXT_ZKSED), __RISCV_ISA_EXT_DATA(zksh, RISCV_ISA_EXT_ZKSH), __RISCV_ISA_EXT_DATA(ztso, RISCV_ISA_EXT_ZTSO), - __RISCV_ISA_EXT_SUPERSET(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_exts), - __RISCV_ISA_EXT_DATA(zvbc, RISCV_ISA_EXT_ZVBC), + __RISCV_ISA_EXT_SUPERSET_VALIDATE(zvbb, RISCV_ISA_EXT_ZVBB, riscv_zvbb_ex= ts, riscv_ext_vector_x_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvbc, RISCV_ISA_EXT_ZVBC, riscv_ext_vector_= crypto_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve32f, RISCV_ISA_EXT_ZVE32F, riscv_zve= 32f_exts, riscv_ext_vector_float_validate), __RISCV_ISA_EXT_DATA_VALIDATE(zve32x, RISCV_ISA_EXT_ZVE32X, riscv_ext_vec= tor_x_validate), __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64d, RISCV_ISA_EXT_ZVE64D, riscv_zve= 64d_exts, riscv_ext_vector_float_validate), @@ -406,20 +423,20 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_SUPERSET_VALIDATE(zve64x, RISCV_ISA_EXT_ZVE64X, riscv_zve= 64x_exts, riscv_ext_vector_x_validate), __RISCV_ISA_EXT_DATA(zvfh, RISCV_ISA_EXT_ZVFH), __RISCV_ISA_EXT_DATA(zvfhmin, RISCV_ISA_EXT_ZVFHMIN), - __RISCV_ISA_EXT_DATA(zvkb, RISCV_ISA_EXT_ZVKB), - __RISCV_ISA_EXT_DATA(zvkg, RISCV_ISA_EXT_ZVKG), - __RISCV_ISA_EXT_BUNDLE(zvkn, riscv_zvkn_bundled_exts), - __RISCV_ISA_EXT_BUNDLE(zvknc, riscv_zvknc_bundled_exts), - __RISCV_ISA_EXT_DATA(zvkned, RISCV_ISA_EXT_ZVKNED), - __RISCV_ISA_EXT_BUNDLE(zvkng, riscv_zvkng_bundled_exts), - __RISCV_ISA_EXT_DATA(zvknha, RISCV_ISA_EXT_ZVKNHA), - __RISCV_ISA_EXT_DATA(zvknhb, RISCV_ISA_EXT_ZVKNHB), - __RISCV_ISA_EXT_BUNDLE(zvks, riscv_zvks_bundled_exts), - __RISCV_ISA_EXT_BUNDLE(zvksc, riscv_zvksc_bundled_exts), - __RISCV_ISA_EXT_DATA(zvksed, RISCV_ISA_EXT_ZVKSED), - __RISCV_ISA_EXT_DATA(zvksh, RISCV_ISA_EXT_ZVKSH), - __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), - __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkb, RISCV_ISA_EXT_ZVKB, riscv_ext_vector_= crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkg, RISCV_ISA_EXT_ZVKG, riscv_ext_vector_= crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkn, riscv_zvkn_bundled_exts, riscv_ext_= vector_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvknc, riscv_zvknc_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkned, RISCV_ISA_EXT_ZVKNED, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvkng, riscv_zvkng_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvknha, RISCV_ISA_EXT_ZVKNHA, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvknhb, RISCV_ISA_EXT_ZVKNHB, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvks, riscv_zvks_bundled_exts, riscv_ext_= vector_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksc, riscv_zvksc_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvksed, RISCV_ISA_EXT_ZVKSED, riscv_ext_vec= tor_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvksh, RISCV_ISA_EXT_ZVKSH, riscv_ext_vecto= r_crypto_validate), + __RISCV_ISA_EXT_BUNDLE_VALIDATE(zvksg, riscv_zvksg_bundled_exts, riscv_ex= t_vector_crypto_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(zvkt, RISCV_ISA_EXT_ZVKT, riscv_ext_vector_= crypto_validate), __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_e= xts), --=20 2.45.2 From nobody Thu Feb 12 21:25:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 114581DC19F; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BDRsHNiC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B5B65C4CEE2; Wed, 5 Feb 2025 16:08:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738771702; bh=OpUsCuGAiwhWFhUg4CwPzoYyxVGCg38PNLAFcvasv7E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BDRsHNiCJoZiVN8vwgR3TrhOJz4DqmtW3dWw4/MRM1ScVYLyQKjfPH9u3N8y6RGlG pvj8AaBL3tnzV9A0M1r8UdXCOt1Coc7Kn5uksI/Cd1C0KAGjlx0CiYcMou+wTbRRLu +vpeNM51Vle7b/+V5FO7adR+/YNr10TeivCEVn49Id4iWEWux1UwKTu6a26FU4lA6p XA5Za+62i8BLBWOPyU6XE8CB7xnel5Z/gvuah1qp7qvutoEreCxLc1oQA+NUNMTqZ1 TH5RzD61Lnl33/N1sv2oT4sOG5W7f7Bl+7lThubaox5qLJwJVFX1IrCqEAKKjltgNr XvGqdCl/qThoQ== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Eric Biggers , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/6] RISC-V: add f & d extension validation checks Date: Wed, 5 Feb 2025 16:05:09 +0000 Message-ID: <20250205-stifle-remake-4e497e96fd66@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250205-cobbler-unpadded-5580c1f5d946@spud> References: <20250205-cobbler-unpadded-5580c1f5d946@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2478; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=e5M7hBrbniSsnE0QrYa2OQIBkQoeZwSnzZ40MTiuFZQ=; b=kA0DAAgWeLQxh6CCYtIByyZiAGejjDyjl+eX1rBJbBES97QQk5NiPvQsNKTteY0c1eWQ28q6K Ih1BAAWCAAdFiEEYduOhBqv/ES4Q4zteLQxh6CCYtIFAmejjDwACgkQeLQxh6CCYtK9vAEAxN8h myRDv/UodgzN2EOsJGsn3+Gil3P8JlhN9YrM8EAA/3ikXzZK0qHHLekERtXLzMqq4M6Blg1zQRE VVJE0RvkM X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Using Clement's new validation callbacks, support checking that dependencies have been satisfied for the floating point extensions. The check for "d" might be slightly confusingly shorter than that of "f", despite "d" depending on "f". This is because the requirement that a hart supporting double precision must also support single precision, should be validated by dt-bindings etc, not the kernel but lack of support for single precision only is a limitation of the kernel. Since vector will now be disabled proactively, there's no need to clear the bit in elf_hwcap in riscv_fill_hwcap() any longer. Signed-off-by: Conor Dooley Reviewed-by: Cl=C3=A9ment L=C3=A9ger Tested-by: Cl=C3=A9ment L=C3=A9ger --- arch/riscv/kernel/cpufeature.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1c148ecea612..ad4fbaa4ff0d 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -109,6 +109,29 @@ static int riscv_ext_zicboz_validate(const struct risc= v_isa_ext_data *data, return 0; } =20 +static int riscv_ext_f_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d)) { + pr_warn_once("This kernel does not support systems with F but not D\n"); + return -EINVAL; + } + + if (!IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + return 0; +} + +static int riscv_ext_d_validate(const struct riscv_isa_ext_data *data, + const unsigned long *isa_bitmap) +{ + if (!IS_ENABLED(CONFIG_FPU)) + return -EINVAL; + + return 0; +} + static int riscv_ext_vector_x_validate(const struct riscv_isa_ext_data *da= ta, const unsigned long *isa_bitmap) { @@ -368,8 +391,8 @@ const struct riscv_isa_ext_data riscv_isa_ext[] =3D { __RISCV_ISA_EXT_DATA(i, RISCV_ISA_EXT_i), __RISCV_ISA_EXT_DATA(m, RISCV_ISA_EXT_m), __RISCV_ISA_EXT_DATA(a, RISCV_ISA_EXT_a), - __RISCV_ISA_EXT_DATA(f, RISCV_ISA_EXT_f), - __RISCV_ISA_EXT_DATA(d, RISCV_ISA_EXT_d), + __RISCV_ISA_EXT_DATA_VALIDATE(f, RISCV_ISA_EXT_f, riscv_ext_f_validate), + __RISCV_ISA_EXT_DATA_VALIDATE(d, RISCV_ISA_EXT_d, riscv_ext_d_validate), __RISCV_ISA_EXT_DATA(q, RISCV_ISA_EXT_q), __RISCV_ISA_EXT_SUPERSET(c, RISCV_ISA_EXT_c, riscv_c_exts), __RISCV_ISA_EXT_SUPERSET_VALIDATE(v, RISCV_ISA_EXT_v, riscv_v_exts, riscv= _ext_vector_float_validate), --=20 2.45.2 From nobody Thu Feb 12 21:25:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 377FB194C61; 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dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="M4En6XTU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4BC32C4CEE2; Wed, 5 Feb 2025 16:08:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738771705; bh=PBTPbAPIWX+QDh4lvcUtj+0ELhjT53JUuY94iLECXmc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=M4En6XTU4gYjM6SblHahsMQFrwquDVrtXhwSOiRd/NNQJVnCAyqvdQY6YapDezFDZ T3rE4qAj6EGNKFBj3I2zifN/45tOUFBp56uQIbe82nWrgE4tgU3A4DwtCisT+kxlMY pVZPkCXzxQOItYf3yEP8Re1gX2bVT82KFcmVfVXuvixXrrz8DYlOvBCfJUatVSMXqp DgKYq51kwuTxFQQMDkwflKOGPqRe1yWuXO9AnLqI+ZU9nwCujIcGFKdvbcFGYT3xep O9zedOVYgFiKqzAiU0UuXRm1TO1WAf3AsZL4smgrgJMddTR0AXD1lI4P49CY4EoyXe 8qPf2mzfIPTEg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Eric Biggers , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 4/6] dt-bindings: riscv: d requires f Date: Wed, 5 Feb 2025 16:05:10 +0000 Message-ID: <20250205-flatly-clover-ae7016cb6e04@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250205-cobbler-unpadded-5580c1f5d946@spud> References: <20250205-cobbler-unpadded-5580c1f5d946@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=openpgp-sha256; l=1242; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=dYPhJy02rU+uIlGkMnAKd9ueA9RZPFw8XUqVyW1zPdM=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOmLe2wyn2Zpc1yYeiZ41d8nEiVLN8wVerFq7twTB6+5B x7SDShv6ShlYRDjYJAVU2RJvN3XIrX+j8sO5563MHNYmUCGMHBxCsBEJp5l+F8j+dNOqWN3k5H2 ND/tQzuX3e94eW31mWv7wwXd6natl3diZHhYuGNy080ni/PWMn1Ysopp5RNZ6wV+tQ1n7x4ON+W +e4UHAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable From: Conor Dooley Per the specifications, the d extension for double-precision floating point operations depends on the f extension for single-precision floating point. Add that requirement to the bindings. This differs from the Linux implementation, where single-precious only is not supported. Reviewed-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index a63b994e0763..ebb252275ddd 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -639,6 +639,12 @@ properties: https://github.com/T-head-Semi/thead-extension-spec/blob/95358= cb2cca9489361c61d335e03d3134b14133f/xtheadvector.adoc. =20 allOf: + - if: + contains: + const: d + then: + contains: + const: f # Zcb depends on Zca - if: contains: --=20 2.45.2 From nobody Thu Feb 12 21:25:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B9F31DF98F; Wed, 5 Feb 2025 16:08:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738771708; cv=none; b=pm7wEE0K1xBXGtw6fme6t35TNPz4DlhRMupSHe4VA5B0KYZxFQ5SdB2uVXNknSYy4pBGhXzQ2+kBH/Jt2HMB4zoZHcfEnbYOeNAMhchtO0FGzhAdw/gTG+rtdAj8/1vGmx8iS6QvZ6VfCPz6QXp7q1ZQ5waQKKGnXZCB2brLixM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738771708; c=relaxed/simple; bh=Hx6D1rRpddICfBXk7BrrDIlZsj2WNmHzrd9slgJOb4Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XGIvSnUJHynGmz8QLBLeOxza0LLEfWk/iSs8VTtprzcvsdzmNNu8WOHxFmcgIWFM082qnOZIqpcLMS4h9ygu6aux0JKZsaUz4M4Zqdr48owzRahYFXyggDxew1/by1oAiVZKUNWN025QL7eVYaS7OPQp8jkAuvspCFssx6GAwKo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Io5PPFVY; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Io5PPFVY" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08174C4CED1; Wed, 5 Feb 2025 16:08:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738771708; bh=Hx6D1rRpddICfBXk7BrrDIlZsj2WNmHzrd9slgJOb4Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Io5PPFVYw7DH0OOFqTIgz5a0FBa0YyVLsVV55Bs1qViAsGGjdwYTZsqw4XsXtHi4j rdYoNiaFF53kMn4Tck0hE2DNnjvCaZ9rPMjqv8ljlUXHyBSqv+7RdLP7JmePdwxREe 8RuwAylKBRa90LauSOjQzUxMzo/kKpq3ZZjz7iaM9j+RflQ81rQYkgxtSbm9UX5M5C HD2MRso0T/TDKlRLzooD92i4+mDHnWi9UGTD/aRHB79XzFYztchvmgEjrWlugiQLv+ KGU+4H+1LyDxn/g1xMd7omKtfGaJj+R4P3QewbHlZMn03ja6e7c9RVasI/xZkM6zSu aEAEnAOdMdd7A== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Eric Biggers , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 5/6] dt-bindings: riscv: add vector sub-extension dependencies Date: Wed, 5 Feb 2025 16:05:11 +0000 Message-ID: <20250205-scalding-huntress-a45cab00ad1c@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250205-cobbler-unpadded-5580c1f5d946@spud> References: <20250205-cobbler-unpadded-5580c1f5d946@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Developer-Signature: v=1; a=openpgp-sha256; l=2332; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=GdLuIc5EAIS3gpLTxrlq7jFgE0FxstD07lH/xrh31/s=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOmLe2xTDnxPurbp87SZax+p3PPk5rSPWK6ZW2nA/Xr7D iv/0JJPHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZhIcxsjQ5PirrqmnspCfnHW lp2FwX4HjNSZwubt2HKhf+Zq2+bX1owMV83sVFLXqb5b5640qWvBtP+GsxbN2HRT//iJZf0qWrv 2MgAA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable From: Conor Dooley Section 33.18.2. Zve*: Vector Extensions for Embedded Processors in [1] says: | The Zve32f and Zve64x extensions depend on the Zve32x extension. The Zve6= 4f extension depends | on the Zve32f and Zve64x extensions. The Zve64d extension depends on the = Zve64f extension | The Zve32x extension depends on the Zicsr extension. The Zve32f and Zve64= f extensions depend | upon the F extension | The Zve64d extension depends upon the D extension Apply these rules to the bindings to help prevent invalid combinations. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-rele= ase-698e64a-2024-09-09 [1] Reviewed-by: Cl=C3=A9ment L=C3=A9ger Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 46 +++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index ebb252275ddd..02065664f819 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -680,6 +680,52 @@ properties: contains: const: zca =20 + - if: + contains: + const: zve32x + then: + contains: + const: zicsr + + - if: + contains: + const: zve32f + then: + allOf: + - contains: + const: f + - contains: + const: zve32x + + - if: + contains: + const: zve64x + then: + contains: + const: zve32x + + - if: + contains: + const: zve64f + then: + allOf: + - contains: + const: f + - contains: + const: zve32f + - contains: + const: zve64x + + - if: + contains: + const: zve64d + then: + allOf: + - contains: + const: d + - contains: + const: zve64f + allOf: # Zcf extension does not exist on rv64 - if: --=20 2.45.2 From nobody Thu Feb 12 21:25:24 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9ACEB1DF98F; Wed, 5 Feb 2025 16:08:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738771711; cv=none; b=qGcwAjckXxDJyrrDBKfHPPDnoMc/Kjl7u8u0ZexMbN44vWc+Ysy9yaxOOD465mmFuv34nTUzCDWEwGWCtbzekggE308N+STgEzl/STnjKX/9OO5dhZlOQkXtoWZz5PAFkj0ccWLXdqJPgcFVDKPA0U4x/k8gnWVFcjRoMBPH2bI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738771711; c=relaxed/simple; bh=23nEvqAgqDq/DOPfIpZhT0472bYiLNAR6cd2MSKj14w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mMn0HtKXZnvrJ286ryEPDHKczKZuhaMFerU5gRKWhBH6eurwbIXxrsrvSpUu89FCMxIqpUYUL0aiELAsjCmB1tIUlZEafMkKtYgXEKfIRusCeamLTW7W6Zsheo2gDXqnuXrddb5JhxdhyqPVTjKCbr5aA9InUJRSQgOuPN/s/U4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l+Av3mmy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l+Av3mmy" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B8AAEC4CEDD; Wed, 5 Feb 2025 16:08:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738771711; bh=23nEvqAgqDq/DOPfIpZhT0472bYiLNAR6cd2MSKj14w=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=l+Av3mmy+6T64+lY9WygDOfeDV7rgXn/2RZVycV6xOeXJPQCAYz++p+PkiTs1xi2Y UEVWi0Ipa+KgxrZkNsBhMCHUZZvc3boeTGFY2S6pR7owWmOvWgsVhiLuqf03HMmlxu tyI/cxlfoAfG/wKK4nR/UR26ABUw7VdK1dmMePCU0tCSELqFfdPl4tbv0gpY8fjxcv yswn2CvRoBD/aM4e2AKIlGNDn41v8IzY8qFChH+Eow0EmLmeLOxB0ReJ1CCxiVQb7m S8gynj07gbvqrMGZqzk7Q1oqJm92xbfaqJ49XsCuLCQgM5D1CzoiYYF+pQrHMuFIHc CiBoR+hQyt+Mg== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Eric Biggers , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , =?UTF-8?q?Cl=C3=A9ment=20L=C3=A9ger?= , Andy Chiu , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 6/6] dt-bindings: riscv: document vector crypto requirements Date: Wed, 5 Feb 2025 16:05:12 +0000 Message-ID: <20250205-ludicrous-gratify-b2ae27b95ebd@spud> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250205-cobbler-unpadded-5580c1f5d946@spud> References: <20250205-cobbler-unpadded-5580c1f5d946@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2259; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=4C+zfCw5yJE5unx/bTKD27SZG4062igzYOF7ISnVt+Q=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDOmLe2y7Bfanpene8DU3nMQ7YfGKj5WTr/KeP7ovccbds kWm0W6fO0pZGMQ4GGTFFFkSb/e1SK3/47LDuectzBxWJpAhDFycAjCRzccZ/pn4u7gq2lttnn6/ WTmxM/2eY+T1TyVPjii/j/x85dZf6yxGhoMX+K6HTk29emNWSLPUFCGV7XnGT3UmvvjzxKFv8TP j6UwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Conor Dooley Section 35.2. Extensions Overview of [1] says: | The Zvknhb and Zvbc Vector Crypto Extensions --and accordingly the compos= ite extensions Zvkn and | Zvks-- (sic) require a Zve64x base, or application ("V") base Vector Exte= nsion. | All of the other Vector Crypto Extensions can be built on any embedded (Z= ve*) or application ("V") base | Vector Extension Eric Biggars pointed out that the spec is actually incorrect, and that the list of instructions requiring a Zve64x base is actually: Zvkn, Zvknc, Zvkng and Zvksc. Implement the rules according to his PR [2]. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-isa-rele= ase-698e64a-2024-09-09 [1] Link: https://github.com/riscv/riscv-isa-manual/pull/1697 [2] Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/extensions.yaml | 33 +++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Docu= mentation/devicetree/bindings/riscv/extensions.yaml index 02065664f819..9aeb9d4731ca 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -726,6 +726,39 @@ properties: - contains: const: zve64f =20 + - if: + contains: + anyOf: + - const: zvbc + - const: zvkn + - const: zvknc + - const: zvkng + - const: zvknhb + - const: zvksc + then: + contains: + anyOf: + - const: v + - const: zve64x + + - if: + contains: + anyOf: + - const: zvbb + - const: zvkb + - const: zvkg + - const: zvkned + - const: zvknha + - const: zvksed + - const: zvksh + - const: zvks + - const: zvkt + then: + contains: + anyOf: + - const: v + - const: zve32x + allOf: # Zcf extension does not exist on rv64 - if: --=20 2.45.2