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Signed-off-by: Frank Li --- change from v1 to v2 - move scu reset under scu node - add 8qm comaptible string for mipi csi2 and mipi csi phys. --- arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi | 391 ++++++++++++++++++= ++++ arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi | 53 +++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 5 + arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi | 60 ++++ arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 5 + 5 files changed, 514 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/bo= ot/dts/freescale/imx8-ss-img.dtsi index d39242c1b9f79..0ca7f7406c842 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi @@ -3,6 +3,14 @@ * Copyright 2019-2021 NXP * Zhou Guoniu */ + +img_axi_clk: clock-img-axi { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <400000000>; + clock-output-names =3D "img_axi_clk"; +}; + img_ipg_clk: clock-img-ipg { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -10,12 +18,285 @@ img_ipg_clk: clock-img-ipg { clock-output-names =3D "img_ipg_clk"; }; =20 +img_pxl_clk: clock-img-pxl { + compatible =3D "fixed-clock"; + #clock-cells =3D <0>; + clock-frequency =3D <600000000>; + clock-output-names =3D "img_pxl_clk"; +}; + img_subsys: bus@58000000 { compatible =3D "simple-bus"; #address-cells =3D <1>; #size-cells =3D <1>; ranges =3D <0x58000000 0x0 0x58000000 0x1000000>; =20 + isi: isi@58100000 { + reg =3D <0x58100000 0x90000>; + interrupts =3D , + , + , + , + , + , + , + ; + clocks =3D <&pdma0_lpcg IMX_LPCG_CLK_0>, + <&pdma1_lpcg IMX_LPCG_CLK_0>, + <&pdma2_lpcg IMX_LPCG_CLK_0>, + <&pdma3_lpcg IMX_LPCG_CLK_0>, + <&pdma4_lpcg IMX_LPCG_CLK_0>, + <&pdma5_lpcg IMX_LPCG_CLK_0>, + <&pdma6_lpcg IMX_LPCG_CLK_0>, + <&pdma7_lpcg IMX_LPCG_CLK_0>; + clock-names =3D "per0", + "per1", + "per2", + "per3", + "per4", + "per5", + "per6", + "per7"; + interrupt-parent =3D <&gic>; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>, + <&pd IMX_SC_R_ISI_CH1>, + <&pd IMX_SC_R_ISI_CH2>, + <&pd IMX_SC_R_ISI_CH3>, + <&pd IMX_SC_R_ISI_CH4>, + <&pd IMX_SC_R_ISI_CH5>, + <&pd IMX_SC_R_ISI_CH6>, + <&pd IMX_SC_R_ISI_CH7>; + status =3D "disabled"; + }; + + irqsteer_csi0: irqsteer@58220000 { + compatible =3D "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; + reg =3D <0x58220000 0x1000>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts =3D ; + clocks =3D <&img_ipg_clk>; + clock-names =3D "ipg"; + interrupt-parent =3D <&gic>; + power-domains =3D <&pd IMX_SC_R_CSI_0>; + fsl,channel =3D <0>; + fsl,num-irqs =3D <32>; + status =3D "disabled"; + }; + + mipi_csi_0_phy: phy@58221000 { + compatible =3D "fsl,imx8qxp-mipi-cphy"; + reg =3D <0x58221000 0x1000>; + #phy-cells =3D <0>; + power-domains =3D <&pd IMX_SC_R_CSI_0>; + }; + + gpio0_mipi_csi0: gpio@58222000 { + compatible =3D "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg =3D <0x58222000 0x1000>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D <0>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&irqsteer_csi0>; + power-domains =3D <&pd IMX_SC_R_CSI_0>; + }; + + csi0_core_lpcg: clock-controller@58223018 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58223018 0x4>; + clocks =3D <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_PER>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "csi0_lpcg_core_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>; + }; + + csi0_esc_lpcg: clock-controller@5822301c { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x5822301c 0x4>; + clocks =3D <&clk IMX_SC_R_CSI_0 IMX_SC_PM_CLK_MISC>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "csi0_lpcg_esc_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>; + }; + + i2c_mipi_csi0: i2c@58226000 { + compatible =3D "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x58226000 0x1000>; + interrupts =3D <8>; + clocks =3D <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names =3D "per", "ipg"; + assigned-clocks =3D <&clk IMX_SC_R_CSI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates =3D <24000000>; + interrupt-parent =3D <&irqsteer_csi0>; + power-domains =3D <&pd IMX_SC_R_CSI_0_I2C_0>; + status =3D "disabled"; + }; + + mipi_csi_0: csi@58227000 { + compatible =3D "fsl,imx8qxp-mipi-csi2"; + reg =3D <0x58227000 0x1000>; + clocks =3D <&csi0_core_lpcg IMX_LPCG_CLK_4>, + <&csi0_esc_lpcg IMX_LPCG_CLK_4>, + <&csi0_pxl_lpcg IMX_LPCG_CLK_0>; + clock-names =3D "core", "esc", "ui"; + assigned-clocks =3D <&csi0_core_lpcg IMX_LPCG_CLK_4>, + <&csi0_esc_lpcg IMX_LPCG_CLK_4>; + assigned-clock-rates =3D <360000000>, <72000000>; + phys =3D <&mipi_csi_0_phy>; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>; + resets =3D <&scu_reset IMX_SC_R_CSI_0>; + status =3D "disabled"; + }; + + irqsteer_csi1: irqsteer@58240000 { + compatible =3D "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; + reg =3D <0x58240000 0x1000>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts =3D ; + clocks =3D <&img_ipg_clk>; + clock-names =3D "ipg"; + interrupt-parent =3D <&gic>; + power-domains =3D <&pd IMX_SC_R_CSI_1>; + fsl,channel =3D <0>; + fsl,num-irqs =3D <32>; + status =3D "disabled"; + }; + + mipi_csi_1_phy: phy@58241000 { + compatible =3D"fsl,imx8qxp-mipi-cphy"; + reg =3D <0x58241000 0x1000>; + #phy-cells =3D <0>; + power-domains =3D <&pd IMX_SC_R_CSI_1>; + status =3D "disabled"; + }; + + gpio0_mipi_csi1: gpio@58242000 { + compatible =3D "fsl,imx8qm-gpio", "fsl,imx35-gpio"; + reg =3D <0x58242000 0x1000>; + #interrupt-cells =3D <2>; + interrupt-controller; + interrupts =3D <0>; + #gpio-cells =3D <2>; + gpio-controller; + interrupt-parent =3D <&irqsteer_csi1>; + power-domains =3D <&pd IMX_SC_R_CSI_1>; + }; + + csi1_core_lpcg: clock-controller@58243018 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58243018 0x4>; + clocks =3D <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_PER>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "csi1_lpcg_core_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>; + }; + + csi1_esc_lpcg: clock-controller@5824301c { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x5824301c 0x4>; + clocks =3D <&clk IMX_SC_R_CSI_1 IMX_SC_PM_CLK_MISC>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "csi1_lpcg_esc_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>; + }; + + i2c_mipi_csi1: i2c@58246000 { + compatible =3D "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x58246000 0x1000>; + interrupts =3D <8>; + clocks =3D <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names =3D "per", "ipg"; + assigned-clocks =3D <&clk IMX_SC_R_CSI_1_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates =3D <24000000>; + interrupt-parent =3D <&irqsteer_csi1>; + power-domains =3D <&pd IMX_SC_R_CSI_1_I2C_0>; + status =3D "disabled"; + }; + + mipi_csi_1: csi@58247000 { + compatible =3D "fsl,imx8qxp-mipi-csi2"; + reg =3D <0x58247000 0x1000>; + clocks =3D <&csi1_core_lpcg IMX_LPCG_CLK_4>, + <&csi1_esc_lpcg IMX_LPCG_CLK_4>, + <&csi1_pxl_lpcg IMX_LPCG_CLK_0>; + clock-names =3D "core", "esc", "ui"; + assigned-clocks =3D <&csi1_core_lpcg IMX_LPCG_CLK_4>, + <&csi1_esc_lpcg IMX_LPCG_CLK_4>; + assigned-clock-rates =3D <360000000>, <72000000>; + phys =3D <&mipi_csi_1_phy>; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>; + resets =3D <&scu_reset IMX_SC_R_CSI_1>; + status =3D "disabled"; + }; + + irqsteer_parallel: irqsteer@58260000 { + compatible =3D "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer"; + reg =3D <0x58260000 0x1000>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupts =3D ; + clocks =3D <&clk_dummy>; + clock-names =3D "ipg"; + interrupt-parent =3D <&gic>; + power-domains =3D <&pd IMX_SC_R_PI_0>; + fsl,channel =3D <0>; + fsl,num-irqs =3D <32>; + status =3D "disabled"; + }; + + pi0_ipg_lpcg: clock-controller@58263004 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58263004 0x4>; + clocks =3D <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pi0_lpcg_ipg_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_pxl_lpcg: clock-controller@58263018 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58263018 0x4>; + clocks =3D <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_PER>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pi0_lpcg_pxl_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>; + }; + + pi0_misc_lpcg: clock-controller@5826301c { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x5826301c 0x4>; + clocks =3D <&clk IMX_SC_R_PI_0 IMX_SC_PM_CLK_MISC0>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pi0_lpcg_misc_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>; + }; + + i2c0_parallel: i2c@58266000 { + compatible =3D "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + reg =3D <0x58266000 0x1000>; + interrupts =3D <8>; + clocks =3D <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>, + <&img_ipg_clk>; + clock-names =3D "per", "ipg"; + assigned-clocks =3D <&clk IMX_SC_R_PI_0_I2C_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates =3D <24000000>; + interrupt-parent =3D <&irqsteer_parallel>; + power-domains =3D <&pd IMX_SC_R_PI_0_I2C_0>; + status =3D "disabled"; + }; + jpegdec: jpegdec@58400000 { reg =3D <0x58400000 0x00050000>; interrupts =3D ; @@ -40,6 +321,116 @@ jpegenc: jpegenc@58450000 { <&pd IMX_SC_R_MJPEG_ENC_S0>; }; =20 + pdma0_lpcg: clock-controller@58500000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58500000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pdma0_lpcg_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>; + }; + + pdma1_lpcg: clock-controller@58510000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58510000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pdma1_lpcg_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH1>; + }; + + pdma2_lpcg: clock-controller@58520000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58520000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pdma2_lpcg_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH2>; + }; + + pdma3_lpcg: clock-controller@58530000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58530000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pdma3_lpcg_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH3>; + }; + + pdma4_lpcg: clock-controller@58540000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58540000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pdma4_lpcg_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH4>; + }; + + pdma5_lpcg: clock-controller@58550000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58550000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pdma5_lpcg_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH5>; + }; + + pdma6_lpcg: clock-controller@58560000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58560000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pdma6_lpcg_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH6>; + }; + + pdma7_lpcg: clock-controller@58570000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58570000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "pdma7_lpcg_clk"; + power-domains =3D <&pd IMX_SC_R_ISI_CH7>; + }; + + csi0_pxl_lpcg: clock-controller@58580000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58580000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "csi0_lpcg_pxl_clk"; + power-domains =3D <&pd IMX_SC_R_CSI_0>; + }; + + csi1_pxl_lpcg: clock-controller@58590000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x58590000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "csi1_lpcg_pxl_clk"; + power-domains =3D <&pd IMX_SC_R_CSI_1>; + }; + + hdmi_rx_pxl_link_lpcg: clock-controller@585a0000 { + compatible =3D "fsl,imx8qxp-lpcg"; + reg =3D <0x585a0000 0x10000>; + clocks =3D <&img_pxl_clk>; + #clock-cells =3D <1>; + clock-indices =3D ; + clock-output-names =3D "hdmi_rx_lpcg_pxl_link_clk"; + power-domains =3D <&pd IMX_SC_R_HDMI_RX>; + }; + img_jpeg_dec_lpcg: clock-controller@585d0000 { compatible =3D "fsl,imx8qxp-lpcg"; reg =3D <0x585d0000 0x10000>; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/= boot/dts/freescale/imx8qm-ss-img.dtsi index 2bbdacb1313f9..946055ec25424 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi @@ -3,6 +3,31 @@ * Copyright 2021 NXP */ =20 +&isi { + compatible =3D "fsl,imx8qm-isi"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + + port@3 { + reg =3D <3>; + }; + }; +}; + &jpegdec { compatible =3D "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgdec"; }; @@ -10,3 +35,31 @@ &jpegdec { &jpegenc { compatible =3D "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc"; }; + +&mipi_csi_0 { + compatible =3D "fsl,imx8qm-mipi-csi2", "fsl,imx8qxp-mipi-csi2"; +}; + +&mipi_csi_0_phy { + compatible =3D "fsl,imx8qm-mipi-cphy", "fsl,imx8qxp-mipi-cphy"; +}; + +&mipi_csi_1 { + compatible =3D "fsl,imx8qm-mipi-csi2", "fsl,imx8qxp-mipi-csi2"; +}; + +&mipi_csi_1_phy { + compatible =3D "fsl,imx8qm-mipi-cphy", "fsl,imx8qxp-mipi-cphy"; +}; + +&pi0_ipg_lpcg { + status =3D "disabled"; +}; + +&pi0_misc_lpcg { + status =3D "disabled"; +}; + +&pi0_pxl_lpcg { + status =3D "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8qm.dtsi index 6fa31bc9ece8f..c6a17a0d739c5 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -333,6 +333,11 @@ iomuxc: pinctrl { compatible =3D "fsl,imx8qm-iomuxc"; }; =20 + scu_reset: reset-controller { + compatible =3D "fsl,imx-scu-reset"; + #reset-cells =3D <1>; + }; + rtc: rtc { compatible =3D "fsl,imx8qxp-sc-rtc"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi b/arch/arm64= /boot/dts/freescale/imx8qxp-ss-img.dtsi index 3a087317591d8..4c15e4569a51a 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-img.dtsi @@ -4,6 +4,62 @@ * Dong Aisheng */ =20 +&csi1_pxl_lpcg { + status =3D "disabled"; +}; + +&csi1_core_lpcg { + status =3D "disabled"; +}; + +&csi1_esc_lpcg { + status =3D "disabled"; +}; + +&gpio0_mipi_csi1 { + status =3D "disabled"; +}; + +&i2c_mipi_csi1 { + status =3D "disabled"; +}; + +&irqsteer_csi1 { + status =3D "disabled"; +}; + +&isi { + compatible =3D "fsl,imx8qxp-isi"; + interrupts =3D , + , + , + , + ; + clocks =3D <&pdma0_lpcg IMX_LPCG_CLK_0>, <&pdma4_lpcg IMX_LPCG_CLK_0>, + <&pdma5_lpcg IMX_LPCG_CLK_0>, <&pdma6_lpcg IMX_LPCG_CLK_0>, + <&pdma7_lpcg IMX_LPCG_CLK_0>; + clock-names =3D "per0", "per4", "per5", "per6", "per7"; + power-domains =3D <&pd IMX_SC_R_ISI_CH0>, <&pd IMX_SC_R_ISI_CH4>, <&pd IM= X_SC_R_ISI_CH5>, + <&pd IMX_SC_R_ISI_CH6>, <&pd IMX_SC_R_ISI_CH7>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + }; + + port@1 { + reg =3D <1>; + }; + + port@2 { + reg =3D <2>; + }; + }; +}; + &jpegdec { compatible =3D "nxp,imx8qxp-jpgdec"; }; @@ -11,3 +67,7 @@ &jpegdec { &jpegenc { compatible =3D "nxp,imx8qxp-jpgenc"; }; + +&mipi_csi_1 { + status =3D "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8qxp.dtsi index 05138326f0a57..c078d92f76c0e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -241,6 +241,11 @@ scu_key: keys { status =3D "disabled"; }; =20 + scu_reset: reset-controller { + compatible =3D "fsl,imx-scu-reset"; + #reset-cells =3D <1>; + }; + rtc: rtc { compatible =3D "fsl,imx8qxp-sc-rtc"; }; --=20 2.34.1