From nobody Sun Dec 14 14:12:13 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BAE53156237; Tue, 4 Feb 2025 01:16:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738631811; cv=none; b=jRAGkfpnVRBBhpG1lREDdW9GjpqZscVEv2XYwMzWFTQ+HwiFghbRajx1K8l/TqzFBIoM+PfhI4hpexB75J2zKq5Ud/aKMSb9k+G+rdSSLSaIRzL65FNwpPZgcsSyhLKvVtmnCdbJzZ16sguMhvk0F2hOXsfStZESAuOdkXz5wcQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738631811; c=relaxed/simple; bh=yXOgZ4Ewyp6xy3kNIlt/CBUiLWk48ZKj1ErEx52sFNI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=l9B4JeApnNgRS39xYYhaLfwh6Kgp4BKFY9fOGIV/IfR9SfqfyFu18EUcyPy/AEDX5/5JV4MVjCI8YM06R5AeErj/f7eA6sIowRYErnttS3561QOfe/ggrekNBbMq0LvaK4T4Om+7Mm1PPYZukihP22mI435+a8l4mL2G7DPc9Bs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Aj1RsB6A; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Aj1RsB6A" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5141GgRd3125055 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 3 Feb 2025 19:16:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1738631802; bh=dYIjNEsOqTgpLvQ/KHwoL+HBHbAu31AJkzw29SIcCNI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Aj1RsB6APn9xL+lQkHEq5+KQODOjGVKAptGJnu/qY1gTcRVcJXLCM0n6vUYwCPNpm Y8qmWnGvom1ZzNsGtAjd96gBmDmPvSqP+gp1Ho4F1XHwhXVekvrXq7ycSLq3jf+4AS /EKKBJ4ckLN0RGuM9BgFxMCt9tBBfShNkaL5pyLQ= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5141GgoO016764 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 3 Feb 2025 19:16:42 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 3 Feb 2025 19:16:42 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 3 Feb 2025 19:16:42 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5141GfAT024451; Mon, 3 Feb 2025 19:16:42 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla Subject: [PATCH v3 5/9] arm64: dts: ti: k3-am62a7-sk: Enable IPC with remote processors Date: Mon, 3 Feb 2025 19:16:37 -0600 Message-ID: <20250204011641.1523561-6-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250204011641.1523561-1-jm@ti.com> References: <20250204011641.1523561-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Devarsh Thakkar For each remote proc, reserve memory for IPC and bind the mailbox assignments. Two memory regions are reserved for each remote processor. The first region of 1MB of memory is used for Vring shared buffers and the second region is used as external memory to the remote processor for the resource table and for tracebuffer allocations. Signed-off-by: Devarsh Thakkar Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v2: - Fix memory carvout sizes, remove leading zeros - Reorder memory carveouts according to memory location - Fix whitespace issues - Fix commit headers, capitalize IPC --- arch/arm64/boot/dts/ti/k3-am62a7-sk.dts | 90 +++++++++++++++++++++++-- 1 file changed, 84 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts b/arch/arm64/boot/dts/= ti/k3-am62a7-sk.dts index a6f0d87a50d8a..eaffbab093cc1 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk.dts @@ -49,6 +49,42 @@ linux,cma { linux,cma-default; }; =20 + c7x_0_dma_memory_region: c7x-dma-memory@99800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99800000 0x00 0x100000>; + no-map; + }; + + c7x_0_memory_region: c7x-memory@99900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x99900000 0x00 0xf00000>; + no-map; + }; + + mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@9b800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b800000 0x00 0x100000>; + no-map; + }; + + mcu_r5fss0_core0_memory_region: r5f-dma-memory@9b900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9b900000 0x00 0xf00000>; + no-map; + }; + + wkup_r5fss0_core0_dma_memory_region: r5f-dma-memory@9c800000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c800000 0x00 0x100000>; + no-map; + }; + + wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { + compatible =3D "shared-dma-pool"; + reg =3D <0x00 0x9c900000 0x00 0x1e00000>; + no-map; + }; + secure_tfa_ddr: tfa@9e780000 { reg =3D <0x00 0x9e780000 0x00 0x80000>; alignment =3D <0x1000>; @@ -60,12 +96,6 @@ secure_ddr: optee@9e800000 { alignment =3D <0x1000>; no-map; }; - - wkup_r5fss0_core0_memory_region: r5f-dma-memory@9c900000 { - compatible =3D "shared-dma-pool"; - reg =3D <0x00 0x9c900000 0x00 0x01e00000>; - no-map; - }; }; =20 opp-table { @@ -737,3 +767,51 @@ dpi1_out: endpoint { }; }; }; + +&mailbox0_cluster0 { + mbox_r5_0: mbox-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster1 { + mbox_c7x_0: mbox-c7x-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&mailbox0_cluster2 { + mbox_mcu_r5_0: mbox-mcu-r5-0 { + ti,mbox-rx =3D <0 0 0>; + ti,mbox-tx =3D <1 0 0>; + }; +}; + +&wkup_r5fss0 { + status =3D "okay"; +}; + +&wkup_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster0>, <&mbox_r5_0>; + memory-region =3D <&wkup_r5fss0_core0_dma_memory_region>, + <&wkup_r5fss0_core0_memory_region>; +}; + +&mcu_r5fss0 { + status =3D "okay"; +}; + +&mcu_r5fss0_core0 { + mboxes =3D <&mailbox0_cluster2>, <&mbox_mcu_r5_0>; + memory-region =3D <&mcu_r5fss0_core0_dma_memory_region>, + <&mcu_r5fss0_core0_memory_region>; +}; + +&c7x_0 { + mboxes =3D <&mailbox0_cluster1>, <&mbox_c7x_0>; + memory-region =3D <&c7x_0_dma_memory_region>, + <&c7x_0_memory_region>; + status =3D "okay"; +}; --=20 2.48.0