From nobody Sun Dec 14 14:08:20 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A0FF132117; Tue, 4 Feb 2025 01:16:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738631813; cv=none; b=iWTTsiHLSe25ZiKS3SNEE10nv/NJFMJX5Dy3tvbcIS4IQZca1OZVk6w1KewIK+h4U0NABlh68iHHNFWwwBzADebMUo8ZIsLIxZAECDKV8RatBYZzG0Gfbdxm1cxUdCRxmbANSzv66EcqOFEYywgeTQtFtn957rIbL8UqnqKwbDg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738631813; c=relaxed/simple; bh=EcEaHQxviktu2+1wkm0E2tsFSVz7WnA/VOxItSbNJrs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NxlnbyloaNFqk7GPnM1Yh6VlDH4REPf8ewcliEz6qXTvkiWVf7Bnb+alsAyvI1xBQDReuVA5Ym/IOCEvVk5oFy49Jnjcum62TXrQoYh/yTjdLCEu7Nu8QA3Hw24krphSKspogIgjoaoU3xVlnFdpq28x5TTDiDc81zEiN/bUf0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=lXklQ46G; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="lXklQ46G" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 5141GgxH2243641 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 3 Feb 2025 19:16:42 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1738631802; bh=qfNRwzxWn/+WARN6HNDKXgKGg+ZHN4hL9TJorAidzAg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=lXklQ46Gd+4r+DzgOCqvEUZRcmVRvcxiL76fUu60PHoY9Z/CoKnnzbnihqYLlkdK0 n+Mg+RdAyQygcI2a3gxnQF8IPF7WFtZv4rYxH95tteHmvWovlsKNvUFQIcQ3brFxc+ mSyK9aacpijv5q6U6PBz5C3687DUcfUtWvY/gUkk= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 5141GgoM127295 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Mon, 3 Feb 2025 19:16:42 -0600 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Mon, 3 Feb 2025 19:16:41 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Mon, 3 Feb 2025 19:16:41 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 5141GfAQ024451; Mon, 3 Feb 2025 19:16:41 -0600 From: Judith Mendez To: Nishanth Menon , Vignesh Raghavendra CC: Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , , Andrew Davis , Hari Nagalla Subject: [PATCH v3 2/9] arm64: dts: ti: k3-am62a-mcu: Add R5F remote proc node Date: Mon, 3 Feb 2025 19:16:34 -0600 Message-ID: <20250204011641.1523561-3-jm@ti.com> X-Mailer: git-send-email 2.48.0 In-Reply-To: <20250204011641.1523561-1-jm@ti.com> References: <20250204011641.1523561-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Hari Nagalla AM62A SoCs have a single R5F core in the MCU voltage domain. The MCU domain also has a 512KB sram memory, the R5F core can use for applications needing fast memory access. Signed-off-by: Hari Nagalla Signed-off-by: Judith Mendez --- Changes since v2: - Fix whitespace issues --- arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi b/arch/arm64/boot/dts= /ti/k3-am62a-mcu.dtsi index 0469c766b769e..e9042c986e68a 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-mcu.dtsi @@ -6,6 +6,18 @@ */ =20 &cbass_mcu { + mcu_ram: sram@79100000 { + compatible =3D "mmio-sram"; + reg =3D <0x00 0x79100000 0x00 0x80000>; + ranges =3D <0x00 0x00 0x79100000 0x80000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + mcu1-sram@0 { + reg =3D <0x0 0x80000>; + }; + }; + mcu_pmx0: pinctrl@4084000 { compatible =3D "pinctrl-single"; reg =3D <0x00 0x04084000 0x00 0x88>; @@ -175,4 +187,30 @@ mcu_mcan1: can@4e18000 { bosch,mram-cfg =3D <0x0 128 64 64 64 64 32 32>; status =3D "disabled"; }; + + mcu_r5fss0: r5fss@79000000 { + compatible =3D "ti,am62-r5fss"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x79000000 0x00 0x79000000 0x8000>, + <0x79020000 0x00 0x79020000 0x8000>; + power-domains =3D <&k3_pds 7 TI_SCI_PD_EXCLUSIVE>; + status =3D "disabled"; + + mcu_r5fss0_core0: r5f@79000000 { + compatible =3D "ti,am62-r5f"; + reg =3D <0x79000000 0x00008000>, + <0x79020000 0x00008000>; + reg-names =3D "atcm", "btcm"; + ti,sci =3D <&dmsc>; + ti,sci-dev-id =3D <9>; + ti,sci-proc-ids =3D <0x03 0xff>; + resets =3D <&k3_reset 9 1>; + firmware-name =3D "am62a-mcu-r5f0_0-fw"; + ti,atcm-enable =3D <0>; + ti,btcm-enable =3D <1>; + ti,loczrama =3D <0>; + sram =3D <&mcu_ram>; + }; + }; }; --=20 2.48.0