From nobody Sun Dec 14 13:41:12 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5972E2135CD; Tue, 4 Feb 2025 12:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738673910; cv=none; b=EXStdFTLB1/nvmWeEfc47tQ1k90HQUZNIgx/DOtfj0+l5g19acpoCCZ3jGiixl+dM+GRKakZyR48OcshQN2F6HIvoeQVJtU0qpdrWxu309HZKzgvXWbvzmf/ehmTT5e4edyqK80pC9yMxR4vIVWNBYozTEktDr995fVMkf742FE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738673910; c=relaxed/simple; bh=I8DMgUlKxN0YLFW7fIpYk765miWWiSO7x6Ir08Z+YeE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R+f/9HIDUT9ButMqoF/BDdNSfROAP+2DzxC2wnPxLzBBpPTWQqQS1akZp0UZpY1eVJ4srpNnwym6H4AqhBlz4ZcOeYoL358KGlejxr6plpPPDsIWR7O1KdzfivQFrdYQ3/Js0eL1dQQDfvMdoPAdXg9EzeBeviMlFCfwCRFTPR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Z5mKkhMm; arc=none smtp.client-ip=198.175.65.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Z5mKkhMm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738673909; x=1770209909; h=from:date:subject:mime-version:content-transfer-encoding: message-id:references:in-reply-to:to:cc; bh=I8DMgUlKxN0YLFW7fIpYk765miWWiSO7x6Ir08Z+YeE=; b=Z5mKkhMmfwsGW5b7DgcS6kaXr87cWhJQ2qJ95x76opM4MLL8+cYhJrNP oG0VYUzb2ofOLNQnjIhvnQ+VzHtFz3l9k8yIAtGKoGR4gu4b9P4HB8yeX qTC6CmpEPunq7FdfrIOD1Pkuk6T2VASBbe7gTrd4OBVS1V+eJhxVPMMVd 08rKMs9OqmtwZnruY8vNXeEMXUESaOFRGv6fBiFRJjhyL7e0OJJ50UQfB oz4mjcEee4N+jRAaoRbTmm6f4Hxrl9lzja3qPzwDExp2VMoc8KcBXXrqz v4dngbjWzb6Fd5vq+6XvfkQxXN2k6hhTIFP3Ycaju413v2gdXSn7NPXaL Q==; X-CSE-ConnectionGUID: kOLjvJPWQ+uIQpZgTpLrWg== X-CSE-MsgGUID: gSlYTUlpRZCBBRJDO0A9zw== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="39096981" X-IronPort-AV: E=Sophos;i="6.13,258,1732608000"; d="scan'208";a="39096981" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2025 04:58:24 -0800 X-CSE-ConnectionGUID: BroWyTuoSgKikE5YQgTpXA== X-CSE-MsgGUID: VbVTFyJJQtCxvsK7KeJHrA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="133834287" Received: from apgcp0c531115.png.altera.com ([10.244.76.209]) by fmviesa002.fm.intel.com with ESMTP; 04 Feb 2025 04:58:20 -0800 From: Mahesh Rao Date: Tue, 04 Feb 2025 20:58:05 +0800 Subject: [PATCH v3 1/3] dt-bindings: fpga: stratix10: Convert to json-schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250204-socfpga_sip_svc_misc-v3-1-697f7f153cfa@intel.com> References: <20250204-socfpga_sip_svc_misc-v3-0-697f7f153cfa@intel.com> In-Reply-To: <20250204-socfpga_sip_svc_misc-v3-0-697f7f153cfa@intel.com> To: Moritz Fischer , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen , Krzysztof Kozlowski , Wu Hao , Ho Yin , Niravkumar L Rabara Cc: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Mahesh Rao X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738673895; l=2698; i=mahesh.rao@intel.com; s=20250107; h=from:subject:message-id; bh=I8DMgUlKxN0YLFW7fIpYk765miWWiSO7x6Ir08Z+YeE=; b=Q37eBlhDCOqcDCxX5fUIhBab1V2DWJZ3YqBctIfwtLOmq1jDVC9+6iBzbNLet/T3ZC3EsumjV aaqcNyOJPrvB654MQDo3Vl5aQnCJxIuLfWaDuRom4yOO0EOQt2HRrVB X-Developer-Key: i=mahesh.rao@intel.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= Convert intel,stratix10-soc fpga manager devicetree binding file from freeform format to json-schema. Reviewed-by: Rob Herring (Arm) Signed-off-by: Mahesh Rao --- .../fpga/intel,stratix10-soc-fpga-mgr.yaml | 36 ++++++++++++++++++= ++++ .../bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 18 ----------- 2 files changed, 36 insertions(+), 18 deletions(-) diff --git a/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpg= a-mgr.yaml b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpg= a-mgr.yaml new file mode 100644 index 0000000000000000000000000000000000000000..6e536d6b28a9732c492da5d57f8= 9df648dba7f4b --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/intel,stratix10-soc-fpga-mgr.y= aml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Stratix10 SoC FPGA Manager + +maintainers: + - Mahesh Rao + - Adrian Ng Ho Yin + - Niravkumar L Rabara + +description: + The Intel Stratix10 SoC consists of a 64-bit quad-core ARM Cortex A53 ha= rd + processor system (HPS) and a Secure Device Manager (SDM). The Stratix10 + SoC FPGA Manager driver is used to configure/reconfigure the FPGA fabric + on the die.The driver communicates with SDM/ATF via the stratix10-svc + platform driver for performing its operations. + +properties: + compatible: + enum: + - intel,stratix10-soc-fpga-mgr + - intel,agilex-soc-fpga-mgr + +required: + - compatible + +additionalProperties: false + +examples: + - | + fpga-mgr { + compatible =3D "intel,stratix10-soc-fpga-mgr"; + }; diff --git a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpg= a-mgr.txt b/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga= -mgr.txt deleted file mode 100644 index 0f874137ca4697820341b23eddb882634bb131d1..000000000000000000000000000= 0000000000000 --- a/Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.t= xt +++ /dev/null @@ -1,18 +0,0 @@ -Intel Stratix10 SoC FPGA Manager - -Required properties: -The fpga_mgr node has the following mandatory property, must be located un= der -firmware/svc node. - -- compatible : should contain "intel,stratix10-soc-fpga-mgr" or - "intel,agilex-soc-fpga-mgr" - -Example: - - firmware { - svc { - fpga_mgr: fpga-mgr { - compatible =3D "intel,stratix10-soc-fpga-mgr"; - }; - }; - }; --=20 2.35.3 From nobody Sun Dec 14 13:41:12 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14DB1212D83; Tue, 4 Feb 2025 12:58:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738673910; cv=none; b=rwcfb8Wv52yG84+DwaZzmUGdFLkyvtlIobn74AoaCt0snuDQ/M5HEmRaX8cMyZiAJ8uXNU9ALoXtEsCIGYwpj/WOcwxzIKYdZwQIj2IbvAlrGarQr1qHoTd45H+rohVDohQrJrxTVHMxOLpojw6ddFsxnX7QuzOxM8YK0R23IKo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738673910; c=relaxed/simple; bh=mkjBwDH3jRDkTTR0sd3jiLgzDZuZjSG6SUey1iRkwiY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HduV/cGKOfssfdVjH895Us3Y4d+LZnayOneiOptmA4yKVsnwDDizKoHMfsznmtSizxOIdI/WN7da1Z+zfX/jWD7bac78Dd9iProU/FJbSgmde1ZuplHMPsliSVbVWzwv1MUKTOfXgSJUwCmmqafbDCZ+xjwmPKIvI1+baZFQNPw= ARC-Authentication-Results: i=1; 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X-CSE-ConnectionGUID: VooJ8yMET2aotmXMua6Q7g== X-CSE-MsgGUID: 9qPiaz11T0mPLOGLYNN+7Q== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="39096993" X-IronPort-AV: E=Sophos;i="6.13,258,1732608000"; d="scan'208";a="39096993" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2025 04:58:28 -0800 X-CSE-ConnectionGUID: r6P4jrbzQq2hX9L8Sfnrsg== X-CSE-MsgGUID: m/t1IqkjRJ6cSdlN1A4NKA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="133834304" Received: from apgcp0c531115.png.altera.com ([10.244.76.209]) by fmviesa002.fm.intel.com with ESMTP; 04 Feb 2025 04:58:24 -0800 From: Mahesh Rao Date: Tue, 04 Feb 2025 20:58:06 +0800 Subject: [PATCH v3 2/3] dt-bindings: firmware: stratix10: Convert to json-schema Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250204-socfpga_sip_svc_misc-v3-2-697f7f153cfa@intel.com> References: <20250204-socfpga_sip_svc_misc-v3-0-697f7f153cfa@intel.com> In-Reply-To: <20250204-socfpga_sip_svc_misc-v3-0-697f7f153cfa@intel.com> To: Moritz Fischer , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen , Krzysztof Kozlowski , Wu Hao , Ho Yin , Niravkumar L Rabara Cc: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Mahesh Rao X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738673895; l=6327; i=mahesh.rao@intel.com; s=20250107; h=from:subject:message-id; bh=mkjBwDH3jRDkTTR0sd3jiLgzDZuZjSG6SUey1iRkwiY=; b=XVJL0IJAmPWojBwCaXLyBNImwkjARNuZGefSrPthZtWuBWHOT3qRB5JKdcE4XIcAXQNNHoDci IWd5rSdb8OmBcY7vW7TMbCPZEFAGPX/EjGAXJMRxaqmB6F5+A9ZlmrI X-Developer-Key: i=mahesh.rao@intel.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= Convert intel,stratix10-svc service layer devicetree binding file from freeform format to json-schema. Also added DT binding for optional stratix10-soc FPGA manager child node. Signed-off-by: Mahesh Rao Acked-by: Conor Dooley --- .../bindings/firmware/intel,stratix10-svc.txt | 57 ------------- .../bindings/firmware/intel,stratix10-svc.yaml | 93 ++++++++++++++++++= ++++ 2 files changed, 93 insertions(+), 57 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc= .txt b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt deleted file mode 100644 index 6eff1afd8daf91714d6a18859667d2607e707da7..000000000000000000000000000= 0000000000000 --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.txt +++ /dev/null @@ -1,57 +0,0 @@ -Intel Service Layer Driver for Stratix10 SoC -=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D -Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard -processor system (HPS) and Secure Device Manager (SDM). When the FPGA is -configured from HPS, there needs to be a way for HPS to notify SDM the -location and size of the configuration data. Then SDM will get the -configuration data from that location and perform the FPGA configuration. - -To meet the whole system security needs and support virtual machine reques= ting -communication with SDM, only the secure world of software (EL3, Exception -Layer 3) can interface with SDM. All software entities running on other -exception layers must channel through the EL3 software whenever it needs -service from SDM. - -Intel Stratix10 service layer driver, running at privileged exception level -(EL1, Exception Layer 1), interfaces with the service providers and provid= es -the services for FPGA configuration, QSPI, Crypto and warm reset. Service = layer -driver also manages secure monitor call (SMC) to communicate with secure m= onitor -code running in EL3. - -Required properties: -------------------- -The svc node has the following mandatory properties, must be located under -the firmware node. - -- compatible: "intel,stratix10-svc" or "intel,agilex-svc" -- method: smc or hvc - smc - Secure Monitor Call - hvc - Hypervisor Call -- memory-region: - phandle to the reserved memory node. See - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - for details - -Example: -------- - - reserved-memory { - #address-cells =3D <2>; - #size-cells =3D <2>; - ranges; - - service_reserved: svcbuffer@0 { - compatible =3D "shared-dma-pool"; - reg =3D <0x0 0x0 0x0 0x1000000>; - alignment =3D <0x1000>; - no-map; - }; - }; - - firmware { - svc { - compatible =3D "intel,stratix10-svc"; - method =3D "smc"; - memory-region =3D <&service_reserved>; - }; - }; diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc= .yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fac1e955852e4f9b966c991dcfa= c56222c5f7315 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/firmware/intel,stratix10-svc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Service Layer Driver for Stratix10 SoC + +maintainers: + - Dinh Nguyen + - Mahesh Rao + +description: > + Intel Stratix10 SoC is composed of a 64 bit quad-core ARM Cortex A53 hard + processor system (HPS) and Secure Device Manager (SDM). When the FPGA is + configured from HPS, there needs to be a way for HPS to notify SDM the + location and size of the configuration data. Then SDM will get the + configuration data from that location and perform the FPGA configuration. + + To meet the whole system security needs and support virtual machine requ= esting + communication with SDM, only the secure world of software (EL3, Exception + Layer 3) can interface with SDM. All software entities running on other + exception layers must channel through the EL3 software whenever it needs + service from SDM. + + Intel Stratix10 service layer driver, running at privileged exception le= vel + (EL1, Exception Layer 1), interfaces with the service providers and prov= ides + the services for FPGA configuration, QSPI, Crypto and warm reset. Servic= e layer + driver also manages secure monitor call (SMC) to communicate with secure= monitor + code running in EL3. + +properties: + compatible: + enum: + - intel,stratix10-svc + - intel,agilex-svc + + method: + description: | + Supervisory call method to be used to communicate with the + secure service layer. + Permitted values are: + - "smc" : SMC #0, following the SMCCC + - "hvc" : HVC #0, following the SMCCC + + $ref: /schemas/types.yaml#/definitions/string-array + enum: + - smc + - hvc + + memory-region: + maxItems: 1 + description: + reserved memory region for the service layer driver to + communicate with the secure device manager. + + fpga-mgr: + $ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml + description: Optional child node for fpga manager to perform fabric co= nfiguration. + +required: + - compatible + - method + - memory-region + +additionalProperties: false + +examples: + - | + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + + service_reserved: svcbuffer@0 { + compatible =3D "shared-dma-pool"; + reg =3D <0x0 0x0 0x0 0x1000000>; + alignment =3D <0x1000>; + no-map; + }; + }; + + firmware { + svc { + compatible =3D "intel,stratix10-svc"; + method =3D "smc"; + memory-region =3D <&service_reserved>; + + fpga-mgr { + compatible =3D "intel,stratix10-soc-fpga-mgr"; + }; + }; + }; + --=20 2.35.3 From nobody Sun Dec 14 13:41:12 2025 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.21]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1F4FB21577A; Tue, 4 Feb 2025 12:58:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738673913; cv=none; b=tFTfqxwyCRgxnc9L8D8CkBTp1+JlDoqAjOqpiPD4YqRIIaW3+z9K61b3cyaNcxPTnlUomqFs7eG1+ywBTPxXXlD5Re3ADUfwDb1SwUVVg+xjQNxrdYZt+JV5vn60S6oh+fzxHCqpOLPOVmgR3F+/DdaLYK78cvR81fD836666FA= ARC-Message-Signature: i=1; a=rsa-sha256; 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d="scan'208";a="133834346" Received: from apgcp0c531115.png.altera.com ([10.244.76.209]) by fmviesa002.fm.intel.com with ESMTP; 04 Feb 2025 04:58:28 -0800 From: Mahesh Rao Date: Tue, 04 Feb 2025 20:58:07 +0800 Subject: [PATCH v3 3/3] firmware: stratix10-svc: Add of_platform_default_populate() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250204-socfpga_sip_svc_misc-v3-3-697f7f153cfa@intel.com> References: <20250204-socfpga_sip_svc_misc-v3-0-697f7f153cfa@intel.com> In-Reply-To: <20250204-socfpga_sip_svc_misc-v3-0-697f7f153cfa@intel.com> To: Moritz Fischer , Xu Yilun , Tom Rix , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Dinh Nguyen , Krzysztof Kozlowski , Wu Hao , Ho Yin , Niravkumar L Rabara Cc: linux-fpga@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mahesh Rao , Mahesh Rao X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1738673895; l=2045; i=mahesh.rao@intel.com; s=20250107; h=from:subject:message-id; bh=jpyQ7g3vF9VLx3+P43WwCMx1CgQIacytqeT6+99h4uE=; b=dJhy3C+0dSJI1aJL0X9Q54m7AsYc1IB8zBWoL3x0THtmJHt3XLmWOYgZk+85IICM6w8TgjLN6 o5DahOeqbVZAeQMNZtOt52ms2MLwUMccKjE57kGed6/tNJfk7llfSOT X-Developer-Key: i=mahesh.rao@intel.com; a=ed25519; pk=tQiFUzoKxHrQLDtWeEeaeTeJTl/UfclUHWZy1fjSiyg= Add of_platform_default_populate() to stratix10-svc driver as the firmware/svc node was moved out of soc. This fixes the failed probing of child drivers of svc node. Fixes: 23c3ebed382a ("arm64: dts: socfpga: agilex: move firmware out of soc= node") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Mahesh Rao Reviewed-by: Xu Yilun --- drivers/firmware/stratix10-svc.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/stratix10-svc.c b/drivers/firmware/stratix10-= svc.c index 3c52cb73237a43aac6984e497d75bab389e3eb9d..e3f990d888d71829f0ab22b8a59= aa7af0316bea0 100644 --- a/drivers/firmware/stratix10-svc.c +++ b/drivers/firmware/stratix10-svc.c @@ -1224,22 +1224,28 @@ static int stratix10_svc_drv_probe(struct platform_= device *pdev) if (!svc->intel_svc_fcs) { dev_err(dev, "failed to allocate %s device\n", INTEL_FCS); ret =3D -ENOMEM; - goto err_unregister_dev; + goto err_unregister_rsu_dev; } =20 ret =3D platform_device_add(svc->intel_svc_fcs); if (ret) { platform_device_put(svc->intel_svc_fcs); - goto err_unregister_dev; + goto err_unregister_rsu_dev; } =20 + ret =3D of_platform_default_populate(dev_of_node(dev), NULL, dev); + if (ret) + goto err_unregister_fcs_dev; + dev_set_drvdata(dev, svc); =20 pr_info("Intel Service Layer Driver Initialized\n"); =20 return 0; =20 -err_unregister_dev: +err_unregister_fcs_dev: + platform_device_unregister(svc->intel_svc_fcs); +err_unregister_rsu_dev: platform_device_unregister(svc->stratix10_svc_rsu); err_free_kfifo: kfifo_free(&controller->svc_fifo); @@ -1253,6 +1259,8 @@ static void stratix10_svc_drv_remove(struct platform_= device *pdev) struct stratix10_svc *svc =3D dev_get_drvdata(&pdev->dev); struct stratix10_svc_controller *ctrl =3D platform_get_drvdata(pdev); =20 + of_platform_depopulate(ctrl->dev); + platform_device_unregister(svc->intel_svc_fcs); platform_device_unregister(svc->stratix10_svc_rsu); =20 --=20 2.35.3