From nobody Thu Dec 18 18:47:16 2025 Received: from out-184.mta0.migadu.com (out-184.mta0.migadu.com [91.218.175.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D142919938D for ; Mon, 3 Feb 2025 18:31:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738607502; cv=none; b=cyEl/FvH9/vrPuVT8Q6js1j/v03CLt03+kxsEPi6L7aIihFF+oVxZOzxghke+IVhaNUtQACkLKjSeJsB6xU5txaP5Zqd20NdfMk5jmA5kwmoutmQGMGmTcvZ9/LvJgGhDJTqdn+cFlT0Vr8I8HDl2c4x2vUIvEtZlYsF7CXMbq8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738607502; c=relaxed/simple; bh=xY+mxWUIwcoJgnhfGlaSlV532s+yW7KbR+gZRh/8eTo=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Pfixkocc7qRKJOiyZBFfHJcpiaNNW/jKpDzZw3XWAB986qTtg+hmy5Titu7/fD+F69Yu0ZQZZRnuLudLVpMIiWeIHE7onfzRXfnYOC5VGOUaf+Sr07SXgcQfdO9YitKUwziJ32NB9kJJSd5iUzbfYl+0KrN/umD8yX4nTfmXgG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=svjl2qkN; arc=none smtp.client-ip=91.218.175.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="svjl2qkN" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1738607493; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Sf6sBMMAV5XjKoDS/ngB0As3YdpZ4fzfIUulH+JWe4I=; b=svjl2qkNOXxx/ORuRlNmH1+hK72/bHVIzo5KboZBHF8OnpcNXt7NFJ0eQxA+u+YTDVo5n+ RA7dJUgkWmIy3ZtCWhA1clKAjEYG684wATyovmhHkDl+8pC0LGR65BUJR4jdRLa6mprVAi 3uO7IaBXWr6xqKLNgLDamGve0S/zQ9Q= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton , Janne Grunau Subject: [PATCH v2 01/14] drivers/perf: apple_m1: Refactor event select/filter configuration Date: Mon, 3 Feb 2025 10:30:58 -0800 Message-Id: <20250203183111.191519-2-oliver.upton@linux.dev> In-Reply-To: <20250203183111.191519-1-oliver.upton@linux.dev> References: <20250203183111.191519-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" Supporting guest mode events will necessitate programming two event filters. Prepare by splitting up the programming of the event selector + event filter into separate headers. Opportunistically replace RMW patterns with sysreg_clear_set_s(). Tested-by: Janne Grunau Signed-off-by: Oliver Upton --- arch/arm64/include/asm/apple_m1_pmu.h | 1 + drivers/perf/apple_m1_cpu_pmu.c | 52 ++++++++++++++++----------- 2 files changed, 33 insertions(+), 20 deletions(-) diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm= /apple_m1_pmu.h index 99483b19b99f..02e05d05851f 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -37,6 +37,7 @@ #define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44) =20 #define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) +#define SYS_IMP_APL_PMCR1_EL12 sys_reg(3, 1, 15, 7, 2) #define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) #define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) #define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index 06fd317529fc..cea80afd1253 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -327,11 +327,10 @@ static void m1_pmu_disable_counter_interrupt(unsigned= int index) __m1_pmu_enable_counter_interrupt(index, false); } =20 -static void m1_pmu_configure_counter(unsigned int index, u8 event, - bool user, bool kernel) +static void __m1_pmu_configure_event_filter(unsigned int index, bool user, + bool kernel) { - u64 val, user_bit, kernel_bit; - int shift; + u64 clear, set, user_bit, kernel_bit; =20 switch (index) { case 0 ... 7: @@ -346,19 +345,24 @@ static void m1_pmu_configure_counter(unsigned int ind= ex, u8 event, BUG(); } =20 - val =3D read_sysreg_s(SYS_IMP_APL_PMCR1_EL1); - + clear =3D set =3D 0; if (user) - val |=3D user_bit; + set |=3D user_bit; else - val &=3D ~user_bit; + clear |=3D user_bit; =20 if (kernel) - val |=3D kernel_bit; + set |=3D kernel_bit; else - val &=3D ~kernel_bit; + clear |=3D kernel_bit; =20 - write_sysreg_s(val, SYS_IMP_APL_PMCR1_EL1); + sysreg_clear_set_s(SYS_IMP_APL_PMCR1_EL1, clear, set); +} + +static void __m1_pmu_configure_eventsel(unsigned int index, u8 event) +{ + u64 clear =3D 0, set =3D 0; + int shift; =20 /* * Counters 0 and 1 have fixed events. For anything else, @@ -371,21 +375,29 @@ static void m1_pmu_configure_counter(unsigned int ind= ex, u8 event, break; case 2 ... 5: shift =3D (index - 2) * 8; - val =3D read_sysreg_s(SYS_IMP_APL_PMESR0_EL1); - val &=3D ~((u64)0xff << shift); - val |=3D (u64)event << shift; - write_sysreg_s(val, SYS_IMP_APL_PMESR0_EL1); + clear |=3D (u64)0xff << shift; + set |=3D (u64)event << shift; + sysreg_clear_set_s(SYS_IMP_APL_PMESR0_EL1, clear, set); break; case 6 ... 9: shift =3D (index - 6) * 8; - val =3D read_sysreg_s(SYS_IMP_APL_PMESR1_EL1); - val &=3D ~((u64)0xff << shift); - val |=3D (u64)event << shift; - write_sysreg_s(val, SYS_IMP_APL_PMESR1_EL1); + clear |=3D (u64)0xff << shift; + set |=3D (u64)event << shift; + sysreg_clear_set_s(SYS_IMP_APL_PMESR1_EL1, clear, set); break; } } =20 +static void m1_pmu_configure_counter(unsigned int index, unsigned long con= fig_base) +{ + bool kernel =3D config_base & M1_PMU_CFG_COUNT_KERNEL; + bool user =3D config_base & M1_PMU_CFG_COUNT_USER; + u8 evt =3D config_base & M1_PMU_CFG_EVENT; + + __m1_pmu_configure_event_filter(index, user, kernel); + __m1_pmu_configure_eventsel(index, evt); +} + /* arm_pmu backend */ static void m1_pmu_enable_event(struct perf_event *event) { @@ -400,7 +412,7 @@ static void m1_pmu_enable_event(struct perf_event *even= t) m1_pmu_disable_counter(event->hw.idx); isb(); =20 - m1_pmu_configure_counter(event->hw.idx, evt, user, kernel); + m1_pmu_configure_counter(event->hw.idx, event->hw.config_base); m1_pmu_enable_counter(event->hw.idx); m1_pmu_enable_counter_interrupt(event->hw.idx); isb(); --=20 2.39.5