From nobody Thu Dec 18 18:47:15 2025 Received: from out-171.mta0.migadu.com (out-171.mta0.migadu.com [91.218.175.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D9A4F20B7E6 for ; Mon, 3 Feb 2025 18:32:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738607556; cv=none; b=R09FPcWMhrG9GCABVEzs5JBu3GV/MeZueVs9UaowtdXRPedIFbADdw6PDTTCnnO/utRJ1Mlxt+uui/MuZKoVOepdHmy7GeUTKBd4SIhfYQPblxmPVwEwRdbrv8xqrNVKIrK6gi3echSXRHzUc0YCDtZWgCbjySfBJTFA2sz2G3U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738607556; c=relaxed/simple; bh=gfVeTaYGvJgjF3+5dv8ThgPZCvgtXsyI4dPTBxdrunc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=eeZC2azujISkQuKw8KPqRYe0IRTbxVGXTcnIWYZodP3tB9DCx4aB/qJ5Rgi/0Qmm5eF/jWwK6GPN96YOKBdqTRxCfTktmLzOwXbFMrmTVkqbD6q23ZC8jRpzBtUQSg7ySufCUVucsGnjcECR/oMnca/TO/gZ4XkijO0i9SEu1K0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=URmdA1um; arc=none smtp.client-ip=91.218.175.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="URmdA1um" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1738607552; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fk4znlvn6GbakMwTeJliB+Oo4bK3C8L8Zl+LfXy3Y/M=; b=URmdA1um0bGgiad2xuSYS+M2AFDxdiAhjsORqGvAvOLpYPM96w6DIyJyZrbs9uCva4jhMG ZuyF7k8yj+JTEyYqMR9Q0//F1Nq/b73X0txi8cCNdii5yMQKpGc50VkAT6DK3Jj/tmpDnw 59L15zZAd+LzcseSJ7p1t5+Iy1XS9oA= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Oliver Upton , Janne Grunau Subject: [PATCH v2 10/14] KVM: arm64: Move PMUVer filtering into KVM code Date: Mon, 3 Feb 2025 10:31:07 -0800 Message-Id: <20250203183111.191519-11-oliver.upton@linux.dev> In-Reply-To: <20250203183111.191519-1-oliver.upton@linux.dev> References: <20250203183111.191519-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The supported guest PMU version on a particular platform is ultimately a KVM decision. Move PMUVer filtering into KVM code. Tested-by: Janne Grunau Signed-off-by: Oliver Upton --- arch/arm64/include/asm/cpufeature.h | 23 ----------------------- arch/arm64/kvm/pmu-emul.c | 15 +++++++++------ 2 files changed, 9 insertions(+), 29 deletions(-) diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/c= pufeature.h index 0eff048848b8..c4326f1cb917 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -525,29 +525,6 @@ cpuid_feature_extract_unsigned_field(u64 features, int= field) return cpuid_feature_extract_unsigned_field_width(features, field, 4); } =20 -/* - * Fields that identify the version of the Performance Monitors Extension = do - * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825, - * "Alternative ID scheme used for the Performance Monitors Extension vers= ion". - */ -static inline u64 __attribute_const__ -cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap) -{ - u64 val =3D cpuid_feature_extract_unsigned_field(features, field); - u64 mask =3D GENMASK_ULL(field + 3, field); - - /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */ - if (val =3D=3D ID_AA64DFR0_EL1_PMUVer_IMP_DEF) - val =3D 0; - - if (val > cap) { - features &=3D ~mask; - features |=3D (cap << field) & mask; - } - - return features; -} - static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp) { return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift); diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 3048e22c240b..57ef4f2814fc 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -1238,13 +1238,16 @@ int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, = struct kvm_device_attr *attr) =20 u8 kvm_arm_pmu_get_pmuver_limit(void) { - u64 tmp; + unsigned int pmuver; =20 - tmp =3D read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1); - tmp =3D cpuid_feature_cap_perfmon_field(tmp, - ID_AA64DFR0_EL1_PMUVer_SHIFT, - ID_AA64DFR0_EL1_PMUVer_V3P5); - return FIELD_GET(ARM64_FEATURE_MASK(ID_AA64DFR0_EL1_PMUVer), tmp); + pmuver =3D SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, + read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1)); + + /* Treat IMPLEMENTATION DEFINED functionality as unimplemented */ + if (pmuver =3D=3D ID_AA64DFR0_EL1_PMUVer_IMP_DEF) + return 0; + + return min(pmuver, ID_AA64DFR0_EL1_PMUVer_V3P5); } =20 /** --=20 2.39.5